WO2008126207A1 - 半導体集積回路の設計方法 - Google Patents

半導体集積回路の設計方法 Download PDF

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Publication number
WO2008126207A1
WO2008126207A1 PCT/JP2007/056381 JP2007056381W WO2008126207A1 WO 2008126207 A1 WO2008126207 A1 WO 2008126207A1 JP 2007056381 W JP2007056381 W JP 2007056381W WO 2008126207 A1 WO2008126207 A1 WO 2008126207A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
design data
semiconductor integrated
accordance
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/056381
Other languages
English (en)
French (fr)
Inventor
Takashi Shikata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Semiconductor Ltd filed Critical Fujitsu Semiconductor Ltd
Priority to PCT/JP2007/056381 priority Critical patent/WO2008126207A1/ja
Priority to JP2009508758A priority patent/JP5012890B2/ja
Publication of WO2008126207A1 publication Critical patent/WO2008126207A1/ja
Priority to US12/556,649 priority patent/US8250504B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/06—Power analysis or power optimisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

　パワーゲーティング制御信号に応じて論理回路に電源電圧を供給するためのパワーゲーティング回路及びクランプ制御信号に応じて前記論理回路の出力信号をクランプするための第１のクランプ回路（２０４）を有する設計データを準備する準備ステップと、前記設計データを検証するために、前記設計データに対して、前記パワーゲーティング回路の代わりに、前記パワーゲーティング制御信号に応じて前記論理回路の出力信号をマスクするための第１のマスク回路（５０１，５０２）を追加した設計データを生成する生成ステップとを有することを特徴とする半導体集積回路の設計方法が提供される。
PCT/JP2007/056381 2007-03-27 2007-03-27 半導体集積回路の設計方法 Ceased WO2008126207A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/JP2007/056381 WO2008126207A1 (ja) 2007-03-27 2007-03-27 半導体集積回路の設計方法
JP2009508758A JP5012890B2 (ja) 2007-03-27 2007-03-27 半導体集積回路の設計方法
US12/556,649 US8250504B2 (en) 2007-03-27 2009-09-10 Designing method of semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/056381 WO2008126207A1 (ja) 2007-03-27 2007-03-27 半導体集積回路の設計方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/556,649 Continuation US8250504B2 (en) 2007-03-27 2009-09-10 Designing method of semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
WO2008126207A1 true WO2008126207A1 (ja) 2008-10-23

Family

ID=39863390

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/056381 Ceased WO2008126207A1 (ja) 2007-03-27 2007-03-27 半導体集積回路の設計方法

Country Status (3)

Country Link
US (1) US8250504B2 (ja)
JP (1) JP5012890B2 (ja)
WO (1) WO2008126207A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012039240A (ja) * 2010-08-04 2012-02-23 Elpida Memory Inc 半導体装置及びその制御方法
CN114818568A (zh) * 2022-05-05 2022-07-29 东南大学 针对静态时序分析中ccs模型回代求解的fpga硬件加速方法

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI489444B (zh) 2012-07-17 2015-06-21 Etron Technology Inc 應用於嵌入式顯示埠的動態隨機存取記憶體
US12184444B2 (en) 2017-02-10 2024-12-31 Johnson Controls Technology Company Space graph based dynamic control for buildings
US10601217B2 (en) * 2017-04-27 2020-03-24 Qualcomm Incorporated Methods for detecting an imminent power failure in time to protect local design state
WO2019018304A1 (en) 2017-07-17 2019-01-24 Johnson Controls Technology Company SYSTEMS AND METHODS FOR BUILDING SIMULATION ON THE BASIS OF AN AGENT FOR OPTIMAL CONTROL
US10535394B2 (en) 2017-07-20 2020-01-14 Samsung Electronics Co., Ltd. Memory device including dynamic voltage and frequency scaling switch and method of operating the same
KR102558422B1 (ko) * 2018-11-07 2023-07-24 에스케이하이닉스 주식회사 파워 게이팅 시스템

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006031408A (ja) * 2004-07-16 2006-02-02 Renesas Technology Corp エミュレータおよび半導体集積回路装置
JP2006209162A (ja) * 2005-01-25 2006-08-10 Renesas Technology Corp 論理検証装置

Family Cites Families (4)

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Publication number Priority date Publication date Assignee Title
US4217618A (en) * 1977-10-25 1980-08-12 Boney George R Thyristor firing circuit module with integral optical isolation, dv/dt limitation, and bidirectional voltage transient suppression
US5051572A (en) * 1990-04-06 1991-09-24 Mcdonnell Douglas Corporation Photomultiplier gating circuit
US7112773B2 (en) * 2004-08-24 2006-09-26 Burle Technologies, Inc. Bleeder powered gating amplifier
US20090315399A1 (en) * 2008-06-20 2009-12-24 Fujitsu Microelectronics Limited Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006031408A (ja) * 2004-07-16 2006-02-02 Renesas Technology Corp エミュレータおよび半導体集積回路装置
JP2006209162A (ja) * 2005-01-25 2006-08-10 Renesas Technology Corp 論理検証装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012039240A (ja) * 2010-08-04 2012-02-23 Elpida Memory Inc 半導体装置及びその制御方法
CN114818568A (zh) * 2022-05-05 2022-07-29 东南大学 针对静态时序分析中ccs模型回代求解的fpga硬件加速方法

Also Published As

Publication number Publication date
US20100005439A1 (en) 2010-01-07
JP5012890B2 (ja) 2012-08-29
JPWO2008126207A1 (ja) 2010-07-22
US8250504B2 (en) 2012-08-21

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