WO2008124671A1 - Robust esd cell - Google Patents

Robust esd cell Download PDF

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Publication number
WO2008124671A1
WO2008124671A1 PCT/US2008/059538 US2008059538W WO2008124671A1 WO 2008124671 A1 WO2008124671 A1 WO 2008124671A1 US 2008059538 W US2008059538 W US 2008059538W WO 2008124671 A1 WO2008124671 A1 WO 2008124671A1
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WO
WIPO (PCT)
Prior art keywords
emitter
esd
base
pinched
type materials
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2008/059538
Other languages
French (fr)
Inventor
Moshe Gerstenhaber
Padraig Cooney
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Analog Devices Inc
Original Assignee
Analog Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Analog Devices Inc filed Critical Analog Devices Inc
Publication of WO2008124671A1 publication Critical patent/WO2008124671A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/40—Vertical BJTs
    • H10D10/421—Vertical BJTs having both emitter-base and base-collector junctions ending at the same surface of the body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H10D10/051—Manufacture or treatment of vertical BJTs
    • H10D10/054—Forming extrinsic base regions on silicon substrate after insulating device isolation in vertical BJTs having single crystalline emitter, collector or base regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H10D10/051—Manufacture or treatment of vertical BJTs
    • H10D10/056—Manufacture or treatment of vertical BJTs of vertical BJTs having the main current going through the whole substrate, e.g. power BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/133—Emitter regions of BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/01—Manufacture or treatment
    • H10D8/041—Manufacture or treatment of multilayer diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/711—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using bipolar transistors as protective elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/133—Emitter regions of BJTs
    • H10D62/135—Non-interconnected multi-emitter structures

Definitions

  • FIG. 1 is a cross-sectional view of a conventional bipolar transistor-based ESD protection structure 10.
  • Conventional bipolar transistor-based ESD protection structure 10 includes a P-type substrate 12, an N-type collector region 14, a P-type base region 16 (e.g., a P-type Si-Ge base region) and an N-type polysilicon emitter 18.
  • the conventional bipolar transistor-based ESD protection structure 10 also includes electrical isolation regions 20 and 22.
  • a metal base contact 24 makes contact with the P-type base region 16 via polysilicon line 26.
  • a metal emitter contact 28 is in contact with the N-type polysilicon emitter 18, while a metal collector contact 30 is in contact with the N-type collector region 14.
  • the metal base contact 24, the metal emitter contact 28 and the metal collector contact 30 each extends through dielectric layer 32.
  • Electrical schematics illustrating this conventional bipolar transistor-based ESD protection structure 10 arranged in a grounded base bipolar transistor-based ESD protection device and a Zener Triggered bipolar transistor-based ESD protection device are provided in FIGS. 2A and 2B, respectively.
  • an electric discharge device includes a bipolar transistor configuration comprising a base, an emitter, and a collector. At least one pinched resistor is formed in a region comprising both the base and emitter so as to produce a pinched resistive area that develops a voltage once the bipolar transistor experiences junction breakdown.
  • a method of forming an electric discharge device includes providing a bipolar transistor configuration comprising a base, an emitter, and a collector. Also, the method includes forming at least one pinched resistor in a region comprising both the base and emitter so as to produce a pinched resistive area that develops a voltage once the bipolar transistor experiences junction breakdown.
  • FIG. 1 is a schematic diagram of a conventional ESD device
  • FIGs. 2A-2B are circuit diagrams representing conventional ESD devices
  • FIG. 3 is a schematic diagram illustrating a top view of the inventive ESD device
  • FIG. 4 is a schematic diagram illustrating a top view of another of the inventive ESD device.
  • FIG. 5 is a circuit diagram representing the inventive ESD device. DETAILED DESCRIPTION QF THE INVENTION
  • the invention involves the use of a pinched resistive area that develops a voltage once junction breakdown occurs.
  • FIG. 3 shows the inventive ESD device 40 having a pinched resistive area 50.
  • the ESD 40 includes a N-type collector region 44, a P-type base region 46, and N+-type emitter regions 48. Note the ESD device 40 resembles that of a bipolar transistor based
  • the ESD device 40 can include a P-type material collector, a N-type base, and P+-type emitter.
  • the invention includes a pinched resistive region 50 formed under the emitter regions 48 and the exposed P-type materials comprising the hole 42 and base region 46.
  • a hole 42 is formed in an area comprising the emitter regions 48 leaving an exposed region of the base region 46.
  • the materials inside the hole 42 is connected to the emitter region 48 using an interconnect, such as Al or the like.
  • the collector 44 is connected to a respective node to be protected and the hole 42 and the emitter regions 48 can be connected to ground. Another way also is the hole 42 and the emitter regions 48 can be connected to a node to be protected and the collector 44 can be connected to a positive supply.
  • the hole 42 is circular shaped however in other embodiments the shape can vary depending on how much resistance is needed and materials used to form the hole 42, thus one can control the resistive value of the ESD device 40.
  • the pinched resistive region 50 develops a voltage once junction breakdown occurs. If the voltage that is generated across the pinched resistive region 50 is of sufficient magnitude, it will forward bias the pn junction between the base region 46 and emitter regions 48, which creates a normal bipolar transistor action so as to allow current to flow only thru the pinched resistive region. The excess current is pumped into the collector region 44. Note the ESD device 40 resembles a bipolar transistor. The result of such a configuration is reduced surface power density and faster turn-on of the ESD device 40 which yields higher reliability and higher ESD rating.
  • FIG. 4 shows the top view of the inventive ESD device 51.
  • the ESD device 51 includes a collector region 52 which is n-type.
  • the collector region includes a base region 54 that includes emitter regions 58.
  • Each of the emitter regions 58 includes a hole 60 which produces pinched resistive regions similar to pinched resistive region 50, as shown in FIG. 3.
  • the number of emitter regions 58 can vary depending on the size of base region 54. As more pinched resistive regions are formed on a base-emitter region the more uniform the injection of the protection device become, hi this embodiment, the hole 60 is circular shaped however in other embodiments the shape can vary depending on how much resistance is needed and materials used to form the base region 54, thus one can control the resistive value of the ESD device 51.
  • the pinched resistor 74 develops a voltage once junction breakdown occurs. If the voltage that is generated across the pinched resistor 74 is of sufficient magnitude, it will forward bias the pn junction between the base 80 and emitter 78, which creates a normal bipolar transistor action. The excess current is pumped into the collector 78.

Landscapes

  • Bipolar Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)

Abstract

An electric discharge device includes a bipolar transistor configuration comprising a base (46), an emitter (48), and a collector (44). At least one pinched resistor (50) is formed in a region comprising both the base and emitter so as to produce a pinched resistive area that develops a voltage once the bipolar transistor experiences junction breakdown.

Description

ROBUST ESD CELL PRIORITY INFORMATION
The present application claims priority to U.S. Utility Application No. 11/697,814, filed on April 9, 2007, which is incorporated herein by reference in its entirety.
BACKGROUND OF THE INVENTION
The invention relates to the field of ESD cells, in particular to an ESD cell having a pinched resistive area. FIG. 1 is a cross-sectional view of a conventional bipolar transistor-based ESD protection structure 10. Conventional bipolar transistor-based ESD protection structure 10 includes a P-type substrate 12, an N-type collector region 14, a P-type base region 16 (e.g., a P-type Si-Ge base region) and an N-type polysilicon emitter 18. The conventional bipolar transistor-based ESD protection structure 10 also includes electrical isolation regions 20 and 22. A metal base contact 24 makes contact with the P-type base region 16 via polysilicon line 26. A metal emitter contact 28 is in contact with the N-type polysilicon emitter 18, while a metal collector contact 30 is in contact with the N-type collector region 14. The metal base contact 24, the metal emitter contact 28 and the metal collector contact 30 each extends through dielectric layer 32. Electrical schematics illustrating this conventional bipolar transistor-based ESD protection structure 10 arranged in a grounded base bipolar transistor-based ESD protection device and a Zener Triggered bipolar transistor-based ESD protection device are provided in FIGS. 2A and 2B, respectively. SUMMARY OF THE INVENTION
According to one aspect of the invention, there is provided an electric discharge device (ESD). The ESD includes a bipolar transistor configuration comprising a base, an emitter, and a collector. At least one pinched resistor is formed in a region comprising both the base and emitter so as to produce a pinched resistive area that develops a voltage once the bipolar transistor experiences junction breakdown.
According to another aspect of the invention, there is provided a method of forming an electric discharge device. The method includes providing a bipolar transistor configuration comprising a base, an emitter, and a collector. Also, the method includes forming at least one pinched resistor in a region comprising both the base and emitter so as to produce a pinched resistive area that develops a voltage once the bipolar transistor experiences junction breakdown.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic diagram of a conventional ESD device; FIGs. 2A-2B are circuit diagrams representing conventional ESD devices; FIG. 3 is a schematic diagram illustrating a top view of the inventive ESD device; FIG. 4 is a schematic diagram illustrating a top view of another of the inventive ESD device; and
FIG. 5 is a circuit diagram representing the inventive ESD device. DETAILED DESCRIPTION QF THE INVENTION
The invention involves the use of a pinched resistive area that develops a voltage once junction breakdown occurs.
FIG. 3 shows the inventive ESD device 40 having a pinched resistive area 50. The ESD 40 includes a N-type collector region 44, a P-type base region 46, and N+-type emitter regions 48. Note the ESD device 40 resembles that of a bipolar transistor based
ESD device. In other embodiments, the ESD device 40 can include a P-type material collector, a N-type base, and P+-type emitter.
The invention includes a pinched resistive region 50 formed under the emitter regions 48 and the exposed P-type materials comprising the hole 42 and base region 46.
A hole 42 is formed in an area comprising the emitter regions 48 leaving an exposed region of the base region 46. The materials inside the hole 42 is connected to the emitter region 48 using an interconnect, such as Al or the like. The collector 44 is connected to a respective node to be protected and the hole 42 and the emitter regions 48 can be connected to ground. Another way also is the hole 42 and the emitter regions 48 can be connected to a node to be protected and the collector 44 can be connected to a positive supply.
In this embodiment, the hole 42 is circular shaped however in other embodiments the shape can vary depending on how much resistance is needed and materials used to form the hole 42, thus one can control the resistive value of the ESD device 40.
The pinched resistive region 50 develops a voltage once junction breakdown occurs. If the voltage that is generated across the pinched resistive region 50 is of sufficient magnitude, it will forward bias the pn junction between the base region 46 and emitter regions 48, which creates a normal bipolar transistor action so as to allow current to flow only thru the pinched resistive region. The excess current is pumped into the collector region 44. Note the ESD device 40 resembles a bipolar transistor. The result of such a configuration is reduced surface power density and faster turn-on of the ESD device 40 which yields higher reliability and higher ESD rating.
FIG. 4 shows the top view of the inventive ESD device 51. The ESD device 51 includes a collector region 52 which is n-type. The collector region includes a base region 54 that includes emitter regions 58. Each of the emitter regions 58 includes a hole 60 which produces pinched resistive regions similar to pinched resistive region 50, as shown in FIG. 3. In other embodiments, the number of emitter regions 58 can vary depending on the size of base region 54. As more pinched resistive regions are formed on a base-emitter region the more uniform the injection of the protection device become, hi this embodiment, the hole 60 is circular shaped however in other embodiments the shape can vary depending on how much resistance is needed and materials used to form the base region 54, thus one can control the resistive value of the ESD device 51.
FIG. 5 shows a circuit representation of the inventive ESD device 70. The ESD device 70 includes a bipolar transistor 72 and a pinched resistor 74. The bipolar transistor includes a collector 76, an emitter 78, and a base 80. The base 80 of the transistor 72 is coupled to the pinched resistor 74. The pinched resistor 74 is also coupled to the emitter 78 of the bipolar transistor 72. Note the emitter 78 can be coupled to ground and the collector 76 can be coupled to a voltage source.
The pinched resistor 74 develops a voltage once junction breakdown occurs. If the voltage that is generated across the pinched resistor 74 is of sufficient magnitude, it will forward bias the pn junction between the base 80 and emitter 78, which creates a normal bipolar transistor action. The excess current is pumped into the collector 78.
Although the present invention has been shown and described with respect to several preferred embodiments thereof, various changes, omissions and additions to the form and detail thereof, may be made therein, without departing from the spirit and scope of the invention.
What is claimed is:

Claims

1. An electric discharge device (ESD) comprising: a bipolar transistor configuration comprising a base, an emitter, and a collector; and at least one pinched resistor that is formed in a region comprising both said base and emitter so as to produce a pinched resistive area that develops a voltage once said bipolar transistor experiences junction breakdown so as to allow current to flow only thru said pinched resistive region.
2. The ESD of claim 1, wherein said pinched resistor is formed using at least one circular shape opening on said emitter.
3. The ESD of claim 1, wherein said pinched resistor is formed using a plurality of circular shape openings on said emitter.
4. The ESD of claim 1, wherein said voltage forward a pn junction formed by said base and emitter.
5. The ESD of claim 3, wherein said circular shape openings comprise the same materials said base.
6. The ESD of claim 1, wherein said collector comprises N-type materials.
7. The ESD of claim 6, wherein said base comprises P-type materials.
8. The ESD of claim 7, wherein said emitter comprises N+-type materials.
9. The ESD of claim 1, wherein said collector comprises P-type materials.
10. The ESD of claim 9, wherein said base comprises N-type materials.
11. The ESD of claim 10, wherein said emitter comprises P+-type materials.
12. A method of forming an electric discharge device (ESD) comprising: providing a bipolar transistor configuration comprising a base, an emitter, and a collector; and forming at least one pinched resistor in a region comprising both said base and emitter so as to produce a pinched resistive area that develops a voltage once said bipolar transistor experiences junction breakdown.
13. The method of claim 12, wherein said pinched resistor is formed using at least one circular shape opening on said emitter.
14. The method of claim 12, wherein said pinched resistor is formed using a plurality of circular shape openings on said emitter.
15. The method of claim 12, wherein said voltage forward a pn junction formed by said base and emitter.
16. The method of claim 14, wherein said circular shape openings comprise the same materials said base.
17. The method of claim 1, wherein said collector comprises N-type materials.
18. The method of claim 17, wherein said base comprises P-type materials.
19. The method of claim 18, wherein said emitter comprise N+-type materials.
20. The method of claim 12, wherein said collector comprises P-type materials.
21. The method of claim 20, wherein said base comprises N-type materials.
22. The method of claim 21, wherein said emitter comprises P+-type materials.
PCT/US2008/059538 2007-04-09 2008-04-07 Robust esd cell Ceased WO2008124671A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/697,814 US7656009B2 (en) 2007-04-09 2007-04-09 Robust ESD cell
US11/697,814 2007-04-09

Publications (1)

Publication Number Publication Date
WO2008124671A1 true WO2008124671A1 (en) 2008-10-16

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TW (1) TWI365530B (en)
WO (1) WO2008124671A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7994747B2 (en) * 2007-07-13 2011-08-09 Seagate Technology Llc Suppressing phased motor voltage transients on disconnect

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2206353A1 (en) * 1971-02-11 1972-10-26 Motorola Inc., Franklin Park, 111. (V.StA.) Integrated transistor and emitter-collector diode
JPS58199563A (en) * 1982-05-17 1983-11-19 Sanyo Electric Co Ltd Transistor with damper diode
JP2005235844A (en) * 2004-02-17 2005-09-02 Fuji Electric Device Technology Co Ltd Semiconductor device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4659979A (en) * 1985-11-27 1987-04-21 Burr-Brown Corporation High voltage current source circuit and method
US5212618A (en) * 1990-05-03 1993-05-18 Linear Technology Corporation Electrostatic discharge clamp using vertical NPN transistor
US6777784B1 (en) 2000-10-17 2004-08-17 National Semiconductor Corporation Bipolar transistor-based electrostatic discharge (ESD) protection structure with a heat sink

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2206353A1 (en) * 1971-02-11 1972-10-26 Motorola Inc., Franklin Park, 111. (V.StA.) Integrated transistor and emitter-collector diode
JPS58199563A (en) * 1982-05-17 1983-11-19 Sanyo Electric Co Ltd Transistor with damper diode
JP2005235844A (en) * 2004-02-17 2005-09-02 Fuji Electric Device Technology Co Ltd Semiconductor device

Also Published As

Publication number Publication date
TW200847389A (en) 2008-12-01
TWI365530B (en) 2012-06-01
US20080246115A1 (en) 2008-10-09
US7656009B2 (en) 2010-02-02

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