WO2008121521A1

WO2008121521A1 - Phase noise compensated voltage controlled oscillator

Info

Publication number: WO2008121521A1
Application number: PCT/US2008/056667
Authority: WO
Inventors: Peter Larsen Soren; Henrik Lai Hansen
Original assignee: Motorola, Inc.
Priority date: 2007-03-30
Filing date: 2008-03-12
Publication date: 2008-10-09
Also published as: GB0706192D0; GB2447961A; GB2447961B

Abstract

A VCO (voltage controlled oscillator) circuit includes a differential mode VCO, a phase locked loop for providing a frequency control voltage to control an operating frequency of the VCO and a negative feedback control loop operable to receive and process a differential output signal produced by the VCO. The control loop includes a differential mode frequency discriminator operable to detect a phase noise content of the received signal and to deliver to the VCO via the feedback loop an error control signal adapted to cancel the detected phase noise content. The VCO includes at least one voltage controlled device, a first input connection for applying the frequency control voltage to the at least one voltage controlled device and a second input connection for applying the error control signal, separately from the frequency control voltage, to at least one voltage controlled device of the VCO.

Description

PHASE NOISE COMPENSATED VOLTAGE CONTROLLED

OSCILLATOR

FIELD OF THE INVENTION

The present invention relates to a voltage controlled oscillator (VCO) circuit. In particular, the invention relates to a VCO circuit useful as a synthesizer circuit for generating a stable frequency RF signal for use in an RF communications transmitter or receiver .

BACKGROUND OF THE INVENTION

Carrier frequency signals in RF communications transmitters are conventionally generated by a frequency synthesizer circuit including a VCO connected in a phase locked loop (PLL) . The phase locked loop, including the VCO, provides an appropriate stable output signal at a precisely defined frequency which may be selected by design. The VCO usually includes a resonator portion which provides oscillations in a given frequency band which includes the output signal frequency, a tuning portion, e.g. employing one or more voltage controlled devices such as varactors, which provide tuning of the output frequency in accordance with an input control voltage and an amplifier or active portion to sustain oscillations in the VCO.

RF synthesizer circuits may also be used in RF receivers to provide accurate reference (local oscillator) frequency signals, e.g. for demodulation of a received signal. In many cases, the receiver and transmitter are combined in a single transceiver unit and the same synthesizer may be used for both the transmitter and receiver portions.

In the prior art, synthesizers for high performance applications, e.g. RF high power transmitters or high sensitivity receivers for use in radio base transceiver stations in mobile wireless communications systems, have conventionally employed VCOs in which the resonator portion, the tuning portion and the amplifier portion are provided using discrete components. These components are soldered together on a PCB (printed circuit board) . This conventional approach has shown several disadvantages. The VCO parts have to be acquired and handled separately prior to assembly. The VCO is costly to assemble from its constituent parts. The VCO is constructed separately from the PLL circuits and the combination of the two is time consuming and costly to assemble. Assembly of the VCO and its combination with the PLL circuits is an intricate operation which is prone to assembly errors. The VCO suffers from the problem of Microphonics' in which mechanical vibration of the PCB causes electrical noise in the VCO by piezoelectric modulation. Furthermore, the phase noise performance of the VCO is reduced to an undesirably low level by reduction of the Q-factor of the resonator portion .

It is known in the prior art to provide a VCO in the form of an integrated circuit. This helps to solve the problems obtained with the use of discrete components as described above. However, the problem of reduced phase noise performance mentioned above is increased with such VCOs, particularly for VCOs having a frequency of operation greater than 1 GHz, especially greater than 5 GHz .

A VCO having an associated frequency discriminator to detect phase noise of the VCO and to provide a feedback signal aimed at reducing phase noise in the VCO is described in the prior art by Meyer in US-A- 4,336,505. The circuit arrangement described in US-A- 4,336,505 provides a single control voltage to the VCO by combining a control voltage produced by an associated phase locked loop required to set the frequency of the VCO with the feedback signal from the discriminator. The circuit arrangement is not suitable for use with a VCO in the form of an integrated circuit.

SUMN[ARY OF THE INVENTION

According to the present invention there is provided a VCO circuit as defined in claim 1 of the accompanying claims.

Embodiments of the present invention will now be described by way of example with reference to the accompanying drawings . BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, in which like reference numerals refer to identical or functionally similar elements throughout the separate views and which, together with the accompanying description later, serve to further illustrate various embodiments and to explain various principles and advantages of the embodiments of the present invention. In the accompanying drawings:

FIG. 1 is a schematic circuit diagram illustrating a frequency synthesizer circuit in accordance with an embodiment of the present invention.

FIG. 2 is a schematic graph of signal power versus frequency illustrating how phase noise of the VCO of the circuit shown in FIG. 1 is reduced using the circuit of FIG. 1.

FIG. 3 schematically depicts an integrated circuit which includes components of the synthesizer circuit of FIG. 1 provided in an area of the integrated circuit.

FIG. 4 is a schematic circuit diagram of an illustrative generalised differential mode VCO useful in the synthesizer circuit of FIG. 1.

FIG. 5 is a schematic circuit diagram of a more detailed illustrative differential mode VCO useful in the synthesizer circuit of FIG. 1.

FIG. 6 is a schematic circuit diagram illustrating a differential mode circuit useful to serve as the differential mode frequency discriminator in the synthesizer circuit of FIG. 1.

FIG. 7 is a schematic waveform diagram illustrating in simple form operation of the circuit of FIG. 6.

FIG. 8 is a schematic circuit diagram illustrating an alternative differential mode circuit useful to serve as the differential mode frequency discriminator in the synthesizer circuit of FIG. 1.

FIG. 9 is a schematic circuit diagram illustrating a further alternative differential mode circuit useful to serve as the differential mode frequency discriminator in the synthesizer circuit of FIG. 1.

FIG. 10 is an example of an active loop filter useful in the noise suppressing control loop of the circuit of FIG. 1.

FIG. 11 is an example of an alternative active loop filter useful in the control loop of the circuit of FIG. 1.

FIG. 12 is a schematic circuit diagram of an illustrative differential mode envelope detector useful in the frequency discriminator circuit described with reference to FIG. 6.

FIG. 13 is an example of another illustrative envelope detector useful in the frequency discriminator circuit described with reference to FIG. 6.

FIG. 14 is an example of a phase detector useful in the frequency discriminator circuit described with reference to FIG. 6. FIG. 15 schematically depicts a construction of an integrated circuit which includes components of the synthesizer circuit of FIG. 1 provided in an integrated circuit together with a separate delay element.

FIG. 16 is a graph of phase noise in dB/Hz plotted against noise offset frequency in Hz illustrating improvements in VCO phase noise performance which may be obtained using the circuit of FIG. 1.

FIG. 17 is a schematic circuit diagram of another illustrative differential mode VCO useful in the synthesizer circuit of FIG. 1.

FIG. 18 is a schematic circuit diagram of another illustrative differential mode VCO useful in the synthesizer circuit of FIG. 1.

FIG. 19 is a schematic circuit diagram of another illustrative differential mode VCO useful in the synthesizer circuit of FIG. 1.

FIG. 20 is a schematic circuit diagram of another illustrative differential mode VCO useful in the synthesizer circuit of FIG. 1.

Skilled artisans will appreciate that components in the accompanying drawings are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the drawings may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention. DESCRIPTION OF EMBODIMENTS OF THE INVENTION

FIG. 1 is a block schematic diagram of an illustrative frequency synthesizer circuit 100 embodying the present invention. The circuit 100 includes a differential mode voltage controlled oscillator (VCO) 101 connected in a phase locked loop (PLL) 103 with known phase locked loop components 105 to provide an input control voltage V₀ to the VCO 101. The input voltage V₀ controls an operational frequency of the VCO 101 in a known manner, e.g. as described later with reference to FIGS. 4 and 5 and 17 to 20. The VCO 101 has differential output lines 107 and 109 which provide an output signal Sl comprising components separated in phase by 180 degrees. The differential output lines 107 and 109 are connected to the phase locked loop components 105, to components of a differential control loop 125 and to output lines 111 and 113.

The differential control loop 125, which includes the VCO 101 itself, is provided to reduce phase noise of the output signal Sl of the VCO 101. The differential control loop 125 is a negative feedback control loop which includes a differential mode frequency discriminator 127. Illustrative examples of the construction and operation of the frequency discriminator 127 are described in more detail later, particularly with reference to FIGS. 6 to 9. The differential mode frequency discriminator 127 of the control loop 125 produces an output error control signal S2 indicative of a detected phase noise content of the output signal Sl of the VCO 101. The error control signal S2 is a low frequency or baseband signal which is amplified by a differential mode amplifier 129 in the control loop 125 and filtered by a differential mode loop filter 131 in the control loop 125. In some embodiments of the invention to be described later, the loop filter 131 may also serve as an integrator.

Resistors 133 and 135 may be included in output lines from the differential mode frequency discriminator 127 leading to the differential mode amplifier 129.

The differential mode loop filter 131 may comprise one or more filter stages. One such stage may include a low pass filter serving as an integrator.

The differential mode amplifier 129 and the differential mode loop filter 131 are shown as separate components but, as will be apparent to those skilled in the art, could be combined in a single component, in other words an active filter. Alternatively, the differential mode loop filter 137 could be provided in the control loop 125 before the differential mode amplifier 129 rather than after the differential mode amplifier 129.

A suitable loop gain in the control loop 125 is a gain of between about 10 dB and about 30 dB, especially between about 15 dB and about 25 dB, e.g. about 20 dB, for the combination of the amplifier 129 and loop filter 131 of the control loop 125.

A suitable bandwidth of the control loop 125 for illustrative operation of the VCO 101 at a frequency greater than 5 GHz, is typically less than 1 MHz, in particular typically less than 600 kHz.

Differential output lines 137 and 139 from the differential mode loop filter 131 provide, as an output of the control loop 125, an error control signal S3 which is injected into the VCO 101. The error control signal S3 comprises positive and negative components applied respectively via the output line 137 and the output line 139. The error control signal S3 is a baseband signal which is injected into at least one voltage controlled (non-linear) device such as a varactor diode or transistor in the VCO 101. Examples of such injection are described later with reference to FIGS. 4 and 5 and FIGS. 17 to 20. This injection causes a modulation of the carrier signal of the VCO 101 by the baseband signal S3, in a manner described in more detail later, causing a corresponding reduction in phase noise of the VCO 101.

FIG. 2 which is a schematic graph of output signal power versus frequency illustrating the effect of this operation. The error control signal S3 is indicated by a dashed line 201 at frequencies less than a base RF frequency Fl, typically 600 kHz to 1 MHz. A curve indicated by a full line is shown which illustrates normal operation of the VCO 101 without the control loop 125. The curve has a resonance peak 203 which is centred on a desired VCO frequency F2, e.g. typically in the range from about 5 GHz to about 50 GHz, providing the RF carrier of the VCO 101. The width of the peak 203 is determined by (amongst other things) the phase noise of the VCO 101. An improved, narrower resonance peak indicated by a dashed line 205 is obtained when the control loop 125 is employed and the error control signal S3 is injected into the VCO 101 to reduce the phase noise. Illustrative quantified improvements in the phase noise performance obtained are described later with reference to FIG. 16.

Examples of the differential mode VCO 101, adapted to provide operation in the circuit 100 to provide injection of the error control signal S3, will be described later, particularly with reference to FIGS. 4 and 5 and FIGS. 17 to 20.

It is not a simple task for a designer to provide an analytical model of the control loop 125 of the circuit 100. The reason is that the control loop 125 is highly non-linear. The control loop 125 contains two frequency translations, one in the VCO 101 (from a baseband frequency to a high frequency carrier frequency) and one in the frequency discriminator 127 (from the carrier frequency to a baseband frequency) . Nevertheless, it is possible for a designer to establish a linearized analytical model of the control loop 125 by use of known simplified time domain equations. Traditional text book theory from control system engineering based on Laplace transforms and the commonly known formula for the closed loop transfer function of a control system can be employed to give a suitable analysis. In particular, a designer of the circuit 100 will be interested in analytically determining the following parameters in this way: a) the transfer function Hi3i(s) of the loop filter 131 suitable to ensure that the control loop 125 is unconditionally stable; b) the form of the open loop transfer function of the control loop 125; this indicates how much the phase noise is suppressed and is beneficial to know for design purposes and also particularly design of the loop filter 131; c) the form of the closed loop transfer function of the control loop 125; this indicates how the combined control of the VCO 101 by the PLL 103 and by the control loop 125 behaves as a function of input voltage to the VCO 101.

When this analytical information has been made available, the circuit 100 can be designed so that the VCO 101 may be controlled in accordance with well known control system theory, particularly in relation to the PLL 103 setting the VCO oscillation frequency by the control voltage V₀.

The open-loop transfer function of the control loop 125 can be expressed mathematically as: H₁₂₅0) = H₁₀₁0)H₁₂₇O)H₁₃₁0) (Equation 1) where H₁O₁ (s) is the Laplace domain transfer function of the VCO 101, H₁₂I (s) is the Laplace domain transfer function of the frequency discriminator 127, and Hi₃i(s) is the Laplace domain transfer function of the frequency discriminator 127. Hιoι(s) indicates changes of the output frequency of the VCO 101 as a function of the input control signal S3. E₁₂I (s) indicates voltage output of the frequency discriminator 127 as a function of input signal frequency.

Equation 1 above can be used to explain how the transfer function Hi₃i(s) of the loop filter 131 should be chosen to guarantee stability. The transfer function Hi3i(s) must be inverting to provide the subtraction required when the error control signal S3 is injected into the VCO 101. Also, in order to ensure stability of the control loop 125, the transfer function H₁₃₁(S should have a number of poles exceeding the number of zeros having a dominant low frequency pole. These conditions can be met in a number of ways. The loop filter 131 of the control loop 125 may for example be suitably provided either as an active low-pass filter or as a lead-lag filter to achieve such a loop. Suitable examples of such filters are described later with reference to FIGS. 10 and 11.

The output signal Sl produced by the VCO 101 in the synthesizer circuit 100 shown in FIG. 1 may be extracted at output terminals 115 and 117 connected to the circuit output lines 111 and 113. Alternatively, or in addition, the output signal Sl may be applied to at least one Mivide by N' frequency divider operating in a differential mode in an output circuit connected to the circuit output lines 111 and 113. For example, the output signal may be applied in parallel to a differential mode divide by Nl frequency divider 119 and a differential mode divide by N2 frequency divider 121 as shown in FIG. 1. The frequency divider 119 delivers to a band selector 123 a differential output signal having a frequency equal to the frequency of the signal Sl divided by a factor Nl. The frequency divider 121 delivers to the band selector 123 a differential output signal having a frequency equal to the frequency of the signal Sl divided by a factor N2. The band selector 123 receives a control signal from a controller 124 to select which of the output frequencies produced by the frequency dividers 119 and 121 shall be provided as a differential output signal S4 to output terminals 126 and 128.

For example, if the desired frequency of the output signal S4 following division by the frequency divider 119 or 121 is in the range 100 MHz to 1 GHz, the VCO 101 may be operable to oscillate and produce an output signal Sl having a frequency of at least 5 GHz, e.g. in the range 5 GHz to 50 GHz, e.g. about 10 GHz. The number Nl by which the frequency divider 119 divides the frequency of the signal Sl is different from the number N2 by which the output frequency divider 121 divides the frequency of the signal Sl. The numbers Nl and N2 are preferably integers. The numbers Nl and N2 depend on the value of the frequency of the signal Sl and on the value of desired output frequencies possible for the output signal S4. For example, where the frequency of Sl is 10 GHz, Nl may be 12 and N2 may be 24 giving an output signal S4 having possible frequencies respectively of 10/12 GHz and 10/24 GHz, i.e. frequencies of about 833 MHz and about 416 MHz. The band selector 123 provides the output signal S4 having the desired frequency by selecting an output signal from either the frequency divider 119 or from the frequency divider 121 as appropriate .

It will be apparent to those skilled in the art that the differential signal Sl from the differential mode VCO 101 may be delivered to more than two frequency dividers operating in a differential mode, each of which divides the frequency of Sl by a different selected factor N to give more than two possible output frequencies in the differential output signal S4.

The synthesizer circuit 100 allows an RF signal having a specific frequency required in a particular application to be synthesized with reduced phase noise. An illustrative example of the improved phase noise performance which may be obtained is described later with reference to FIG. 16. The synthesizer circuit 100 may be employed for example in an RF communications transmitter, e.g. to provide an RF carrier signal. Alternatively, the circuit 100 may be employed for example in an RF communications receiver, e.g. to provide a local oscillator of a receiver demodulator. As described in Applicant's published patent application number GB-A-2430089, it is beneficial to include in the output circuit of a frequency synthesizer circuit such as the circuit 100 a frequency divider such as the divider 119 or the divider 121 which divides down the output frequency provided by the VCO 101 in the circuit 100. This allows use of a VCO operating at a frequency much higher than the required output frequency of the synthesizer circuit. The use of the frequency divider, e.g. the divider 119 or the divider 121, advantageously helps to improve the phase noise performance of the output signal produced by the synthesizer circuit 100. This is achieved because the phase noise performance of a signal produced by a VCO can be improved by a factor of 20"logio(N) by applying the frequency division, where N is the divisor number by which the VCO output signal frequency is divided to produce the synthesizer output signal frequency.

The synthesizer circuit 100 may beneficially be produced in the form of an integrated circuit, e.g. fabricated on a semiconductor chip in a known manner. In addition, the VCO 101 may be fabricated easily in integrated circuit form by using oscillatory components such as on-chip L-R-C circuits and transistors adapted to such fabrication in a known implementation procedure.

Furthermore, the VCO 101 and other parts of the circuit 100 are suited to fabrication in integrated circuit form, especially because they operate in a differential mode. The differential mode beneficially provides increased immunity to the unavoidable noise present in power supply lines and (where present) in an antenna conducting ground plane, as well as noise in an integrated circuit chip substrate.

An integrated circuit incorporating the VCO 101 may also include many of the other components of the circuit 100 including the PLL 103 and its components 105 and the control loop 125 including the differential mode frequency discriminator 127. In some cases, it may be necessary or appropriate to supply some components as separate components, for example a reference oscillator (not shown) employed in the PLL 103.

FIG. 3 schematically depicts an integrated circuit construction of the circuit 100. The construction shown includes an integrated circuit 300, e.g. a semiconductor chip, in which components of the circuit 100 are fabricated in an illustrative area 301. Circuits having other functions (related or unrelated to the circuit 100) may also be fabricated on the integrated circuit 300. An area 303 indicates an illustrative location of such other circuits.

PLL oscillator circuits operating at frequencies of 10 GHz or more fabricated in integrated circuit form are already in wide use in the microwave and optical communications industry and the technology for producing such circuits can suitably be adapted to produce the integrated circuit 300.

FIGS. 4 and 5 are schematic circuit diagrams of illustrative VCOs useful as the differential mode VCO 101 of the circuit 100. FIGS. 4 and 5 also illustrate how the error control signal S3 produced by the differential control loop 125 may be injected into the VCO 101.

FIG. 4 shows a first VCO 400 which is an illustrative generalised VCO suitable for use as the differential mode VCO 101. Only the basic components of the VCO 400 are shown in FIG. 4. The VCO 400 may include further components not shown. The VCO 400 includes an inductor 401 and an inductor 403 which are connected together at one end and are connected to an oscillation sustaining gain block 405 at another end via connections 413 and 415 respectively. An arm 407 connected between the connections 413 and 415 includes back-to-back varactor diodes 409 and 411. The arm 407 including the varactor diodes 409 and 411 forms a parallel resonator with the inductors 401 and 403 in a loop 412 and with varactor diodes 417 and 419 connected respectively to the connectors 413 and 415. An input connection 414 from the PLL 103 (FIG. 1) delivers the control voltage V₀ produced by the PLL 103 to the varactor diodes 409 and 411. Components of the control signal S3 produced by the differential control loop 125 (FIG. 1) are applied via the lines 137 and 139 (already seen in FIG. 1) . The line 137 is connected via the varactor diode 417 to the connection 413, and the line 139 is connected via the varactor diode 419 to the connection 415. The output lines 107 and 109 (already seen in FIG. 1) via which the output signal Sl is delivered are connected respectively to the connection 413 and the connection 415.

In operation, the VCO 400 oscillates at a radio frequency, herein referred to as the Operating frequency' , which is controlled by the control voltage Vc . The control voltage adjusts a variable capacitance of the varactor diodes 409 and 411 and thereby adjusts the resonance frequency of oscillations in the resonator comprising the loop 412. The error control signal S3 is a baseband control voltage generated by the control loop 125 (FIG. 1) in one of the ways to be described in more detail later with reference to FIGS. 6 to 9. The error control signal S3 serves to cancel detected phase noise in the VCO 400. The error control signal S3 adds the phase noise detected by the frequency discriminator 127 (FIG. 1) to the phase noise present in the resonator of the VCO 101 in such a way as to provide cancellation of the phase noise present in the resonator of the VCO 101. The error control signal S3 is input to the varactor diodes 417 and 419 causing the capacitance of the varactor diodes 417 and 419 to be modulated by the error control signal S3 effectively upconverting the baseband error control signal S3 to the oscillator operating frequency to cancel the detected noise.

In an alternative embodiment (not shown) the varactor diodes 417 and 419 may be replaced by resistors. In this case, the baseband error control signal S3 causes a modulation of the baseband voltage on the varactor diodes 409 and 411 changing their capacitance. Again this causes an upconversion of the baseband error signal S3 to the operating frequency of the VCO 101. The upconverted signal components of the signal S3 are thereby added to the phase noise present in the VCO 101 to cancel the phase noise. Effectively this causes a drop in the noise power in the resonator of the VCO 101 beneficially giving a reduced sideband phase noise in the output signal Sl.

The oscillation sustaining gain block 405 includes one or more active components, e.g. one or more amplifiers, which provide gain to sustain oscillations in the VCO 400. The resulting oscillations are extracted in the form of the output RF signal Sl via the output lines 107 and 109.

The VCO 400 (and each of the other illustrative VCOs described herein for use in embodiments of the present invention) is different from VCOs of the prior art used in circuit arrangements with phase noise suppressing loops, e.g. in the circuit arrangement proposed in US-A-4, 336, 505. The basic difference is that the error control signal S3 is injected into the VCO 101 independently of the control signal V_c from the PLL 103 rather than as a single combined control signal as in the prior art. The error control signal S3 can thereby be employed directly to modulate an electrical property of a non-linear device, such as the varactor diodes 417 and 419, independently of the injection of the control voltage V₀. A benefit of the direct injection arrangement employed in embodiments of the invention such as the VCO circuit 400 is that the first at least one non-linear device, such as the varactor diodes 409 and 411, employed for frequency tuning and the second at least one non-linear device, such as the varactor diodes 417 and 419, added for injection of the error control signal S3 for phase noise suppression, can be selected independently so that an appropriate non-linear relationship between voltage and electrical property can be implemented for each of the first and second at least one non-linear devices. For example, the non-linear devices, e.g. varactor diodes 409 and 411, employed for frequency tuning can be different in size and can give a different voltage versus capacitance relationship, from those, e.g. the varactor diodes 417 and 419, employed for injection of the error control signal S3 for phase noise suppression. Selecting the pairs of non-linear devices independently in this way provides independent adjustment of loop gain in each of the PLL 103 and in the control loop 125. This introduces a degree of design freedom that relaxes stability constraints of placement of poles and zeros in the PLL 103 and the control loop 125 as compared with the prior art described in US-A- 4,336,505.

FIG. 5 shows a more detailed illustrative VCO 500 suitable for use as the differential mode VCO 101. The VCO 500 includes three transistors 517, 519 and 521 which are shown as n-mos (negative-metal oxide semiconductor) devices although they could be replaced by p-mos devices (with reversal of applied voltage polarities) or by other field effect or bipolar junction transistors. The VCO 500 includes an inductor 501 and an inductor 503 which are connected together at one end. The inductor 501 is connected at its other end via a connection 513 to the transistor 517 at its drain electrode. The inductor 503 is connected at its other end via a connection 515 to the transistor 519 at its drain electrode. The transistors 517 and 519 are connected together at their respective source electrodes to the transistor 521 at its drain electrode. The transistor 521 is connected at its source electrode to ground. A bias voltage V_bias is applied via a connection 523 to the transistor 521 at its gate electrode. The transistor 521 provides bias control of the transistors 517 and 519.

An arm 507 connected between the connections 513 and 515 includes back-to-back varactor diodes 509 and 511. The arm 507 including the varactor diodes 509 and 511 forms a resonator loop 512 with the inductors 501 and 503. An input connection 514 from the PLL 103 (FIG. 1) delivers the control voltage V₀ produced by the PLL 103 to the varactor diodes 509 and 511. A voltage V_dd is applied from a connection 525 to the respective drain electrodes of the transistors 517 and 519 to provide a source-drain current in the transistors 517 and 519. The voltage V_dd may be applied via the inductors 501 and 503 as shown in FIG. 5 or in another suitable known way (not shown) . A cross-coupling 529 between the transistor 517 at its gate electrode and the connection 515 and a cross-coupling 531 between the transistor 519 at its gate electrode and the connection 513 are shown in an illustrative manner to indicate that the transistors 517 and 519 provide the required gain to sustain oscillations in the resonator loop 512. The arrangement described so far for the VCO 500 is the same as a standard VCO known in the art as a ^λsingle switch VCO' .

In addition to the standard single switch VCO arrangement, the VCO 500 includes input connections 533 and 535 which are connected respectively to the output lines 137 and 139 (FIG. 1) which deliver the error control signal S3 from the control loop 125. The connection 533 provides an input connection via a varactor diode 525 to the transistor 517 at its drain electrode. The connection 535 provides an input connection via a varactor diode 527 to the transistor 519 at its drain electrode. The differential components of the error control signal S3 from the control loop 125 are thereby provided as input signals to the varactor diodes 525 and 527. The output lines 107 and 109 (already seen in FIG. 1) are connected to the respective drain electrodes of the transistors 517 and 527.

In operation, the VCO 500 oscillates at a resonance radio frequency (operating frequency) which is controlled by the control voltage V₀ which modulates a variable capacitance of the varactors 509 and 511. The transistors 517 and 519 provide an arrangement analogous to the gain block 405 of the VCO 400, that is they provide active components which provide gain to oscillations in the resonator loop 512 of the VCO 500. The components of the error control signal S3 modulate the capacitance of the varactor diodes 525 and 527. In a manner similar to that described earlier for the VCO 400, this modulation translates into an upconversion of the error control signal S3 to the frequency of oscillation of the VCO 500. As described earlier in relation to the VCO 400, the overall result is a decrease in the phase noise of the VCO 500 by cancellation of its phase noise as detected by the frequency discriminator 127.

The resulting oscillations at the operation frequency produced by the VCO 500 are extracted in the form of the output signal Sl (FIG. 1) via the output lines 107 and 109.

Further examples of VCOs which are adapted for use as the VCO 101 are described later with reference to FIGS. 17 to 20.

As noted earlier, the frequency discriminator 127 of the differential control loop 125 shown in FIG. 1 is provided to detect the phase noise present in the output signal Sl of the VCO 101. Illustrative circuits suitable for use as the frequency discriminator 127 will now be described with reference to FIGS. 6 to 9.

FIG. 6 shows a first illustrative frequency discriminator circuit 600 suitable for use as the differential mode frequency discriminator 127. The circuit 600 includes an electrically controllable delay unit 601 connected to a mixer 603. The output lines 107 and 109 delivering components of the output signal Sl from the VCO 101 are split to provide differential input lines 605 and 607 to the delay unit 601 and also differential input lines 609 and 611 to the mixer 603.

The delay unit 601 delays the components of the signal Sl applied to it via the lines 605 and 607 by a time delay τ chosen to make the inputs to the mixer 603 applied via the lines 609 and 611, relative to the inputs applied via the lines 605 and 607, uncorrelated in the time domain, preferably by applying a time delay τ which establishes a 90 degrees phase difference between the respective delayed and undelayed inputs. The mechanism of this procedure is illustrated in FIG. 7 and described as follows. As shown in FIG. 7, the signal Sl versus time is represented by a portion 701 which is delivered via the line 609 and a portion 703 delivered via the corresponding line 605 to the delay unit 601 which delays the portion 703 by a time delay by τ to produce a portion 705 in the line 613 at the output of the delay unit 601. Each of the portions 701, 703 and 705 comprises a sinusoidal carrier with superimposed noise. The portion 703 includes an illustrative noise spike 707 at some time t = tl-τ. An identical noise spike 709 is obtained in the portion 701 at the time t = tl-τ. A mixing operation on the portions 703 and 701 will produce no useful output: only a dc component will result as the noise spikes 707 and 709 are correlated for the two portions. However, an output signal which is a function of (phase noise) frequency is desired. This is obtained by introducing the time delay τ. A noise spike 713 which is obtained at a time t = tl on the portion 701 is sufficiently different from a noise spike 711 obtained on the delayed portion 705 that the two noise spikes do not correlate. The mixing operation provided by the mixer 603 on the portions 701 and 705, having the relative time delay τ gives an output from the mixer 603 which is a function of phase noise frequency as desired. This result may be demonstrated mathematically as follows.

The signal present on the line 609 as a function of time t may be expressed as S₆o₉(t) and written as:

S₆o9(t) = cos (ω_ot + Φ₆o9(t) ) (Equation 2) and the signal present on line 613 may be expressed as S₆i₃ (t) and written as:

S₆I₃ (t) = sin(ω_o(t - τ) + Φ₆₁₃(t) ) (Equation 3) assuming the signals Sδ09(t) and Sδi3 (t) are kept in quadrature, ωo is the angular frequency of the VCO 101, τ is the time delay introduced by the delay unit 601, and Φ₆₀₉(t) and Φ₆₁₃(t) represent the time domain phase noise of signals Sδ09(t) and Sδi3 (t) respectively. Multiplying the signals Sδ09(t) and Sδi3 (t) together, it is seen that the result, which is a voltage V_Ouτ(t) appearing at the output of the mixer 603 as a function of time, is given by:

V_0UT (t) = K-sin(ω_oτ + Φ₆i₃(t) - Φ₆o9(t) ) (Equation 4) assuming that the second harmonic product of the mixer 603 can be ignored because it can be removed by filtering. A similar result is obtained for the signal Sen (t) applied on the line 611 when mixed with the signal Sβis (t) applied on the line 615. Equation 4 effectively states that the output of the frequency discriminator circuit 600 for a noisy input sine wave is a dc term ωoτ that is function of the time delay τ applied by the delay unit 601 and a time varying measure of the phase noise difference Φ₆₁₃(t) - Φ609(t) . Furthermore, Equation 4 indicates how to choose the time delay τ . The delay τ should be chosen to meet two conditions Cl and C2 as follows.

Condition Cl

Firstly, the delay τ should be large enough to make Φ₆₁₃(t) and Φ609(t) uncorrelated in the time domain, e.g. to make the difference Φ₆₁₃(t) - Φ609(t) different from zero as stated previously. Numerical computer simulations indicate that this condition is met for the circuit 100 if the delay τ is chosen in such a way that

2π τ > 10- (Equation 5) ω₀

For example, if the VCO 101 is oscillating at a frequency of about 10 GHz, the delay τ should be chosen to be at least about 1 nanosecond. Such a delay can be realized in whole or in part by use of transistor delay elements provided on an integrated circuit chip. An example of the delay unit 601 is described later with reference to FIG. 15. Condition C2

Secondly, the delay τ must be chosen to make the detector provided by the frequency discriminator circuit 600 operate on a zero cross-over of the sine function of Equation 4. This ensures maximum gain of the circuit 600 when the time derivative of the sine function is at a maximum at a zero cross-over. Furthermore, it ensures monotonicity of the transfer function of the phase noise detector provided by the circuit 600.

The two conditions Cl and C2 specified above may be met simultaneously for the detector provided by the frequency discriminator circuit 600 by adjusting the delay unit 601 by control signals. A first control signal S5 is applied from a controller 639 via a connection 637, and a second signal S6 is applied by a control loop 631 via a connector 633. The signal S6 is a fine adjustment signal that keeps the signals S₆o₉(t) and S₆i3 (t) (and the signals S₆n (t) and S₆is (t) ) in quadrature and may be produced in a manner as described further below .

The signal S5 is a digital control signal that may be a function of the oscillation frequency of the VCO 101. The signal S5 may be employed to switch digitally controlled transistor delay elements (not shown) within the delay unit 601. The signal S5 is set in this way to give : ωoτ = N π (Equation 6) where N is a positive integer, N = I, 2, 3,... As the controller 639 setting the signal S5 may have knowledge of the desired oscillation angular frequency ωo of the VCO 101, it is straightforward to meet the condition of Equation 6. This may be carried out in the controller 639, for example, by direct computation of τ from Equation 6, or by use of a look-up table stored by a memory (not shown) of the controller 639. In the case of the look-up table, the value of N applied by the controller 639 is selected to give the required value of τ based on Equation 5.

The mixer 603 produces the differential output signal S2 shown in FIG. 1. As previously noted, the signal S2 is amplified by the differential mode loop amplifier 129 shown in FIG. 1 and is filtered and integrated by the differential mode loop filter 131. The filter 131 removes unwanted high frequency components in the output lines 631 and 633 from the mixer 603 including unmixed fractions of the signal Sl and its delayed counterpart and higher order products of these input signals.

A pair of connections 617 and 619 in the circuit 600 sample the components of the undelayed signal Sl in the lines 609 and 611. A pair of connections 621 and 623 sample the components of the delayed signal produced in the lines 613 and 615 by the delay unit 601. The pair of connections 617 and 619 and the pair of connections 621 and 623 provide respective differential inputs to a phase detector 625 in the further control loop 631. The phase detector 625 may take a number of forms which may be known per se. The phase detector 625 detects a difference in phase between the undelayed signal Sl delivered via the connections 617 and 619 and the corresponding delayed signal delivered via the connections 621 and 623. The phase detector 625 produces an output signal which is an indication of the measured difference in phase between the undelayed signal Sl and its delayed counterpart. Ideally, there should be a phase difference of 90 degrees between the phase of the undelayed signal Sl and the phase of its delayed counterpart, as described above. The output signal produced by the phase detector 625 is applied in turn to a loop filter 627 and to an amplifier 629. The loop filter 627 may comprise one or more filter stages including a low pass filter serving as an integrator. The amplifier 629 provides a sustaining gain in the loop 631. The loop filter 627 and the amplifier 629 are shown as separate components but, as will be apparent to those skilled in the art, could be combined in a single component. Alternatively, instead of the amplifier 629 following the loop filter 627, the loop filter 627 could follow the amplifier 629. The output connection 633 from the amplifier 629 provides the input connection to the delay unit 601 to deliver to the delay unit 601 the control signal S6 referred to earlier.

The control loop 631 is an optional but preferable part of the circuit 600 which may be included to provide a delay locked loop. The control signal S6 delivered to the delay unit 601 ensures that the time delay τ applied by the delay unit 601 is exactly equivalent to a phase difference of 90 degrees. The phase detector 625 may be a quadrature phase detector, e.g. as provided by an exclusive OR gate. Such a detector produces an output proportional to the difference from 90 degrees of the phase difference between the input signals to the detector. Controlling the time delay τ applied by the delay unit 601 to be exactly equivalent to a phase difference of 90 degrees by use of the control signal S6 from the loop 631 ensures that the respective inputs to the mixer 603 have a phase difference of exactly 90 degrees. This condition guarantees that the Condition C2 specified earlier is met. The resultant operation simplifies loop stability and allows the loop gain of the control loop 125 (FIG. 1) to be maximised in order to give maximum and effective phase noise suppression.

Shown in FIG. 8 is a second illustrative frequency discriminator circuit 800 suitable for use as the differential mode frequency discriminator 127 (FIG. 1). The circuit 800 includes an electrically controllable delay unit 801 and a summer 803. The output lines 107 and 109 delivering components of the output signal Sl from the VCO 101 (FIG. 1) are split to provide differential input lines 805 and 807 to the summer 803 and also differential input lines 809 and 811 to the delay unit 801. The delay unit 801 delays the signal Sl applied to it via the lines 809 and 811 by an amount equivalent to a phase shift of an integral multiple of 180 degrees and produces components of an output delayed counterpart of the signal Sl in output lines 813 and 815 leading from the delay unit 801 to the summer 803. The summer 803 adds the undelayed signal Sl delivered via the lines 805 and 807 to the delayed counterpart of the same signal delivered via the lines 813 and 815. Output lines 817 and 819 from the summer 803 provide a differential input to an envelope detector 852. Output lines 851 and 853 from the envelope detector 852 provide a differential input to a DC remover 854. Output lines 855 and 857 from the DC remover 854 provide the output signal S2 which is delivered around the control loop 125 as described earlier with reference to FIG. 1.

The delay unit 801 applies a time delay which ensures that the control loop 125 is stable. The time delay is set by a signal S7 applied from a controller 845 via a connection 843. The controller 845 may operate in a manner similar to that of the controller 635. It may also be used also to provide a frequency setting for the PLL 103 (FIG. 1) .

In operation, the delay unit 801, the summer 803, the envelope detector 852 and the DC remover 854 together provide a phase shift demodulator (also known in the art as a Foster-Seeley discriminator) which provides a detector of the phase noise of the VCO 101. The detector operates in the following way.

The delay unit 801 delays the input differential signal Sl applied via the lines 809 and 811 by a time delay τ (this is in general different from the time delay τ applied by the delay unit 601) . The summer 803 subtracts from the resulting delayed signal delivered from the delay unit 801 via the lines 813 and 815 the differential undelayed counterpart signal applied via the lines 805 and 807. Effectively this operation produces an output signal by the summer 803 that contains the time derivative of the phase noise of the input signal Sl. This output signal can be further processed to obtain the output signal S2 shown in FIG. 1. This operation can be shown by mathematical analysis as follows.

Firstly, it is noted that the mathematical definition of the derivative with respect to time t of a generalised signal S (t) is defined as: dS ,. S(t)-S(t-τ)

— = lim—— (Equation 7) dt r→o _τ

When τ is small, Equation 7 leads to the approximation:

S(t)-S(t-τ) = τ^^- (Equation 8) dt

The delay unit 801 and the summer 803 together perform the subtraction indicated by the left hand side of Equation 8. The output signal Sl from the VCO 101 may in this case be represented by the signal S₈₀₉(t) present on the line 809 and can be expressed as a sine wave of the form:

S₈₀9(t) = A sin(ω_ot + Φ₈o9(t) ) (Equation 9) Again, cϋo is the angular frequency of the VCO 101 and <I>809(t) is the time domain phase noise of the VCO 101. A is an arbitrary constant that represents the signal amplitude . By combining Equations 8 and 9, Equation 10 as follows can be derived:

τ ^{dS%w (t)} = TA cos(ω₀t + Φ₈₀₉ (t))(ω₀ + ^^{809 (t)}) (Equation 10 ) dt dt

The left hand side of Equation 10 is equivalent to the output of the summer 803. The right hand side of Equation 10 describes a signal that is a high frequency carrier having an angular frequency Cϋo modulated by a baseband signal consisting of the time derivative of the phase noise of the VCO 101 and a dc component. The high frequency carrier is removed by the envelope detector 852. Examples of suitable envelope detectors for use as the envelope detector 852 are described later with reference to FIGS. 12 and 13. The envelope detector 852 produces an output signal S₂{t) which can be described in the following form:

S₂(t) = τA(ω₀+ mxλ) (Equation 11) dt where A is again an arbitrary amplitude constant and τ is again the time delay applied by the delay unit 801. It is now apparent that if the output signal S₂(t) is integrated with respect to time and the dc term τAωo is removed, the required output signal S2, which contains the phase noise of the VCO 101 as a function of time, is obtained as described by Equation 12 as follows:

S2 = ^S₂(t)dt = τAΦ_&ω(t) (Equation 12)

In the circuit 800, the DC remover 854 carries out the required removal of the dc term τAωo appearing in Equation 11. Furthermore, the integration required by Equation 12 is appropriately applied in the control loop 125 by the differential mode loop filter 131 after amplification by the differential mode amplifier 129

(FIG. 1) . The loop filter 131 also removes remaining high frequency components in the output lines 855 and 857 from the DC remover 854 including uncancelled components of the signal Sl and its delayed counterpart.

A pair of connections 821 and 823 in the circuit 800 sample the components of the undelayed signal Sl in the lines 805 and 807. A pair of connections 825 and 827 sample the components of the counterpart delayed signal in the lines 813 and 815. The pair of connections 821 and 823 provide differential inputs to an inverter 829 which inverts the respective components of the signal Sl in the connections 821 and 823 and delivers an inverted differential output signal via connections 830 and 831 to a phase detector 833 in a further control loop 835. The pair of connections 825 and 827 provide components of the delayed counterpart signal produced by the delay unit 801 as inputs to the phase detector 833.

The phase detector 833 detects differences in phase between the respective differential signals applied to it via: (i) the pair of connections 830 and 831; and

(ii) the pair of connections 825 and 827. Ideally, the phase difference should be zero degrees, since the delay unit 801 and the inverter 829 should each ideally change the phase of the signal Sl from the VCO 101 by 180 degrees. The phase detector 833 may take a number of forms which may be known per se. In a simple known form the phase detector 833 may for example be as described later with reference to FIG. 14.

The phase detector 833 produces an output signal which is an indication of the measured difference in phase between the undelayed signal Sl and its delayed counterpart. The output signal produced by the phase detector 833 is applied in the further loop 835 in turn to a loop filter 837 and to an amplifier 839. The loop filter 837 may comprise one or more filter stages including a low pass filter serving as an integrator. The amplifier 839 provides a sustaining gain in the loop 835. The loop filter 837 and the amplifier 839 are shown as separate components but, as will be apparent to those skilled in the art, could be combined in a single component. Alternatively, the amplifier 839 could be before the filter 837 in the loop 835. An output connection 841 from the amplifier 839 provides another input connection to the delay unit 801 and delivers a control signal S8 to the delay unit 801.

The control loop 835 is an optional but preferable part of the circuit 800 which may be included to provide a delay locked loop. The control loop 835 provides by the control signal S8 delivered to the delay unit 801 fine adjustment of the time delay τ applied by the delay unit 801. This may ensure that the time delay τ applied by the delay unit 801 is exactly equivalent to a phase difference of 180 degrees. This simplifies loop stability of the control loop 125 (FIG. 1) and allows loop gain of the control loop 125 to be maximised in order to give maximum and effective phase noise suppression .

FIG. 9 shows an alternative illustrative differential discriminator circuit 900 which may used in place of the circuits 600 and 800 shown in FIGS. 6 and 8 respectively to provide the differential mode frequency discriminator 127 shown in FIG. 1. The discriminator circuit 900 includes an analog differential differentiator 901.

In the differentiator 901, an input line 903 connected to the output line 107 from the VCO 101 (FIG.l) is connected to an input of a differential amplifier 907 of the differentiator 901 via a capacitor 909 of the differentiator 901. An input line 905 connected to the output line 109 from the VCO 101 (FIG. 1) is connected to another input of the differential amplifier 907 via a capacitor 911 of the differentiator 901. A resistor 913 of the differentiator 901 is connected in parallel with the differential amplifier 907 between (i) the input line 903, at a junction between the capacitor 909 and the differential amplifier 907, and (ii) an output line 917 from the differential amplifier 907. Similarly, a resistor 915 of the differentiator 901 is connected in parallel with the differential amplifier 907 between (i) the input line 905, at a junction between the capacitor 911 and the differential amplifier 907, and (ii) an output line 919. The output lines 917 and 919 are connected as inputs to an envelope detector 921. Output lines 923 and 925 from the envelope detector 921 are connected as inputs to a DC remover 927. Output lines 929 and 931 from the DC remover 931 produce the output signal S2 for delivery around the control loop 125 as described earlier with reference to FIG. 1.

The differentiator 901 works in a manner similar to the detector provided in combination by the delay unit 801 and the summer 803 in the circuit 800, but it does not require a delay element. The differentiator 901 operates directly in the time domain to provide a differentiation operation on the differential output signal Sl produced by the VCO 101 as its input signal. The differentiator 901 produces a corresponding output signal V_dt(t) which can be written as: dΦ(t)

V_dt (t) = Acos(ω₀t + Φ(t))(ω₀ + — ) (Equation 13 ) dt in which the other various symbols have the meanings given earlier. The time constant RC of the differentiator 901 provided by the resistors 913 and 915 and the capacitors 909 and 911 should be chosen in such a way that :

1/ RC« ω₀

The differentiator 901 thus transforms the phase noise Φ(t) in the output signal Sl from the phase modulation (PM) domain into the amplitude modulation (AM) domain. In Equation 13, this is seen by noting the multiplying parentheses containing the differentiated phase noise. The envelope detector 921 removes the high frequency content of the signal produced by the differentiator 901, leaving only the envelope term containing the differentiated phase noise.

The DC remover 927 operates on the differential output signal produced by the envelope detector 921 in a manner similar to the DC remover 854 shown in FIG. 8. The differential output signal S2 is produced by the DC remover 927 in the output lines 929 and 931 and is delivered around the control loop 125 for further processing by the differential mode amplifier 121 and the differential mode loop filter 131 (FIG. 1) .

FIG. 10 is a schematic circuit diagram of an illustrative active filter 1000 which is an example of a filter suitable for use as the loop filter 131 in the circuit 100 of FIG. 1. In the filter 1000, an input line 1001, e.g. connected to an output line of the differential mode amplifier 129 (FIG.l) is connected to an input of a differential amplifier 1005 via a resistor 1003. An input line 1007, e.g. connected to the other output line of the amplifier 129, is connected to another input of the differential amplifier 1005 via a resistor 1009. A parallel combination of a capacitor 1011 and a resistor 1013 is connected in parallel with the differential amplifier 1005 between (i) the input line 1001, at a junction between the resistor 1003 and the differential amplifier 1005, and (ii) an output line 1019 from the differential amplifier 1005. Similarly, a parallel combination of a capacitor 1017 and a resistor 1015 is connected in parallel with the differential amplifier 1005 between (i) the input line 1007, at a junction between the resistor 1009 and the differential amplifier 1005, and (ii) an output line 1021 from the differential amplifier 1005.

The active filter 1000 receives the input signal S2 (optionally already amplified by the amplifier 129) and applies an appropriate filtering, integration and amplification to the signal to produce the error control signal S3.

FIG. 11 is a schematic circuit diagram of an illustrative active filter 1100 which is another example of a filter suitable for use as the loop filter 131 in the circuit 100 of FIG. 1. In the filter 1100, an input line 1101, e.g. connected to an output line of the differential mode amplifier 129 (FIG.l), is connected to an input of a differential amplifier 1105 via a resistor 1103. An input line 1107, e.g. connected to the other output line of the amplifier 129, is connected to another input of the differential amplifier 1105 via a resistor 1109. A series combination of a resistor 1111 and a capacitor 1113 is connected in parallel with the differential amplifier 1105 between (i) the input line 1101, at a junction between the resistor 1103 and the differential amplifier 1105, and (ii) an output line 1119 from the differential amplifier 1105. Similarly, a series combination of a resistor 1115 and a capacitor 1117 is connected in parallel with the differential amplifier 1105 between (i) the input line 1107, at a junction between the resistor 1109 and the differential amplifier 1105, and (ii) an output line 1121 from the differential amplifier 1105.

The active filter 1100 receives the input signal S2 (optionally already amplified by the amplifier 129) and applies an appropriate filtering, integration and amplification to the signal to produce the error control signal S3.

FIG. 12 is a schematic circuit diagram of an illustrative differential mode envelope detector 1200 useful as the envelope detector 852 (FIG. 8) or as the envelope detector 921 (FIG. 9) . A first component S_ΣN of an input signal to be processed by the detector 1200 is applied via a connection 1202 to the base of an npn junction transistor 1201, and a second component S'_ΣN is applied via a connection 1217 to the base of an npn junction transistor 1203. The components S_ΣN and S'_ΣNare complementary. The collector of the transistor 1201 is connected through a resistor 1205 to a voltage source 1231 which supplies a voltage V_DD. The collector of the transistor 1203 is connected through a resistor 1207 to the voltage source 1231 to receive the voltage V_DD.

The emitter of the transistor 1201 is connected to a current source 1208 and via a connection 1204 to a rectifying diode 1209. The rectifying diode 1209 is connected to a parallel combination of a capacitor 1211, a resistor 1213 and a current source 1215. The current sources 1208 and 1215 and the capacitor 1211 and the resistor 1213 are connected to ground at their ends remote from the transistor 1201.

The emitter of the transistor 1203 is connected to a current source 1221 and via a connection 1219 to a rectifying diode 1223. The rectifying diode 1223 is connected to a parallel combination of a capacitor 1225, a resistor 1227 and a current source 1229. The current sources 1221 and 1229 and the capacitor 1225 and the resistor 1227 are connected to ground at their ends remote from the transistor 1203.

The transistors 1201 and 1203 operate as voltage followers. In this mode of operation a voltage on each of the output connections 1204 and 1219 replicates the voltage on each of the input connections 1202 and 1217. The capacitors 1211 and 1225 integrate the charge that is applied to them respectively by the diodes 1209 and 1223 into output voltages S_out and S Out developed on output connections 1206 and 1220 respectively. The current sources 1215 and 1229 maintain a proper operating point for the voltages on the capacitors 1211 and 1225.

When a signal of constant amplitude and frequency is applied at the input connection 1202 some steady state voltage (selected by design) is defined at the output connection 1206. This happens because the current source 1215 discharges into the resistor 1213 exactly as much current as the diode 1209 sources. If the input signal amplitude of the signal S_ΣN applied via the input connection 1202 increases, the voltage at the output connection 1206 which is the signal S_out will increase as more current is sourced by the diode 1209. The diode 1209 will source less current if the amplitude of the signal S_ΣN applied on the input connection 1202 drops. The rate by which the voltage of the signal S_out can change on the output connection 1206 is determined by various parameters, including the time constant defined by the capacitance of the capacitor 1211 and the resistance of the resistor 1213, the properties of the diode 1209 and the magnitude of current flow in the current source 1215. If these parameters are adjusted appropriately the output voltage S_out can be made to track the envelope of the input signal S_ΣN. A similar effect can be obtained at the output connection 1220 wherein the output signal S O_ut can be made to track the envelope of the input signal S'_ΣN.

FIG. 13 shows another illustrative envelope detector 1300 which is an example of an envelope detector useful in the circuit 800 or in the discriminator 900 described earlier. For simplicity, the detector 1300 is shown in FIG. 13 with single connections between components but may in practice be constructed and operate in differential mode with duplex connections between components.

An input signal is delivered via an input line 1301. The input line 1301 provides a first input to a mixer 1303. The input line 1301 is split before the mixer 1303 to provide an input line 1305 to a limiting amplifier 1307. An output line 1309 from the limiting amplifier 1307 provides another input to the mixer 1303. An output line 1311 from the mixer 1303 provides an input to a low pass filter 1313. An output line 1315 from the low pass filter 1313 provides an output signal indicating a desired envelope of the input signal applied at the input line 1301.

The envelope detector 1300 operates in the following way to find the envelope A(t) of a given input signal. The limiting amplifier 1307 saturates the input signal desired to be extracted as a constant. The mixer 1303 multiplies the two signals applied to via the lines 1301 and 1309 to produce a signal which represents a dc term proportional to the desired signal A(t) plus the second harmonic of the input signal. The low pass filter 1313 removes the second harmonic by filtering. In practice, the second harmonic is easily removed by the filter 1313 since the desired signal A(t) is a baseband signal which on a frequency scale is typically 10 GHz to 50 GHz away from the second harmonic.

FIG. 14 is a schematic circuit diagram of an illustrative phase frequency detector 1400 suitable for use as one example of the phase detector 833 in the control loop 835 of the circuit 800 shown in FIG. 8. The phase frequency detector 1400 includes a first D-flip flop (data flip flop) 1401 to which an input line 1403 is connected to deliver a reference signal R. An output line 1405 extends from the flip flop 1401. A second D- flip flop 1407 has an input line 1409 to deliver an input signal V to be phase locked. An output line 1411 extends from the flip flop 1401. In accordance with standard naming of terminals of D-flip flops, ^λD' , ^λCLK' , ^λCLEAR' and ^λQ' indicate respectively data input, clock, clear and data output terminals of each of the flip-flops 1401 and 1407. Samples of signals in the output line 1405 and the output line 1411 are provided to an AND gate 1413 via lines 1415 and 1417 respectively. The AND gate 1413 provides a re-set control signal to the flip flop 1401 via a line 1419 and to the flip flop 1407 via a line 1418 respectively.

The reference signal R and the signal V to be phase locked are aligned in phase automatically by the loop action of the control loop 835 (FIG. 8) which in this embodiment acts as a phase locked loop. Assume that before locking of the loop 835 the rising edge of the signal R indicated by a square wave 1421 arrives at the flip flop 1401 before the rising edge of the signal V indicated by a square wave 1423, which has the same form and frequency as the wave 1421, arrives at the flip flop 1407. An output ^λUP' signal is applied to the output line 1405 to indicate this state. This signal continues until the AND gate 1413 applies a control signal to reset the flip flops 1401 and 1407. This happens when there is a positive rising edge on the ^λV input on input connection 1409. Similarly, if before locking of the loop 835, the rising edge of the signal V arrives at the flip flop 1407 before the rising edge of the signal R arrives at the flip flop 1401, an output ^λDOWN' signal is applied to the output line 1411 to indicate this state. This signal continues until the AND gate 1413 applies a control signal to re-set the flip flops 1401 and 1407. This happens when there is a rising edge on the ^λR' input on input connection 1403. Hence, if the loop 835 is not in the locked state, pulse trains will be generated on the output lines 1405 and 1411 depending on which of the signals R and V is leading the other. The ^λUP' and ^λDOWN' signals on the output lines 1405 and 1411 can be used in a well known manner to control a known charge pump (not shown) which sources or sinks electrical charge to or from a capacitor. Effectively, a control voltage is thereby developed which is driven up or down to correct for the leading or lagging. In the circuit 800, the control voltage is employed to provide the signal S8 which is employed to give fine adjustment of the time delay applied by the delay unit 801 as described earlier.

The PLL 103 including the phase locked loop components 105 shown in FIG. 1 controls the operating frequency of the VCO 101 by delivery of the control voltage V_0. The PLL 103 may take a number of forms which are well known per se. Examples are described for example in Applicant's published UK patent application number GB-A-2430089. The control loop 125 is operated whilst the PLL 103 is operated. This means that the VCO 101 is controlled by two control loops at the same time potentially causing a risk of a competition between the individual mechanisms of the two loops. However, a dual loop controller as commonly used in control systems engineering and known methods and tools available to deal with such dual loop systems is preferably employed. Thus, the controller employed in the control loop 125, e.g. the controller 639 in the circuit 600, or the controller 845 in the circuit 800, may therefore suitably be the same controller employed to set the frequency in the PLL 103. In any case, the design of such a dual loop system is simplified if only one of the control loops includes an integrator. Hence it is convenient for an integrator, e.g. as provided by the loop filter 131, to be present in the control loop 125 but not in the PLL 103. Nevertheless, integrators could be present in both loops if the likely increase in design complexity is accepted.

An example of a procedure that may be employed for analytical design of the circuit 100 is as follows. With the control loop 125 running in conjunction with the PLL 103, the expression for VCO phase in a standard expression normally employed to determine the VCO transfer function may be substituted by an expression including the closed loop transfer function of the control loop 125. The frequency setting of the PLL 103 may then be designed in a standard way.

Each of the delay unit 601 and the delay unit 801 included respectively in the circuit 600 of FIG. 6 and the circuit 800 of FIG. 8 may be implemented in the form of a known transistor delay cell. When the circuit 100 is in the form of an integrated circuit, e.g. the integrated circuit 300 shown in FIG. 3, the delay unit 601 or 801 in the form of a transistor delay cell may be incorporated within the integrated circuit. Alternatively, or in addition, the time delay applied by the delay unit 601 or the delay unit 801 may be provided partly by a separate delay element. FIG. 15 schematically depicts a construction 1500 formed in this way. The construction 1500 includes an integrated circuit chip 1501 formed on a substrate 1506, e.g. a printed circuit board. The chip 1501 incorporates components of the circuit 100 in an area 1502. An operating circuit 1503 in the area 1502 comprises the differential mode frequency discriminator 127 in the form of the circuit 600 without the delay unit 601. The delay unit 601 comprises a transistor delay 1504 formed on the integrated circuit chip 1501 and a delay element 1505 formed separately from the chip 1501 on the substrate 1506. In FIG. 15, the delay element 1505 is shown formed as an elongate metallised strip deposited in a known manner on the substrate 1506. The metallised strip acts as a transmission line delay. The delay element 1505 is connected in series with the transistor delay 1504 which together provide the required time delay τ.

The advantage of obtaining the time delay τ by a delay unit which is partly in the form of a passive transmission line, e.g. in the form of the delay element 1505, is that the transmission line noise figure obtained is equal to its insertion loss which might be lower than the noise figure achievable by obtaining the required delay τ using transistors only. Furthermore, a passive transmission line has zero power dissipation which might be an advantage in certain low power systems such as mobile or portable radios or telephones or other portable radio equipment used in high frequency wireless communications .

The delay element 1505 is connected to appropriate components of the operating circuit 1503 by an output pad driver (amplifier) 1507 to deliver a signal to be delayed to one end of the delay element 1505. The delay element 1505 is also connected at its other end to the transistor delay 1504 which in turn is connected to the appropriate components of the operating circuit 1503 via an input amplifier 1508. The driver pad 1507 and the amplifier 1508 apply a sustaining gain to the input and output signal of the delay element 1505.

A signal from the operating circuit 1503 to be delayed is amplified by the driver pad 1507 and applied as an input signal to the delay element 1505. The signal is delayed by the delay element 1505 and delivered as an output signal by the delay element 1505. The output signal of the delay element 1505 is amplified by the amplifier 1508 and returned to the operating circuit 1503 via the transistor delay 1504 in which a further delay is applied. The control signals S5 and S6 (referred to earlier in relation to the circuit 500 shown in FIG. 5) are applied to the transistor delay 1504.

As noted earlier, VCOs formed on an integrated circuit show a typical phase noise performance of about -100 dBc at a 100 kHz offset for output frequencies in the vicinity of 2 GHz, with further reduced performance at higher frequencies. For many applications such as narrow band radio communications (e.g. such as in TETRA systems) this performance is inadequate. However, beneficially, the use of the control loop 125 providing the error control signal S3 for separate injection into the VCO 101 in the circuit 100 in accordance with embodiments of the invention provides a significant improvement in this performance. In order to demonstrate the improvement, a comparative analysis example has been carried out. The following non-limiting conditions were chosen for employment in the comparative analysis. The operating (oscillation) frequency of the VCO 101 and the frequency of the output signal Sl produced by the VCO 101 was approximately 10 GHz. The output signal S4 had a frequency between 150 MHz and 1 GHz. The PLL 103 typically had a loop bandwidth of not more than 10 kHz. The differential mode frequency discriminator 127 employed in the control loop 125 was of the form of the circuit 600 described with reference to FIG. 6. The delay time τ applied by the delay unit 601 was between 0.5 nanosecond and 10 nanoseconds, typically about 1 nanosecond. The control loop 125 had a bandwidth of about 500 kHz. This bandwidth was determined by finding a good compromise between a suitably high bandwidth and a bandwidth limited so as not to give a VCO phase noise which exceeded its own open loop noise performance curve. In the comparative analysis example, the phase noise performance of the circuit 100 was estimated by harmonic balance simulation using a simulator supplied by Agilent Corporation under the trade name Advanced Design System Version 2005A. The simulator was employed to estimate: (i) the phase noise of the output signal Sl of the VCO 101 without employing the differential control loop 125 in the circuit 100; (ii) the phase noise of the output signal Sl of the VCO 101 with the differential control loop 125 employed; and (iii) the phase noise of the output signal S4 obtained after dividing down the output signal Sl with the differential control loop 125 employed. The circuit 100 and the VCO 101 used in it were simulated in integrated circuit form using a high level model.

The results obtained in the comparative analysis are shown in FIG. 16 which is a graph of phase noise in dBc/Hz plotted versus offset frequency in Hz for the three cases (i) , (ii) and (iii) described above. The horizontal scale of the graph of FIG. 16 is logarithmic over the range 10 Hz to 10 MHz. The phase noise performance obtained in case (i) is indicated by a curve 1601. The phase noise performance is significantly improved in case (ii) (compared with case (i) ) as indicated by a lower curve 1603. Experimental points ml and m2 on the curve 1603 illustrate the improved results obtained in case (ii) . For point ml at an offset frequency of 100 kHz, the phase noise is lowered to about -116 dB/Hz from about -99 dB/Hz. For point m2 at an offset frequency of 21.5kHz, the phase noise is lowered to about -113 dB/Hz from about -80 dB/Hz. As expected, the phase noise performance is further reduced by dividing the output frequency. When the output frequency is divided by a factor of 11 in case (iii) to give an output frequency of about 900 MHz, a lower curve 1605 is obtained. In this case, the phase noise for the offset frequencies of 100 KHz and 21.5kHz (as for points ml and m2) is further reduced respectively to about -133 dB/Hz and about -136 dB/Hz respectively at points indicated as m3 and m4.

The results obtained in cases (ii) and (iii) above as shown in FIG. 16 illustrate that a significant improvement in phase noise performance may beneficially be obtained by using the differential control loop 125 including the differential mode frequency discriminator 127 in conjunction with the differential mode VCO 101 in the circuit 100. Further (smaller) improvements in phase noise performance may be obtained by additional use of other control loops in conjunction with the control loop 125 to reduce phase noise of the VCO 101. For example, the circuitry described in Applicant's UK published patent application GB-A-2430089 may additionally be employed. In this circuitry, the phase of a feedback signal from the VCO delivered to the phase locked loop employed to control the VCO frequency is adjusted to correct for detected spurious phase errors. Further (smaller) improvements in phase noise performance may also be obtained by making enhancements to the VCO 101, such as in the following embodiments. FIGS. 17 to 20 show schematic circuit diagrams of further examples of VCOs which may be employed as the VCO 101 in the circuit 100 of FIG. 1. These further examples are specially adapted, from standard VCOs known in the art, to suit operation in the circuit 100.

A first further example of an adapted VCO is a VCO 1700 shown in FIG. 17. This is another adaptation of the VCO single switch VCO referred to earlier. In this case, the delivery of the error control signal S3 via the varactor diodes 525 and 527 as shown in FIG. 5 is not used. Instead, a further arm 508 is connected between the connections 513 and 515. The further arm 508 includes back-to-back varactor diodes 1701 and 1703. An input connection 1705 is connected to the junction between the varactor diodes 1701 and 1703.

In the VCO 1700, a single connection injection of the error control signal S3 into the core of the VCO 101 is made via the input connection 1705. The VCO 1700 can be considered as a reduced case of the VCO 500 (FIG. 5), but it is simpler to implement than the VCO 500. The operational frequency of the VCO 1700 is set as for the VCO 500 by the control voltage V₀. The VCO 1700 (like the VCO 500) contains a cross-coupled gain stage provided by the connections 529 and 531. This will cause low frequency noise on the drain electrode of the transistor 517 to track the low frequency noise on the the drain electrode of the transistor 519. In other words, the low frequency noise on the drain electrodes of the transistors 517 and 519 at which the output connections 107 and 109 are also connected is highly correlated. In this case, the error control signal S3 can be delivered via a single input connection, namely the connection 1705. The signal S3 modulates the capacitance of the varactor diodes 1701 and 1703 and thereby reduces the phase noise of the VCO 1700 in a manner similar to that described earlier for the VCOs 400 and 500. The single connection 1705 may be obtained from the dual connections 137 and 139 in one of the following ways: a) a combined signal S3 from the components delivered via the lines 137 and 139 may be obtained by directly joining or adding the component voltages on the lines 137 and 139; or b) one of the lines 137 and 139 may be left open (unconnected) or may be terminated by connection to an appropriate node such as ground by a resistor; the other of the lines 137 and 139 may be the only one of them used to inject the signal S3.

A second further example of an adapted VCO is a VCO 1800 shown in FIG. 18. This is another adaptation of the single switch VCO referred to earlier. In this case, the delivery of the error control signal S3 via the varactor diodes 525 and 527 as shown in FIG. 5 is again not used. Instead, an input connection 1801 through a resistor 1803 is connected to a common node 1804 of the inductors 501 and 503. A p-mos transistor 1805 is connected between the connection 525 and the node 1804 with its drain electrode connected to the connection 525. The VCO 1800 illustrates how the error control signal S3 can be injected through the inductors 510 and 503 in the single switch oscillator core. As in the VCO 1700, the error control signal S3 is delivered via a single connection, the connection 1801 in FIG. 18, based upon the assumption that the phase noise is correlated in the components of the output signal Sl at the output lines 107 and 109. The purpose of introducing the p-mos transistor 1805 is to turn the common node 1804 of the inductors 501 and 503 into a high impedance virtual ground point. The transistors 521 and 1805 are bias transistors that define the current flowing in the oscillator core of the VCO 1800. When the error control signal S3 is injected into the node 1804 from the connection 1801 it is applied through the inductors 501 to the varactor diodes 509 and 511 and modulates the capacitance of the varactor diodes 509 and 511. This modulation causes the phase noise to be reduced in the manner described earlier for the VCO 500.

A further p-mos transistor 1807 is connected at its drain electrode to the connection 525. The transistor 1807 is connected at its source electrode to the drain electrode of a further n-mos transistor 1813. The source and gate electrodes of the transistor 1807 are connected together by a connection 1811. The gate electrode of the transistor 1813 is connected via the connection 523 to the gate of the transistor 521. The source electrode of the transistor 1813 is connected to ground. A further n-mos transistor 1815 is connected at its gate electrode to the gate electrode of the transistor 1813 via a connection 1823. The source electrode of the transistor 1815 is connected to ground. The drain electrode of the transistor 1815 is connected to the gate electrode of the transistor 1815 by a connection 1819 and also to a bias current generator 1817 having an input connection 1821 delivering a control current.

The arrangement of the transistors 1807, 1813 and 1815 and the bias current generator 1817 in the VCO 1800 forms a current mirror that ensures that the current flow in the transistors 1805 and 521 is as required to balance bias current flow in the VCO 1800. The current flowing out via the n-mos transistor 521 matches that flowing in via the p-mos transistor 1805.

A third further example of an adapted VCO is a VCO

1900 shown in FIG. 19. This is an adaptation of a standard VCO known in the art as a ^Λdouble switch VCO' so that the VCO is suitable for use as the VCO 101 in the circuit 100 of FIG. 1. In the VCO 1900, the inductors 510 and 503 are replaced by a single inductor 1905 connected between the connections 513 and 515 and not connected to the connection 525. A p-mos transistor

1901 is connected at its drain electrode to the connection 525 and at its source electrode to the connection 513. Similarly, a p-mos transistor 1903 is connected at its drain electrode to the connection 525 and at its source electrode to the connection 515. The p-mos transistors 1901 and 1903 have a conductivity sense (direction of current flow) which is opposite to that of the n-mos transistors 517 and 519. A cross- coupling 1907 is shown between the transistor 1901 at its gate electrode and the connection 515, and a cross- coupling 1909 is shown between the transistor 1903 at its gate electrode and the connection 513. The arrangement described so far for the VCO 1900 is the same as the standard VCO known in the art as the double switch VCO.

In addition to the standard VCO double switch arrangement, the VCO 1900 includes an arrangement via which the error control signal S3 is delivered. The lines 137 and 139 (FIG. 1) which deliver the error control signal S3 are connected respectively to an input connection 1910 which is connected through a varactor diode 1915 to the connection 513 and to an input connection 1912 which is connected through a varactor diode 1917 to the connection 515. The input signal delivered in this way is shown by the reference symbol S3b in FIG. 19. In addition, or alternatively, an arm 1914 including back-to-back varactor diodes 1911 and 1913 is connected between the connections 513 and 515. A single connection 1916 is connected to a junction between the varactor diodes 1911 and 1913 and delivers the error control signal S3 to that junction. The input signal delivered in this way is shown by the reference symbol S3a in FIG. 19. In the case of delivery via the single connection 1916, it is again assumed that the low frequency noise on the drain electrodes of the transistors 517 and 519 at which the output lines 107 and 109 are also connected is highly correlated. The error control signal S3 (delivered either as S3a or S3b) modulates the capacitance of the varactor diodes 1915 and 1917 and/or the capacitance of the varactor diodes 1911 and 1913 thereby causing the phase noise to be reduced in the manner described earlier for the VCO 500.

A fourth further example of an illustrative adapted VCO is a VCO 2000 shown in FIG. 20. This is another adaptation of the standard double switch VCO referred to earlier so that the VCO is suitable for use as the VCO 101 in the circuit 100 of FIG. 1. In the VCO

2000 the connections 1910, 1912 and 1914 (and the varactor diodes connected to them) as shown in FIG. 19 are not present. Instead, a further inductor 2001 is connected in series with the inductor 1905 between the connections 513 and 515. A single input connection 2003 including a resistor 2005 is connected to a junction between the inductors 1905 and 2001. Use of such a single input connection is again based upon the assumption that the phase noise is correlated at the output lines 107 and 109. The error control signal S3 is injected into the junction between the inductors 1905 and 2001 from the connection 2003. It is applied to the varactor diodes 509 and 511 via the inductors 1905 and

2001 and thereby modulates the capacitance of the varactor diodes 509 and 511. This modulation causes the phase noise to be reduced in the manner described earlier for the VCO 500. It is to be noted that the phase noise performance of the standard double switch VCO is known to be improved by about 4 to 6 dB relative to the standard single switch VCO for the same power dissipation and the same supply voltage. Thus, a similar improvement may be obtained by use of the VCO 1900 or the VCO 2000 rather than the VCO 500, the VCO 1700 or the VCO 1800, although in some applications the VCO 500, the VCO 1700 or the VCO 1800 may be preferred for simplicity or cost reasons .

The circuit 100 embodying the invention, particularly when provided in the form of the integrated circuit 300, is suitable for use in RF communications transceivers, e.g. to provide carrier frequency signals for transmission or to provide local oscillator signals for use in receiver processing. The circuit 100 is particularly suitable for use in transceivers transmitting at a high power level and/or receiving at a high sensitivity level. An example of a high power transmitter level is an output RF power of at least 10 Watts modulated with a 25kHz bandwidth π/4 Differential Quadrature Phase Shift Keyed signal (DQPSK modulation) in accordance with the TETRA standard, measured at the radiator (antenna) of the transmitter. An example of a high sensitivity receiver is a receiver having a sensitivity better than -118 dBm at 3% static BER (Bit Error rate) for a π/4 Differential Quadrature Phase Shift Keyed signal (DQPSK modulation) . Such a transceiver may for example be suitable for use in a base transceiver station of a mobile wireless communication system, e.g. such as a system for operation in accordance with TETRA standards.

Claims

1. A VCO (voltage controlled oscillator) circuit including a differential mode VCO, a phase locked loop for providing a frequency control voltage to the VCO to control an operating frequency of the VCO and a negative feedback control loop operable to receive and process a differential output signal produced by the VCO, the control loop including a differential mode frequency discriminator operable to detect a phase noise content of the received signal and to deliver to the VCO via the control loop an error control signal adapted to cancel the detected phase noise content, wherein the VCO includes at least one voltage controlled device, a first input connection for applying the frequency control voltage to the at least one voltage controlled device and a second input connection for applying the error control signal, separately from the frequency control voltage, to at least one voltage controlled device of the VCO.

2. A VCO circuit according to claim 1 wherein the at least one voltage controlled device comprises a device having an electrical property which is modulated by application of a modulating control voltage.

3. A VCO circuit according to claim 2 wherein the VCO includes a resonator including at least one inductor, a first voltage controlled device and a second voltage controlled device and an input connection for applying the frequency control voltage to the first and second voltage controlled devices.

4. A VCO circuit according to claim 3 wherein the VCO includes a first transistor connected to the first voltage controlled device and a second transistor connected to the second voltage controlled device.

5. A VCO circuit according to claim 4 including at least one input connection connected to the at least one inductor for applying the error control signal through the at least one inductor to the first and second voltage controlled devices.

6. A VCO circuit according to claim 4 including a third voltage controlled device connected to the first transistor and a fourth voltage controlled device connected to the second transistor and at least one input connection for applying the error control signal to the third and fourth voltage controlled devices.

7. A VCO circuit according to claim 6 including an input connection for applying a first component of the error control signal to the third voltage controlled device and a further input connection for applying a second component of the error control signal to the fourth voltage controlled device.

8. A VCO circuit according to claim 7 wherein the first and second transistors are cross-coupled.

9. A VCO circuit according to claim 8 including a third transistor connected to the first voltage controlled device and to the first transistor and a fourth transistor connected to the second voltage controlled device and to the second transistor, the first and second transistors having a conductivity sense opposite to that of the third and fourth transistors.

10. A VCO circuit according to claim 9 wherein the at least one inductor is connected at one end to the first and third transistors and the other end to the second and fourth transistors.

11. A VCO circuit according to claim 10 wherein the third and fourth transistors are cross-coupled.

12. A VCO circuit according to claim 1 wherein the voltage controlled devices comprise varactor diodes.

13. A VCO circuit according to claim 1 wherein the differential mode frequency discriminator includes a delay unit operable to apply a time delay to a received signal produced as an output by the VCO and a combiner operable to combine the received signal with a delayed version of the received signal produced by the delay unit .

14. A VCO circuit according to claim 13 wherein the delay unit of the differential mode frequency discriminator is operable to apply a time delay equivalent to a 90 degrees phase shift to the received signal, and the combiner is a mixer operable to multiply the received signal with a delayed version of the received signal produced by the delay unit to detect the phase noise content.

15. A VCO circuit according to claim 13 wherein the differential mode frequency discriminator is operable to apply a time delay equivalent to a 180 degrees phase shift to the received signal and the combiner is a summer operable to add the received signal to a delayed version of the received signal produced by the delay unit to detect the phase noise content.

16. A VCO circuit according to claim 1 wherein the frequency discriminator comprises a differentiator for producing a derivative with respect to time of a received signal produced as an output by the VCO.

17. A VCO circuit according to claim 15 including an envelope detector for detecting an envelope of a signal produced as an output signal by the summer.

18. A VCO circuit according to claim 16 including an envelope detector for detecting an envelope of a signal produced as an output signal by the differentiator.

19. A VCO circuit according to claim 17 including a dc remover for removing a dc component of a signal produced as an output signal by the envelope detector.

20. A VCO circuit according to claim 1 wherein the feedback loop includes a low pass filter to filter an output signal produced by the frequency discriminator.

21. A VCO circuit according to claim 1 wherein the feedback loop includes an amplifier to amplify an error control signal in the feedback loop.

22. A VCO circuit according to claim 13 including a further control loop including a phase detector operable to detect an error in phase difference between a phase of the received signal and a phase of the delayed version of the received signal produced by the delay unit to produce a phase difference error control signal, the further control loop being connected to the delay unit to deliver the error control signal to the delay unit to control a time delay applied by the delay unit.

23. A VCO circuit according to claim 22 wherein the delay unit of the differential mode frequency discriminator is operable to apply a time delay equivalent to a 90 degrees phase shift and the further control loop is operable to provide an error control signal to the delay unit which locks the time delay applied by the delay unit to be equivalent to a phase delay of 90 degrees.

24. A VCO circuit according to claim 23 wherein the phase detector comprises an exclusive OR gate.

25. A VCO circuit according to claim 22 wherein the delay unit of the differential mode frequency discriminator is operable to apply a time delay equivalent to a 180 degrees phase shift and the further control loop is operable to provide an error control signal to the delay unit which locks the time delay applied by the delay unit to be equivalent to a phase delay of 180 degrees.

26. A VCO circuit according to claim 25 including a differential mode inverter operable to invert the received signal and wherein the phase detector is operable to detect a difference between a phase of an output signal produced by the delay unit and a phase of an output signal produced by the inverter.

27. A VCO circuit according to claim 26 wherein at least part of the VCO and at least part of the negative feedback control loop of the circuit are included in an integrated circuit.

28. A VCO circuit according to claim 1 including an output delivery circuit including a frequency divider operable to divide a frequency of an output signal produced by the VCO.

29. A VCO circuit according to claim 28 wherein the output circuit includes a plurality of different frequency dividers operable to provide output signals at different frequencies.

30. A VCO circuit according to claim 29 wherein the VCO oscillates at a frequency of at least 5 GHz.

31. A VCO circuit according to claim 30 wherein the VCO produces an output RF signal at one or more frequencies in the range 100 MHz to 1 GHz.