WO2008120346A1 - 回路設計支援プログラム、回路設計支援装置および回路設計支援方法 - Google Patents

回路設計支援プログラム、回路設計支援装置および回路設計支援方法 Download PDF

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Publication number
WO2008120346A1
WO2008120346A1 PCT/JP2007/056830 JP2007056830W WO2008120346A1 WO 2008120346 A1 WO2008120346 A1 WO 2008120346A1 JP 2007056830 W JP2007056830 W JP 2007056830W WO 2008120346 A1 WO2008120346 A1 WO 2008120346A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit design
design supporting
information
extracting unit
order module
Prior art date
Application number
PCT/JP2007/056830
Other languages
English (en)
French (fr)
Inventor
Ryuta Tsuchiya
Masami Matsuzaki
Ichiro Shiihara
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2007/056830 priority Critical patent/WO2008120346A1/ja
Publication of WO2008120346A1 publication Critical patent/WO2008120346A1/ja

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

　下位のモジュールを上位のモジュールにボトムアップさせる際に、制約情報抽出部（１１０１）が、所定の記憶領域から制約条件が付された下位のモジュールの所定の端子に関する情報を抽出し、回路情報抽出部（１１０２）が、上位のモジュールの回路情報を抽出し、移動先決定部（１１０３）が、制約情報抽出部（１１０１）によって抽出された所定の端子に関する情報および回路情報抽出部（１１０２）によって抽出された回路情報に基づいて、前記制約条件を移動するインスタンスのピンを決定するので、ボトムアップを効率的におこなうことができる。
PCT/JP2007/056830 2007-03-29 2007-03-29 回路設計支援プログラム、回路設計支援装置および回路設計支援方法 WO2008120346A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/056830 WO2008120346A1 (ja) 2007-03-29 2007-03-29 回路設計支援プログラム、回路設計支援装置および回路設計支援方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/056830 WO2008120346A1 (ja) 2007-03-29 2007-03-29 回路設計支援プログラム、回路設計支援装置および回路設計支援方法

Publications (1)

Publication Number Publication Date
WO2008120346A1 true WO2008120346A1 (ja) 2008-10-09

Family

ID=39807939

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/056830 WO2008120346A1 (ja) 2007-03-29 2007-03-29 回路設計支援プログラム、回路設計支援装置および回路設計支援方法

Country Status (1)

Country Link
WO (1) WO2008120346A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10394983B2 (en) * 2017-06-14 2019-08-27 Excellicon Corporation Method to automatically generate and promote timing constraints in a Synopsys Design Constraint format

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001274252A (ja) * 2000-03-24 2001-10-05 Toshiba Corp 集積回路設計方法および集積回路設計装置
JP2006324578A (ja) * 2005-05-20 2006-11-30 Matsushita Electric Ind Co Ltd 半導体集積回路の設計方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001274252A (ja) * 2000-03-24 2001-10-05 Toshiba Corp 集積回路設計方法および集積回路設計装置
JP2006324578A (ja) * 2005-05-20 2006-11-30 Matsushita Electric Ind Co Ltd 半導体集積回路の設計方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10394983B2 (en) * 2017-06-14 2019-08-27 Excellicon Corporation Method to automatically generate and promote timing constraints in a Synopsys Design Constraint format

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