WO2008115874A1 - Ajustement de la résistance de mémoire non volatile au moyen de cellules de mémoire factices - Google Patents

Ajustement de la résistance de mémoire non volatile au moyen de cellules de mémoire factices Download PDF

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Publication number
WO2008115874A1
WO2008115874A1 PCT/US2008/057245 US2008057245W WO2008115874A1 WO 2008115874 A1 WO2008115874 A1 WO 2008115874A1 US 2008057245 W US2008057245 W US 2008057245W WO 2008115874 A1 WO2008115874 A1 WO 2008115874A1
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WIPO (PCT)
Prior art keywords
volatile storage
data
storage elements
dummy
memory cells
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PCT/US2008/057245
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English (en)
Inventor
Henry Chen
Nima Mokhlesi
Dengtao Zhao
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Sandisk Corporation
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Priority claimed from US11/688,874 external-priority patent/US7535764B2/en
Application filed by Sandisk Corporation filed Critical Sandisk Corporation
Publication of WO2008115874A1 publication Critical patent/WO2008115874A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/14—Dummy cell management; Sense reference voltage generators

Definitions

  • the present invention relates to technology for non-volatile storage.
  • Non-volatile semiconductor memory has become more popular for use in various electronic devices.
  • non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices.
  • Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories.
  • Both EEPROM and flash memory utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate.
  • the floating gate and channel regions are positioned between the source and drain regions.
  • a control gate is provided over and insulated from the floating gate.
  • the threshold voltage of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate.
  • the program voltage is applied to the control gate as a series of pulses (referred to as programming pulses), with the magnitude of the pulses increasing at each pulse.
  • programming pulses a set of one or more verify operations are performed to determined whether the memory cell(s) being programmed have reached their target level. If a memory cell has reached its target level, programming stops for that memory cell. If a memory cell has not reached its target level, programming will continue for that memory cell.
  • NAND structure which includes arranging multiple transistors in series between two select gates.
  • the transistors in series and the select gates are referred to as a NAND string.
  • memory cells are programmed in a certain order wherein the memory cells on the word line that is next to the source side select gate are programmed first. Subsequently, the memory cells on the adjacent word line are programmed, followed by the programming of memory cells on the next adjacent word line, and so on, until the memory cells on the last word line next to the drain side select gate are programmed.
  • the conductivity of the channel area under those word lines usually decreases as most of the cells will be programmed to one of the programmed states (while a smaller number will stay in the erased state).
  • the IV characteristics during a subsequent read operation will be different, since less current will flow than compared to previous verify operations performed during programming.
  • the lowered current causes an artificial shift of the threshold voltages for the memory cells, which can lead to errors when reading data.
  • a block of data memory cells is manufactured with a dummy word line at the bottom of the block, at the top of the block, and/or at other locations.
  • the resistances of the NAND strings can be changed to account for shifts in resistance due to programming of data into the NAND strings (or other groups of memory cells).
  • the read process can be designed to account for a predicted amount of change to the resistance of a NAND string due to programming data into the memory cells of the NAND string.
  • the memory cells connected to the dummy word line can be programmed such that they can alter the actual change in resistance of the NAND string to be closer to the predicted amount of change to the resistance of a NAND string.
  • One embodiment includes determining information indicative of a resistance characteristic for a set of non-volatile storage elements.
  • the set of non-volatile storage elements includes data non-volatile storage elements and dummy non-volatile storage elements.
  • the process further includes programming the data non- volatile storage elements and setting one or more dummy non-volatile storage elements based on the determined resistance information.
  • Another embodiment includes determining information about group resistance for a set of non-volatile storage elements (including data and dummy non-volatile storage elements), programming the data non-volatile storage elements, and adjusting the group resistance by changing a characteristic of the one or more dummy non-volatile storage elements based on the determined information.
  • Another embodiment includes determining deviation of change in resistance for at least a subset of a set of data non-volatile storage elements with respect to a predefined change. For a given data non-volatile storage element, the change in resistance is based on pre and post programming of other data non-volatile storage elements.
  • the set of non-volatile storage elements includes data non-volatile storage elements and one or more dummy non-volatile storage elements.
  • the process also includes identifying a minimum deviation and a maximum deviation based on the determining of the deviation of change in resistance, and determining a condition for one or more of the dummy non-volatile storage elements that alter the minimum deviation and the maximum deviation in accordance with an error reduction criteria.
  • the resistance for the set of non-volatile storage elements is altered by setting the one or more of the dummy non-volatile storage elements to the determined condition.
  • Another embodiment includes determining information indicative of a resistance characteristic for a set of non-volatile storage elements.
  • the set of non-volatile storage elements includes data non-volatile storage elements and dummy non-volatile storage elements.
  • the data non-volatile storage elements are programmed, including performing verify operations.
  • the verify operations uses a first overdrive voltage for unselected data non-volatile storage elements and a second overdrive voltage for dummy data non-volatile storage elements.
  • the first overdrive voltage is lower than the second overdrive voltage.
  • One or more dummy non-volatile storage elements have their threshold voltage set to be within in a range of threshold voltages near charge-neutrality for the dummy non-volatile storage elements based on the determined resistance information.
  • One example implementation includes a set of non-volatile storage elements and one or more managing circuits in communication with the set of non-volatile storage elements.
  • the set of non-volatile storage elements includes data non-volatile storage elements and dummy non-volatile storage elements.
  • the one or more managing circuits perform the processes described above. BRIEF DESCRIPTION OF THE DRAWINGS
  • Figure 1 is a top view of a NAND string.
  • Figure 2 is an equivalent circuit diagram of the NAND string.
  • Figure 3 is a block diagram of a non- volatile memory system.
  • Figure 4 is a block diagram depicting one embodiment of a memory array.
  • Figure 5 is a block diagram depicting one embodiment of a sense block.
  • Figure 6 depicts an example set of threshold voltage distributions.
  • Figure 7 depicts an example coding of data into a set of data states associated with threshold voltage distributions.
  • Figure 8 depicts an example coding of data into a set of data states associated with threshold voltage distributions.
  • Figure 9 is a flow chart describing one embodiment for operating non-volatile memory cells.
  • Figure 10 is a flow chart describing one embodiment of a process for programming non-volatile memory cells.
  • Figure 11 is a flow chart describing one embodiment of a process for determining resistance information for data non-volatile memory cells.
  • Figures 12A-D are flow charts describing various embodiments for programming data non-volatile memory cells and setting threshold voltages for dummy non-volatile memory cells.
  • Figure 13 is a flow chart describing one embodiment of a process for determining resistance information for data non-volatile memory cells, programming data non-volatile memory cells, and setting threshold voltages for dummy non-volatile memory cells.
  • Figure 14 is a flow chart describing one embodiment of a process for determining resistance information for data non-volatile memory cells, programming data non-volatile memory cells, and setting threshold voltages for dummy non-volatile memory cells.
  • Figure 15 is a flow chart describing one embodiment of a process for determining resistance information for data non-volatile memory cells, programming data non-volatile memory cells, and setting threshold voltages for dummy non-volatile memory cells.
  • FIG. 1 is a top view showing one NAND string.
  • Figure 2 is an equivalent circuit thereof.
  • the NAND string depicted in Figures 1 and 2 includes four transistors 100, 102, 104 and 106 in series and sandwiched between a first (or drain side) select gate 120 and a second (or source side) select gate 122.
  • Select gate 120 connects the NAND string to a bit line via bit line contact 126.
  • Select gate 122 connects the NAND string to source line 128.
  • Select gate 120 is controlled by applying the appropriate voltages to select line SGD.
  • Select gate 122 is controlled by applying the appropriate voltages to select line SGS.
  • Each of the transistors 100, 102, 104 and 106 has a control gate and a floating gate.
  • transistor 100 has control gate IOOCG and floating gate 100FG.
  • Transistor 102 includes control gate 102CG and a floating gate 102FG.
  • Transistor 104 includes control gate 104CG and floating gate 104FG.
  • Transistor 106 includes a control gate 106CG and a floating gate 106FG.
  • Control gate IOOCG is connected to word line WL3
  • control gate 102CG is connected to word line WL2
  • control gate 104CG is connected to word line WLl
  • control gate 106CG is connected to word line WLO.
  • Figures 1 and 2 show four memory cells in the NAND string, the use of four transistors is only provided as an example.
  • a NAND string can have fewer than four memory cells or more than four memory cells.
  • some NAND strings will include eight memory cells, 16 memory cells, 32 memory cells, 64 memory cells, 128 memory cells, etc. The discussion herein is not limited to any particular number of memory cells in a NAND string.
  • a typical architecture for a flash memory system using a NAND structure will include several NAND strings.
  • Each NAND string is connected to the source line by its source select gate controlled by select line SGS and connected to its associated bit line by its drain select gate controlled by select line SGD.
  • select line SGS Source select gate controlled by select line SGS
  • select line SGD Drain select gate controlled by select line SGD
  • Each bit line and the respective NAND string(s) that are connected to that bit line via a bit line contact comprise the columns of the array of memory cells.
  • Bit lines are shared with multiple NAND strings.
  • the bit line runs on top of the NAND strings in a direction perpendicular to the word lines and is connected to one or more sense amplifiers.
  • Each memory cell can store data (analog or digital).
  • the range of possible threshold voltages of the memory cell is divided into two ranges which are assigned logical data "1" and "0.”
  • the threshold voltage is negative after the memory cell is erased, and defined as logic "1.”
  • the threshold voltage after programming is positive and defined as logic "0.”
  • the threshold voltage is negative and a read is attempted by applying 0 volts to the control gate, the memory cell will turn on to indicate logic one is being stored.
  • the threshold voltage is positive and a read operation is attempted by applying 0 volts to the control gate, the memory cell will not turn on, which indicates that logic zero is stored.
  • a memory cell can also store multiple levels of information (referred to as a multi-state memory cell).
  • the range of possible threshold voltages is divided into the number of levels of data. For example, if four levels of information is stored (two bits of data), there will be four threshold voltage ranges assigned to the data values "11", “10", “01”, and "00.”
  • the threshold voltage after an erase operation is negative and defined as "11". Positive threshold voltages are used for the data states of "10", "01", and "00.” If eight levels of information (or states) are stored (e.g. for three bits of data), there will be eight threshold voltage ranges assigned to the data values "000”, “001", “010", “011” “100”, “101", “110” and “111.”
  • the specific relationship between the data programmed into the memory cell and the threshold voltage levels of the cell depends upon the data encoding scheme adopted for the cells.
  • U.S. Patent No. 6,222,762 and U.S. Patent Application Publication No. 2004/0255090 both of which are incorporated herein by reference in their entirety, describe various data encoding schemes for multi-state flash memory cells.
  • data values are assigned to the threshold voltage ranges using a Gray code assignment so that if the threshold voltage of a floating gate erroneously shifts to its neighboring physical state, only one bit will be affected.
  • the data encoding scheme can be changed for different word lines, the data encoding scheme can be changed over time, or the data bits for random word lines may be inverted or otherwise randomized to reduce data pattern sensitivity and even wear on the memory cells.
  • non-volatile storage devices in addition to NAND flash memory, can also be used.
  • a so called TANOS structure consisting of a stacked layer of TaN-Al 2 ⁇ 3-SiN-Si ⁇ 2 on a silicon substrate
  • TANOS structure consisting of a stacked layer of TaN-Al 2 ⁇ 3-SiN-Si ⁇ 2 on a silicon substrate
  • Another type of memory cell useful in flash EEPROM systems utilizes a non- conductive dielectric material in place of a conductive floating gate to store charge in a non-volatile manner.
  • Such a cell is described in an article by Chan et al, "A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device," IEEE Electron Device Letters, Vol. EDL-8, No. 3, March 1987, pp. 93-95.
  • a triple layer dielectric formed of silicon oxide, silicon nitride and silicon oxide (“ONO") is sandwiched between a conductive control gate and a surface of a semi-conductive substrate above the memory cell channel.
  • the cell is programmed by injecting electrons from the cell channel into the nitride, where they are trapped and stored in a limited region. This stored charge then changes the threshold voltage of a portion of the channel of the cell in a manner that is detectable.
  • the memory cell is erased by injecting hot holes into the nitride. See also Nozaki et al., "A 1-Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Application," IEEE Journal of Solid-State Circuits, Vol. 26, No. 4, April 1991, pp. 497-501, which describes a similar memory cell in a split-gate configuration where a doped polysilicon gate extends over a portion of the memory cell channel to form a separate select transistor.
  • the programming techniques mentioned in section 1.2 of "Nonvolatile Semiconductor Memory Technology," edited by William D. Brown and Joe E. Brewer, IEEE Press, 1998, incorporated herein by reference, are also described in that section to be applicable to dielectric charge-trapping devices. Other types of memory devices can also be used.
  • Figure 3 illustrates a non-volatile storage device 210 that may include one or more memory die or chips 212.
  • Memory die 212 includes an array (two-dimensional or three dimensional) of memory cells 200, control circuitry 220, and read/write circuits 230A and 230B.
  • access to the memory array 200 by the various peripheral circuits is implemented in a symmetric fashion, on opposite sides of the array, so that the densities of access lines and circuitry on each side are reduced by half.
  • the read/write circuits 230A and 230B include multiple sense blocks 300 which allow a page of memory cells to be read or programmed in parallel.
  • the memory array 100 is addressable by word lines via row decoders 240A and 240B and by bit lines via column decoders 242A and 242B.
  • a controller 244 is included in the same memory device 210 (e.g., a removable storage card or package) as the one or more memory die 212. Commands and data are transferred between the host and controller 244 via lines 232 and between the controller and the one or more memory die 212 via lines 234.
  • One implementation can include multiple chips 212.
  • Control circuitry 220 cooperates with the read/write circuits 230A and 230B to perform memory operations on the memory array 200.
  • the control circuitry 220 includes a state machine 222, an on-chip address decoder 224 and a power control module 226.
  • the state machine 222 provides chip- level control of memory operations.
  • the on-chip address decoder 224 provides an address interface between that used by the host or a memory controller to the hardware address used by the decoders 240A, 240B, 242A, and 242B.
  • the power control module 226 controls the power and voltages supplied to the word lines and bit lines during memory operations.
  • power control module 226 includes one or more charge pumps that can create voltages larger than the supply voltage.
  • control circuitry 220 power control circuit 226, decoder circuit 224, state machine circuit 222, decoder circuit 242A, decoder circuit 242B, decoder circuit 240A, decoder circuit 240B, read/write circuits 230A, read/write circuits 230B, and/or controller 244 can be referred to as one or more managing circuits.
  • Figure 4 depicts an exemplary structure of memory cell array 200.
  • the array of memory cells is divided into M blocks of memory cells.
  • the block is the unit of erase. That is, each block contains the minimum number of memory cells that are erased together.
  • Each block is typically divided into a number of pages.
  • a page is a unit of programming.
  • One or more pages of data are typically stored in one row of memory cells.
  • a page can store one or more sectors.
  • a sector includes user data and overhead data.
  • Overhead data typically includes an Error Correction Code (ECC) that has been calculated from the user data of the sector.
  • ECC Error Correction Code
  • a portion of the controller calculates the ECC when data is being programmed into the array, and also checks it when data is being read from the array.
  • the ECCs and/or other overhead data are stored in different pages, or even different blocks, than the user data to which they pertain.
  • a sector of user data is typically 512 bytes, corresponding to the size of a sector in magnetic disk drives.
  • a large number of pages form a block, anywhere from 8 pages, for example, up to 32, 64, 128 or more pages. Different sized blocks and arrangements can also be used.
  • the bit lines are divided into even bit lines and odd bit lines. In an odd/even bit line architecture, memory cells along a common word line and connected to the odd bit lines are programmed at one time, while memory cells along a common word line and connected to even bit lines are programmed at another time.
  • Block i includes X+l bit lines and X+l NAND strings.
  • Block i also includes 64 data word lines (WLO- WL63), 2 dummy word lines (WL_d0 and WL_dl), a drain side select line (SGD) and a source side select line (SGS).
  • One terminal of each NAND string is connected to a corresponding bit line via a drain select gate (connected to select line SGD), and another terminal is connected to the source line via a source select gate (connected to select line SGS).
  • each NAND string includes sixty four data memory cells and two dummy memory cells.
  • the NAND strings can have more or less than 64 data memory cells and two dummy memory cells.
  • Data memory cells can store user or system data. Dummy memory cells are typically not used to store user or system data.
  • FIG. 5 is a block diagram of an individual sense block 300 partitioned into a core portion, referred to as a sense module 480, and a common portion 490.
  • a sense module 480 for each bit line and one common portion 490 for a set of multiple sense modules 480.
  • a sense block will include one common portion 490 and eight sense modules 480.
  • Each of the sense modules in a group will communicate with the associated common portion via a data bus 472.
  • U.S. Patent Application Publication 2006/0140007 which is incorporated herein by reference in its entirety.
  • Sense module 480 comprises sense circuitry 470 that determines whether a conduction current in a connected bit line is above or below a predetermined threshold level.
  • sense module 480 includes a circuit commonly referred to as a sense amplifier.
  • Sense module 480 also includes a bit line latch 482 that is used to set a voltage condition on the connected bit line. For example, a predetermined state latched in bit line latch 482 will result in the connected bit line being pulled to a state designating program inhibit (e.g., Vdd).
  • Common portion 490 comprises a processor 492, a set of data latches 494 and an I/O Interface 496 coupled between the set of data latches 494 and data bus 420.
  • Processor 492 performs computations. For example, one of its functions is to determine the data stored in the sensed memory cell and store the determined data in the set of data latches.
  • the set of data latches 494 is used to store data bits determined by processor 492 during a read operation. It is also used to store data bits imported from the data bus 420 during a program operation. The imported data bits represent write data meant to be programmed into the memory.
  • I/O interface 496 provides an interface between data latches 494 and the data bus 420.
  • bit line latch 482 serves double duty, both as a latch for latching the output of the sense module 480 and also as a bit line latch as described above.
  • each processor 492 will include an output line (not depicted in Fig. 5) such that each of the output lines is wired-OR'd together.
  • the output lines are inverted prior to being connected to the wired-OR line. This configuration enables a quick determination during the program verification process of when the programming process has completed because the state machine receiving the wired-OR line can determine when all bits being programmed have reached the desired level. For example, when each bit has reached its desired level, a logic zero for that bit will be sent to the wired-OR line (or a data one is inverted).
  • the state machine When all bits output a data 0 (or a data one inverted), then the state machine knows to terminate the programming process.
  • the state machine may (in some embodiments) need to read the wired-OR line eight times, or logic is added to processor 492 to accumulate the results of the associated bit lines such that the state machine need only read the wired-OR line one time.
  • the data to be programmed is stored in the set of data latches 494 from the data bus 420.
  • the program operation under the control of the state machine, comprises a series of programming voltage pulses (with increasing magnitudes) applied to the control gates of the addressed memory cells. Each programming pulse is followed by a verify process to determine if the memory cell has been programmed to the desired state.
  • Processor 492 monitors the verified memory state relative to the desired memory state. When the two are in agreement, processor 492 sets the bit line latch 482 so as to cause the bit line to be pulled to a state designating program inhibit. This inhibits the cell coupled to the bit line from further programming even if it is subjected to programming pulses on its control gate. In other embodiments the processor initially loads the bit line latch 482 and the sense circuitry sets it to an inhibit value during the verify process.
  • Data latch stack 494 contains a stack of data latches corresponding to the sense module. In one embodiment, there are 3-5 (or another number) data latches per sense module 480. In one embodiment, the latches are each one bit. In some implementations (but not required), the data latches are implemented as a shift register so that the parallel data stored therein is converted to serial data for data bus 420, and vice versa. In one preferred embodiment, all the data latches corresponding to the read/write block of m memory cells can be linked together to form a block shift register so that a block of data can be input or output by serial transfer. In particular, the bank of read/write modules is adapted so that each of its set of data latches will shift data in to or out of the data bus in sequence as if they are part of a shift register for the entire read/write block.
  • the threshold voltages of the memory cells should be within one or more distributions of threshold voltages for programmed memory cells or within a distribution of threshold voltages for erased memory cells, as appropriate.
  • Figure 6 illustrates example threshold voltage distributions corresponding to data states for the memory cell array when each memory cell stores four bits of data. Other embodiment, however, may use more or less than four bits of data per memory cell.
  • Figure 6 shows a first threshold voltage distribution or state 0 for erased memory cells. Fifteen threshold voltage distributions or states 1-15 for programmed memory cells are also depicted. In one embodiment, the threshold voltages in state 0 are negative and the threshold voltages in the states 1-15 are positive.
  • each of the data states 0-15 are read reference voltages used for reading data from memory cells. By testing whether the threshold voltage of a given memory cell is above or below the respective read reference voltage, the system can determine what state the memory cell is in.
  • each data state 1-15 At or near the lower edge of each data state 1-15 are verify reference voltages. When programming memory cells to a given state, the system will test whether those memory cells have a threshold voltage greater than or equal to the verify reference voltage.
  • the data states 0-15 can partially overlap since the ECC can handle a certain percentage of cells that are in error. Also note that the Vt axis may be offset from actual voltages applied to the control gates as body effect through source or body biasing is used to shift negative threshold voltage into the measurable positive range. Another point to note is that contrary to the equal spacing/width of the shown 16 states, various states may have different widths/spacings in order to accommodate varying amounts of susceptibility to retention loss. [0057] Each data state of Figure 6 corresponds to predetermined values for the data bits stored in the memory cells programmed to the respective states. Figure 7 is a table providing an example of the data values assigned to each data state 0-15.
  • a memory cell stores data in four different pages.
  • the four pages are referred to as the lower page, upper page, higher page and top page.
  • Figure 7 depicts the data in each page for each data state 0-15.
  • each page is programmed separately.
  • all four data bits for a memory cells are programmed at the same time.
  • Figure 8 is a table providing another example of the data values assigned to each data state 0-15.
  • the data values of Fig. 8 utilize a Gray code assignment so that only one bit changes between neighboring data states. This arrangement reduces the number of error bits if the threshold voltage of a memory cells is too low or too high.
  • FIG. 9 is a flow chart describing one embodiment for operating non-volatile memory cells.
  • memory cells are erased (in blocks or other units) prior to programming.
  • Memory cells are erased (see step 600), in one embodiment, by raising the p-well to an erase voltage (e.g., 20 volts) for a sufficient period of time and grounding the word lines of a selected block while the source and bit lines are floating. Due to capacitive coupling, the unselected word lines, bit lines, select lines, and source are also raised to a significant fraction of the erase voltage.
  • an erase voltage e.g. 20 volts
  • a strong electric field is thus applied to the tunnel oxide layers of selected memory cells and the data of the selected memory cells are erased as electrons of the floating gates are emitted to the substrate side, typically by a Fowler-Nordheim tunneling mechanism.
  • the threshold voltage of a selected cell is lowered. Erasing can be performed on the entire memory array, a block, or another unit of cells. After the block of memory cells is erased, the various memory cells can be programmed as described herein.
  • step 602 soft programming is optionally performed to narrow the distribution of erased threshold voltages for the erased memory cells. Some memory cells may be in a deeper erased state than necessary as a result of the erase process. Soft programming can apply small programming pulses to move the threshold voltage of the erased memory cells to a tighter threshold voltage distribution.
  • step 604 resistance information is determined for the data cells of each NAND string.
  • step 604 can include directly measuring resistance (absolute or relative value) or measuring a property or data that can be used to determine information directly or indirectly about resistance (absolute or relative value). More details of some of the different embodiments are provided below.
  • the invention described herein is not limited to any specific method of determining resistance information or any specific set of information indicative of a resistance characteristic.
  • the step of determining the resistance is performed by, or at the direction of, the controller. In other embodiments, the step of determining the resistance is performed by, or at the direction of, the state machine or another component.
  • the data memory cells are programmed with data (e.g., user data). For example, multiple pages of data are programmed into the memory cells connected to WL0-WL63.
  • the threshold voltages of the dummy memory cells are set based on the resistance information determined in step 604. Setting the threshold voltages of the dummy memory cells can, in some embodiments, include performing one or more programming operations. For example, the memory cells connected to WL_dO and/or WL dI can be subjected to programming and the programming could put the dummy memory cells into any of the data states 0-15. Alternatively, the dummy memory cells can have their threshold voltage set to any of a number of analog levels.
  • Changing the threshold voltage of a dummy memory cell changes the resistance of the NAND string that the dummy memory cell is a part of. Increasing the threshold voltage of the dummy memory cell increases the resistance of the NAND string. Decreasing the threshold voltage of the dummy memory cell decreases the resistance of the NAND string.
  • step 604 can be performed on a NAND string-by-NAND string basis (e.g., bit line - by - bit line basis), thereby, determining resistance information for each NAND string. Consequently, in one embodiment, the threshold voltage for each of the dummy memory cells can be individually set. By selectively programming memory cells on the dummy word lines, the resistances of the NAND strings can be individually tuned to account for changes in their individual resistance due to programming of data into the respective NAND strings.
  • a NAND string-by-NAND string basis e.g., bit line - by - bit line basis
  • steps 604 and 608 could be performed before, after, or during step 606.
  • the controller knows the user data before it is programmed into the data memory cells; therefore, step 604 can be performed prior to step 606.
  • the controller may buffer the data before programming.
  • the controller may initially program the data into multiple blocks of memory cells as binary data (one bit of data per memory cell). After enough data is stored as binary data, the data is then re- programmed into a single block as multi-level (or multi-state) data. Prior to programming the data into a single block as multi-level (or multi-state) data, the controller has access to the data in the multiple blocks of binary data. In other cases, the controller does not know the user data before it is programmed into the data memory cells; therefore, step 604 is performed after step 606.
  • step 610 the data memory cells are read and the data read is provided to the user.
  • data from the memory cells is provided to a host by the controller. Because the dummy memory cells were programmed as explained above, the error introduced from a change in resistance due to programming the data word lines is reduced for the process of reading data.
  • the selected word line is connected to a voltage, a level of which is specified for each read and verify operation in order to determine whether a threshold voltage of the concerned memory cell has reached such level.
  • the non-selected word lines are connected to an overdrive voltage (referred to as Vread) different from that of the selected word line.
  • Vread overdrive voltage
  • the overdrive voltage is typically chosen to be higher than the maximum threshold voltage that can be programmed to a data memory cell.
  • the difference between the overdrive voltage and the threshold voltage can also be referred to as the overdrive.
  • the conduction current is measured to be greater than a certain value, then it is assumed that the memory cell turned on and the voltage applied to the word line is greater than the threshold voltage of the memory cell. If the conduction current is not measured to be greater than the certain value, then it is assumed that the memory cell did not turn on and the voltage applied to the word line is not greater than the threshold voltage of the memory cell.
  • the conduction current of a memory cell is measured by the rate it discharges or charges a dedicated capacitor in the sense amplifier.
  • the conduction current of the selected memory cell allows (or fails to allow) the NAND string that included the memory cell to discharge a voltage on the bit line. The charge on the bit line is measured after a period of time to see whether it has been discharged or not.
  • Figure 10 is a flow chart describing a programming process for programming memory cells connected to a selected word line.
  • the process of Fig. 10 is performed by and/or at the direction of control circuitry 220 (state machine 222 provides the control and power control 226 provides the appropriate signals) and/or at the direction of controller 244. Because a programming process may include programming multiple pages, the programming process may include performing the process of Fig. 10 multiple times.
  • the process of Fig. 10 can be used to perform step 606 and step 608 of Fig. 9.
  • memory cells are programmed from the source side to the drain side. For example, looking at Fig. 4, word line WLO is programmed first, followed by programming WLl, followed by programming WL2, etc.
  • step 724 a "data load” command is issued by controller 244 and input to state machine 222.
  • address data designating the page address is provided to the decoder circuitry.
  • step 728 a page of program data for the addressed page(s) is input for programming. For example, 528 bytes of data could be input in one embodiment. That data is latched in the appropriate registers/latches for the selected bit lines. In some embodiments, the data is also latched in a second register for the selected bit lines to be used for verify operations.
  • step 730 a "program" command is received from controller 244 and provided to state machine 222.
  • step 728 the data latched in step 728 will be programmed into the selected memory cells controlled by state machine 222 using a set of pulses applied to the appropriate word line.
  • Vpgm the programming voltage signal (e.g., the set of pulses)
  • a program counter PC maintained by state machine 222 is initialized at 0.
  • step 734 a pulse of the program signal Vpgm is applied to the selected word line.
  • step 736 the data states of the selected memory cells are verified using the appropriate set of target levels. If it is detected that the threshold voltage of a selected memory cell has reached the appropriate target level, then the memory cell is locked out of future programming for the remainder of the process of Fig. 10 by raising its bit line voltage. If all memory cells being programmed have reached their target data states (step 738), then the programming process is complete and successful. A status of "PASS" is reported in step 740. Note that in some implementations of step 738, it is checked whether at least a predetermined number of memory cells have been verified to have reached their target states. This predetermined number can be less than the number of all memory cells, thereby allowing the programming process to stop before all memory cells have reached their appropriate verify levels. The memory cells that are not successfully programmed can be corrected using error correction during the read process.
  • step 738 If, in step 738, it is determined that not all of the memory cells have reached their target states, then the programming process continues.
  • step 750 the program counter PC is checked against a program limit value.
  • a program limit value is 20; however, other values can be used in various implementations. If the program counter PC is not less than the program limit value, then it is determined in step 766 whether the number of memory cells that have not been successfully programmed is equal to or less than a predetermined number. If the number of unsuccessfully programmed memory cells is equal to or less than the predetermined number, then the programming process is flagged as passed and a status of PASS is reported in step 768. In many cases, the memory cells that are not successfully programmed can be corrected using error correction during the read process.
  • step 770 If, however, the number of unsuccessfully programmed memory cells is greater than the predetermined number, the program process is flagged as failed and a status of FAIL is reported in step 770. If, in step 760, it is determined that the program counter PC is less than the program limit value, then the magnitude of the next Vpgm pulse is increased by the step size (e.g., 0.2 - 0.4 volt step size) and the program counter PC is incremented in step 762. After step 762, the process loops back to step 734 to apply the next Vpgm pulse.
  • step size e.g., 0.2 - 0.4 volt step size
  • Figure 11 is a flow chart describing one embodiment of a process for determining resistance information for data non-volatile memory cells (step 604 of Fig. 9). The process of Fig. 11 is performed individually (and in some cases simultaneously) for each NAND string. In step 802, the next data memory cell is considered. If this is the first time that step 802 is being performed, then the first data memory cell (e.g., connected to WLO) of the NAND string is accessed.
  • the first data memory cell e.g., connected to WLO
  • step 804 the system characterizes change of resistance experienced by the data memory cells on the NAND string that is currently under consideration.
  • Each memory cell experiences a change in resistance relative to all of the memory cells programmed subsequent to that memory cell.
  • the memory cell connected to WL3 will experience a change in resistance due to the programming of the memory cells connected to WL4-WL63.
  • the change in relative resistance will be with respect to before the memory cells on WL4-WL63 are programmed in comparison to after the memory cells connected to WL4-WL63 are programmed.
  • There are many ways to measure this change in resistance One method is to measure the actual resistance values. Another embodiment is to estimate the change of resistance based on the data programmed into the memory cells. Other methods can also be used.
  • the embodiment of Figure 11 characterizes the change in resistance based on the data programmed into the memory cells.
  • the change of resistance is characterized by comparing the actual data programmed to an even distribution of data and determining the deviation from the even distribution.
  • An even distribution of data exists when all data states are represented equally (or as close to equal as possible). In an example where there are sixty-four data memory cells on a NAND string and sixteen data states, each data state will appear four times on a NAND string if there is an even distribution of data.
  • Step 804 will characterize the difference between the actual data programmed and an even distribution of data, and use that difference to program the dummy memory cells.
  • 11/421,667 "Verify Operation For Non-Volatile Storage Using Different Voltages," filed on June 1, 2006, incorporated herein by reference in its entirety, describes a system that when performing a data sensing operation, including a verify operation during programming of nonvolatile storage elements, a first voltage is used for unselected word lines that have been subjected to a programming operation and a second voltage is used for unselected word lines that have not been subjected to a programming operation.
  • This system accounts for the change of resistance during programming and can be tuned to account for an even distribution of data.
  • the technique can also be used during read operations.
  • step 804 the system determines the deviation from an even distribution of data. For the data memory cell under consideration, step 804 looks at all the memory cells programmed subsequent to that memory cell. For example, if the memory cell connected to WL3 is under consideration, then step 804 will include looking at all the memory cells connected to WL4-WL63.
  • the system can characterize the deviation from the even distribution in many different ways. One example is to assign a number value to each data state; for example, data state 0 is assigned 0, data state 1 is assigned 1, data state 2 is assigned 2, data state 3 is assigned 3, ..., data state 15 is assigned 15. The system can add up the assigned numbers for each data state of actual data and divide by the number of memory cells. Thus an average will be calculated.
  • Step 808 performs the calculation to determine the deviation value for one data memory cell on a NAND string and that determined deviation value is stored in step 806.
  • step 808 it is determined whether there are any more memory cells on the NAND string to consider. If there are more memory cells on the NAND string to consider, the process loops back to step 802 and considers the next memory cell. Thus, the loop of steps 802-806 is performed once for each memory cell on the NAND string. After there are no more memory cells on the NAND string to consider (step 808), then the maximum deviation and the minimum deviation are identified in step 810.
  • step 812 the system determines an adjustment to both the maximum deviation and the minimum deviation so that the minimum deviation is below zero change, the maximum deviation is above zero change, the difference between maximum deviation and zero change is minimized, and the difference between the minimum deviation and zero change is minimized.
  • step 814 the system determines the threshold voltages to program the dummy memory cells in order to achieve the adjustment of step 812. Note that centering the minimum and maximum deviation about zero change with respect to the average is just one example of an error reduction criterion that can be used. Other error reduction criteria can also be used.
  • the reason for adjusting the maximum deviation and minimum deviation to be about zero change is because zero change represents the even distribution.
  • the adjustment represents the difference in resistance between the actual data and the even distribution of data.
  • programming the dummy memory cells the resistance to the NAND string can be changed.
  • programming the dummy memory cells based on the adjustments of step 812 seeks to change the resistance of NAND string to move toward a resistance for a NAND string with an even distribution.
  • the read process is equipped to account for change in resistance due to an even distribution of data.
  • the NAND string if the NAND string has its maximum deviation and minimum deviation both equal to zero, then the NAND string is the even distribution and both dummy memory cells (WL dO and WL dI) are set to be in data state 7. That is, the threshold voltage of the dummy memory cells are raised so that they are in the threshold voltage distribution corresponding to data state 7. If the NAND string has data resulting in a lower resistance than the even distribution, then the resistance to the NAND string can be increased by programming the dummy memory cells to a data state higher than 7. If the NAND string has a resistance greater than the even distribution, then the resistance of the NAND string can be lowered by programming the dummy memory cells to a state lower than data state 7.
  • dummy memory cells will only be programmed into data state 0, 7 and 15.
  • the memory cells can be programmed into any of the data states, thereby, providing more resolution in how the resistance of the NAND string is tuned.
  • the threshold voltage need not be programmed into a data state. Rather, the threshold voltage can be any analog value between zero and the maximum allowed threshold voltage. In one example, the maximum allowed threshold voltage is at least 2 volts less than the overdrive voltage used on non-selected word lines during the read process.
  • the dummy memory cells can be programmed to minimize the average of the square of the deviations for all of the memory cells on the NAND string.
  • the system can seek to minimize the number of memory cells in the NAND string with resistance changes that fall outside a range of resistance changes that have negligible impact on the overall Vt distribution.
  • step 814 may call for a larger (or lower) dummy threshold than is possible.
  • the dummy cell(s) are programmed to the maximum (or minimum) threshold voltage possible.
  • Figures 12A-12D provide various embodiments describing the order of programming the data memory cells and setting the threshold voltages for the dummy memory cells.
  • Figure 12A provides an example that includes the dummy memory cells being programmed after the data memory cells.
  • step 850 all the data memory cells are programmed.
  • step 852 the threshold voltage for the dummy memory cells are set after programming the data memory cells. Because the dummy memory cells are programmed after the programming of the data memory cells, the process of Figure 11 can be performed by looking at the actual data in the memory cells. On the other hand, Figure 11 can also be performed based on data the controller has stored in a buffer or in other blocks (as described above).
  • Figure 12B describes an embodiment that uses only one of the dummy memory cells per NAND string.
  • step 860 all the data memory cells are programmed.
  • step 862 the threshold voltage for the one dummy memory cell per NAND string is set.
  • the one dummy memory cell is on word line WL dI.
  • the determination of which dummy word line to use to effect resistance can be made dynamically.
  • Figure 12C describes an embodiment where (for a NAND string) one dummy memory cell is programmed after a subset of the data memory cells have been programmed and the other dummy memory cell is programmed after programming all the data memory cells.
  • the system programs data memory cells for the first half (or different fraction) of the word lines (e.g. WL0-WL31).
  • the threshold voltage for each of the dummy memory cell(s) connected to WL_dO are set.
  • the remaining data memory cells are programmed (e.g. for WL32-WL63).
  • the system sets the threshold voltage(s) for the dummy memory cells connected to WL_dl.
  • the controller has access to all of the data for all of the word lines at the time of performing step 872; therefore, the dummy memory cells connected to WL_d0 are set based on data for all of the word lines.
  • the controller (or other relevant entity) only has access to the data that has been programmed into the data memory cells in step 870. In the latter case, the dummy memory cells connected to WL dO are set based on the contents of the data memory cells connected to the first half (or different fraction) of the word lines (e.g. WLO- WL31).
  • step 876 the system sets the threshold voltage for the dummy memory cells connected to WL dI based on data for all of the word lines.
  • Figure 12D provides another embodiment where all the dummy memory cells are programmed after starting to program the data memory cells and prior to completing programming of all data memory cells.
  • step 880 data memory cells are programmed for the first group of word lines.
  • step 882 the threshold voltages are set for dummy memory cells connected to WL_d0.
  • step 884 memory cells connected to the second group of word lines are programmed.
  • step 886 the threshold voltage is set for dummy memory cells connected to WL_dl.
  • step 888 memory cells connected to the third group of word lines are programmed.
  • the first group of word lines includes WL0-WL21
  • the second group of word lines includes WL22-WL42
  • the third group of word lines includes WL43- WL63.
  • the three groups can include different members.
  • Figure 13 provides another embodiment of determining resistance information for data memory cells, programming the data memory cells, and setting the threshold voltage of the dummy memory cells based on the resistance information.
  • the change in resistance for a NAND string is estimated by the number of memory cells in a high data state.
  • the NAND string can be broken up into three groups. The first group includes word lines WL0-WL21, the second group includes WL22-WL42 and the third group includes WL43-WL63.
  • the system determines the number of high data states in the second group of memory cells. Assume that states 12-15 are high data states. Thus, the system will count the number of memory cells in the second group that have data stored in data states 12-15.
  • the high data states are associated with higher threshold voltages, which have a greater impact on resistance.
  • the system will count the number of memory cells in the third group that are in high data states.
  • the first group of memory cells will be programmed with user data.
  • the dummy memory cells connected to WL dO will be programmed based on the number of high data states in the second group and the third group of data memory cells. In one embodiment, the number of memory cells in the second group and third group that are in a high resistance state are compared to the number of memory cells that would be in the high resistance state for the even distribution. This deviation will be used to set the threshold voltage of the dummy memory cell to data state zero, data state 7 or data state 15.
  • step 910 the second group of memory cells are programmed.
  • step 912 dummy memory cells connected to WL_dl are programmed based on the number of memory cells in the third group that are in the high data state as compared to the even distribution of cells.
  • step 914 the third group of data memory cells are programmed.
  • the high data state can include other sets of states, such as data states 8-15 or other grouping of data states.
  • all of the dummy memory cells can all be programmed after all data memory cells are programmed, based on the deviation between the number of memory cells in group two and three (or just group three) as compared to the analogous set of data memory cells with an even distribution.
  • the dummy memory cells connected to WL_d0 will be programmed (after the first group of data memory cells) based on the number of data memory cells in the first group that are in the high state.
  • the dummy memory cells connected to WL_dl will be programmed (after the all three groups of data memory cells) based on the number of data memory cells in all three groups that are in the high state.
  • Figure 14 provides another embodiment for determining resistance information, programming data memory cells and setting the threshold voltage of dummy memory cells.
  • the data memory cells are programmed.
  • the system counts the number of data memory cells in the high data state. In one embodiment, the system will consider all the data memory cells. In another embodiment, the system only considers whether an upper group of data memory cells are in a high data state.
  • the upper group of data memory cells can be the top half of word lines (e.g. WL32-WL63), the top one third of word lines, or other groupings.
  • the dummy memory cells are programmed or otherwise have their threshold voltage set based on the number of memory cells counted in step 934 as compared to the even distribution of memory cells.
  • Figure 15 provides another embodiment for determining resistance information, programming data memory cells and, setting the threshold voltage for dummy memory cells.
  • step 960 data is programmed into all the data memory cells.
  • step 962 the system performs a physical measurement of resistance information for the NAND strings.
  • There are many ways to physically measure resistance information For example, to measure the resistance of one or more transistors (set A) in a NAND string, have their control gate voltage set to be relatively lower than the normal overdrive voltage used during a read process. For all other transistors (set B) on the NAND string, the control gate voltage is set to the normal overdrive voltage used during a read process. In this way, the resistances of set A will dominate the overall series resistance of the entire NAND string.
  • the system can find the series resistance by setting the bit line voltage to some value and measuring the current.
  • One embodiment is described in United States Patent Application No. 11/617,972, "Resistance Sensing and Compensation for Non-Volatile Storage,” filed on December 29, 2006, incorporated herein by reference in its entirety.
  • set A could be the entire NAND string.
  • target threshold voltages for the dummy memory cells are determined based on the measured resistance data from step 962. For example, the physical measurements can determine whether a particular NAND string is a high resistance or low resistance NAND string. If it is a low resistance NAND string, then the dummy memory cells can be programmed to data state twelve. If the NAND string is a high resistance NAND string, the dummy memory cells can be programmed to data state four. In step 966, the dummy memory cells are programmed based on the determined threshold voltage levels determined in step 964.
  • the non- selected word lines are connected to an overdrive voltage that is typically chosen to be higher than the maximum threshold voltage that can be programmed to a data memory cell.
  • the difference between the overdrive voltage and the threshold voltage is referred to as the overdrive.
  • the resistance of a non-selected memory cell is a non-linear function of the overdrive. In particular, the resistance is very sensitive to the overdrive when the overdrive is close to zero, but relatively insensitive for large overdrive.
  • the dummy memory cells are operated with overdrive close to zero. Consequently, the overdrive voltage for the dummy memory cells can be set to a lower voltage than for the typical data memory cell so that the overdrive voltage is closer to the threshold voltage of the dummy memory cell.
  • the dummy memory cells can be programmed to a narrower range of threshold voltages when compared to data memory cells.
  • the dummy memory cells can have their threshold voltages set near the charge-neutrality condition of the floating gate, which is the condition where there are as many protons as electrons.
  • the dummy memory cells can have a lower overdrive voltage (as compared to data memory cells ) and have their threshold voltages set to the charge-neutrality condition, slightly above the charge-neutrality condition or slightly below the charge-neutrality condition (instead of data states 0, 7 and 15), depending on how the above processes need to change the resistance of the NAND string.
  • This configuration can be used with the process described above.

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Abstract

Dans certains systèmes de stockage non volatiles, un bloc de cellules de mémoire de données est fabriqué avec une ligne de mots factices sur le bas du bloc, sur le haut du bloc, et/ou à d'autres emplacements. En programmant de manière sélective les cellules de mémoire sur la ou les lignes de mots factices, les résistances associées aux cellules de mémoire de données peuvent être modifiées pour tenir compte de différents motifs de données programmés.
PCT/US2008/057245 2007-03-21 2008-03-17 Ajustement de la résistance de mémoire non volatile au moyen de cellules de mémoire factices WO2008115874A1 (fr)

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US68887507A 2007-03-21 2007-03-21
US11/688,874 2007-03-21
US11/688,874 US7535764B2 (en) 2007-03-21 2007-03-21 Adjusting resistance of non-volatile memory using dummy memory cells
US11/688,875 2007-03-21

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EP0801398A2 (fr) * 1996-04-09 1997-10-15 Information Storage Devices, Inc. Procédé et dispositif pour stockage analogique, utilisant des structures à grilles flottantes non-et
US5696717A (en) * 1995-10-16 1997-12-09 Samsung Electronics Co., Ltd. Nonvolatile integrated circuit memory devices having adjustable erase/program threshold voltage verification capability

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