WO2008106304A1 - Source/drain stressor and method therefor - Google Patents
Source/drain stressor and method therefor Download PDFInfo
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- WO2008106304A1 WO2008106304A1 PCT/US2008/053563 US2008053563W WO2008106304A1 WO 2008106304 A1 WO2008106304 A1 WO 2008106304A1 US 2008053563 W US2008053563 W US 2008053563W WO 2008106304 A1 WO2008106304 A1 WO 2008106304A1
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- semiconductor device
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- sidewall spacer
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 239000004065 semiconductor Substances 0.000 claims abstract description 119
- 239000000463 material Substances 0.000 claims abstract description 54
- 125000006850 spacer group Chemical group 0.000 claims abstract description 41
- 239000007943 implant Substances 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000000137 annealing Methods 0.000 claims abstract 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 11
- 238000011065 in-situ storage Methods 0.000 claims description 10
- 229910052785 arsenic Inorganic materials 0.000 claims description 6
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 6
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 claims description 5
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 5
- 206010010144 Completed suicide Diseases 0.000 claims description 4
- 229910052787 antimony Inorganic materials 0.000 claims description 4
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 4
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 claims description 4
- 239000002019 doping agent Substances 0.000 claims description 4
- 229910052738 indium Inorganic materials 0.000 claims description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 claims 4
- 229910015890 BF2 Inorganic materials 0.000 claims 3
- 239000010410 layer Substances 0.000 description 36
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
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- 239000002356 single layer Substances 0.000 description 2
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- 238000002360 preparation method Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H—ELECTRICITY
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
Definitions
- This disclosure relates generally to semiconductor devices, and more specifically, to semiconductor devices having source/drain stressors.
- Source/drain stressors have been developed to provide strain in channel regions to improve transistor performance. Tensile stress applied to the channel has been found to improve electron mobility for N channel transistors while compressive stress applied to the channel has been found to improve hole mobility. The degree of improvement is generally greater with greater stress being applied.
- the source/drain stressor approach involves removing the semiconductor material near the channel area to form recess regions there and then filling recess regions by growing a semiconductor material of a different type. With silicon being the starting semiconductor material, which is typical, the tensile stress can be exerted by growing silicon carbon and the compressive can be exerted by growing silicon germanium. One limitation on the stress is the carbon and germanium concentrations.
- FIG. 1 is a cross section of a semiconductor device at a stage in a process of one embodiment
- FIG. 2 is a cross section of the semiconductor device of FIG. 1 at a subsequent stage in processing
- FIG. 3 is a cross section of the semiconductor device of FIG. 2 at a subsequent stage in processing
- FIG. 4 is a cross section of the semiconductor device of FIG. 3 at a subsequent stage in processing
- FIG. 5 is a cross section of the semiconductor device of FIG. 4 at a subsequent stage in processing
- FIG. 6 is a cross section of the semiconductor device of FIG. 1 at a subsequent stage in processing
- FIG. 7 is a cross section of the semiconductor device of FIG. 6 at a subsequent stage in processing.
- FIG. 8 is a cross section of a semiconductor device similar to that of FIG. 1 at stage in a process according to anther embodiment.
- An angled implant is performed from the source side of a transistor to form a source implant region that is at least nearly under the edge of the gate.
- the gate has a thin sidewall spacer at the time of the implant.
- the gate acts as a mask for the drain side so that the doped region formed on the drain side by the implant is spaced from the gate.
- a subsequent anneal ensures that the source side doped region is at least aligned to the edge of the gate and may extend under the gate a small amount.
- An etch removes semiconductor material using the gate and sidewall spacer as a mask to form one recess region aligned on the source with the thin sidewall spacer and another recess region aligned on the drain side with the thin sidewall spacer.
- Forming the recess region on the drain side removes the doped region formed by the implant on the drain side.
- the source implant region has a portion that extends under the sidewall spacer so that it is not removed by forming the source side recess region.
- a semiconductor material of a different type is then grown in the recess regions. This different semiconductor material then contacts the remaining portion of the source implant region and also forms a drain on the drain side.
- the different semiconductor material is preferably in situ doped to avoid the need for a source/drain implant that would tend to relax the strain.
- the remaining portion of the source implant region thus ensures that source extends at least to the edge of the gate. This is of minimal consequence on the drain side because a voltage applied to the drain will tend to deplete the region immediately adjacent to the drain anyway. Further, having it on the drain side would increase the overall parasitic capacitance. This is better understood by the following description and the drawings.
- FIG. 1 Shown in FIG. 1 is a semiconductor device 10 comprising a sustaining substrate 12, an insulating layer 14 over sustaining substrate 12, a semiconductor layer 16 over insulating layer 14, an isolation region 18 establishing a boundary for semiconductor layer 16, a gate dielectric 20 over a portion of semiconductor layer 16, a gate 22 over gate dielectric 20, and a sidewall spacer 24 on the sidewalls of gate 22.
- the combination of sustaining substrate 12, insulating layer 14, and semiconductor layer 16 is a semiconductor on insulator (SOI) substrate which is a common substrate.
- SOI semiconductor on insulator
- a bulk semiconductor type of substrate having no insulating layer may also be used. In such case the top portion of the substrate could be considered a semiconductor layer.
- semiconductor layer 16 may be multi-layer.
- semiconductor layer 16 could be a silicon, underlying and relatively thicker, layer with an overlying, thinner SiGe layer.
- Gate 22 may be multiple layers or a single layer. A single layer of polysilicon is effective for this purpose, but a metal layer or layers or a combination of metal and silicon layers may also be used.
- Gate dielectric 20 is preferably a grown oxide, which is typical for gate dielectrics, but another material may be used. For example a high K dielectric may be used.
- Sidewall spacer 24 is preferably formed of nitride but another material may be used. Sidewall spacer 24 is preferably relatively thin. In this described example, sidewall spacer 24 is preferably about 50 Angstroms in thickness, but could vary. An expected range is about 40 to 100 Angstroms but that could vary as well.
- FIG. 2 Shown in FIG. 2 is semiconductor device after performing an angled implant 26.
- the angle is preferably about 10 degrees from vertical directed toward a source side so that gate 22 acts as a mask for a drain side. Other angles may also be effective such as 5 to 30 degrees.
- Angled implant 26 results in forming a doped region 28 and a doped region 30.
- Doped region 28 is on the source side.
- Doped region 30 is on the drain side.
- Doped region 28 has a portion that extends under sidewall spacer 24.
- Doped region 30, on the other hand, is spaced from gate 22 and sidewall spacer 24.
- Implant 26 is a species useful in forming sources and drains.
- implant 26 may be an implant of arsenic or phosphorus or both.
- implant 26 may be an implant of boron or boron di-fluoride (BF 2 ).
- the depth of doped region 28 is chosen to be the depth that is desired for the depth of the source at the interface with the channel.
- the degree to which doped region 28 extends under sidewall spacer 24 and potentially gate 22 can be determined by the angle and the energy. In this example, doped region 28 extends to about the edge of the gate, which is the interface between gate 22 and sidewall spacer 24 on the source side.
- the energy is also used for setting the depth.
- the angle also has an effect on the depth.
- FIG. 3 Shown in FIG. 3 is semiconductor device 10 after an anneal that has the affect of expanding doped regions 28 and 30 as well as activating dopants in doped region 28. This anneal ensures that doped region 28 at least extends to the edge of gate 22 and will typically extend a little amount under gate 22.
- FIG. 4 Shown in FIG. 4 is semiconductor device 10 after an etch using sidewall spacer 24 and gate 22 as a mask to result in a recess 32 on the source side aligned to sidewall spacer 24 and a recess 34 on the drain side aligned to sidewall spacer 24.
- Recesses 32 and 34 leave some of semiconductor layer 16 between recesses 32 and 34 and insulating layer 14. Recesses 32 and 34 can be viewed as being on opposite ends of sidewall spacer 24.
- semiconductor device 10 after forming semiconductor region 36 in recess 32 and semiconductor region 38 in recess 34 by epitaxial growth.
- Semiconductor regions 36 and 38 are stressors for a channel region directly under gate dielectric 20 and between the remaining portion of doped region 28 and semiconductor region 38.
- semiconductor regions 36 and 38 exert a tensile stress.
- the tensile stress may be achieved by growing silicon carbon (SiC) to form semiconductor regions 36 and 38.
- semiconductor regions 36 and 38 exert a compressive stress.
- the compressive stress may be achieved by growing silicon germanium (SiGe) to form semiconductor regions 36 and 38.
- the stress arises from the lattice constant of the seed layer being different from the natural lattice constant of the semiconductor region being grown.
- the grown semiconductor layer is forced into the lattice structure of the seed layer and thereby is caused to exert stress.
- a clean of semiconductor layer 16 Prior to performing the epitaxial growth, a clean of semiconductor layer 16 must normally be performed. It is generally not feasible to avoid forming a layer of native oxide on semiconductor layer 16 after performing the etch that forms recesses 32 and 34.
- it is desirable for the layer functioning as a seed to be free from other materials. This is particularly true, as in the case for forming semiconductor regions 36 and 38, when the grown materials need to be free of dislocations.
- a clean of the surface is performed. Necessarily this will normally be a chemistry, such as HF, that will remove oxide.
- the clean can also be a combination of multiple steps.
- One example is the use of an HF wet clean followed by a hydrogen gaseous prebake that is done in situ within the epitaxial chamber.
- gate dielectric 20 is oxide
- the remaining portion of doped region 28 protects gate dielectric 20 from the chemistry used for the clean on the source side.
- the portion of semiconductor layer 16 under sidewall spacer 24 protects gate dielectric 20 from the chemistry used for the clean.
- Semiconductor regions 36 and 38 can be in situ doped in that they may be doped to the desired conductivity type, P or N, during their growth.
- P type the in situ doping will normally be boron and for N type, phosphorus or arsenic or both.
- semiconductor regions 36 and 38 are formed to be the same conductivity type as doped region 28. In such case, semiconductor region 36 and the remaining portion of doped region 28 form a continuous conductivity type suitable for functioning as a source.
- An anneal step which may replace the previously described anneal step, may be performed after semiconductor regions 36 and 38 are grown but there is a risk that will cause relaxation of the stress or excessive dopant diffusion. Thus, it is expected that it would normally be better to perform any anneals before growing semiconductor regions 36 and 38.
- FIG. 6 Shown in FIG. 6 is semiconductor device 10 after forming sidewall spacer 40 on the sidewall of spacer 24.
- Sidewall spacer 40 is preferably nitride but could be another material or combination of materials.
- Sidewall spacer 40 is preferably thicker than sidewall spacer 24. An example of such a lateral thickness is about 400 Angstroms at the thickest point.
- semiconductor device 10 Shown in FIG. 7 is semiconductor device 10 after forming suicide regions 42 and 44 on the top surface of semiconductor regions 36 and 38. Sidewall spacers, in conventional fashion, protect the channel and the gate dielectric from the suicide. Deep source/drain formation by such as implantation may be conducted prior to suicide formation. Further processing, such as forming interlayer dielectric layers and contract layers, may continue.
- a drain side protection layer is applied for forming doped regions on only the source side after gate stack formation.
- semiconductor device 10 of FIG. 1 with a patterned photoresist layer 50 exposing the source side and covering the drain side.
- An implant and anneal are performed after the photoresist patterning. Due to the masking of the patterned photoresist layer 50, the implant and anneal results in a doped region 28 as shown in FIG. 3 but with no doped region on the drain side. Processing continues as shown in FIGs. 4-7 to achieve a semiconductor device with source/drain stressors.
- the semiconductor layer could itself be multiple layers.
- One such example would be a silicon layer with a SiGe layer immediately over the silicon layer. In such case the etch which forms the recesses would remove both SiGe and silicon. SiGe may be regrown replacing the combination of silicon and SiGe.
- indium or BF 2 may be used for P type doping and antimony may be used for N type doping.
- the dimensions given are exemplary and other dimensions may be used.
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Abstract
Description
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Priority Applications (4)
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KR1020097017872A KR101399208B1 (en) | 2007-02-28 | 2008-02-11 | Source/drain stressor and method therefor |
EP08729512A EP2115778A4 (en) | 2007-02-28 | 2008-02-11 | Source/drain stressor and method therefor |
JP2009551780A JP5559547B2 (en) | 2007-02-28 | 2008-02-11 | How to make a semiconductor device |
CN2008800064701A CN101622713B (en) | 2007-02-28 | 2008-02-11 | Source/drain stressor and method therefor |
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US11/680,181 | 2007-02-28 | ||
US11/680,181 US7572706B2 (en) | 2007-02-28 | 2007-02-28 | Source/drain stressor and method therefor |
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PCT/US2008/053563 WO2008106304A1 (en) | 2007-02-28 | 2008-02-11 | Source/drain stressor and method therefor |
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US (1) | US7572706B2 (en) |
EP (1) | EP2115778A4 (en) |
JP (1) | JP5559547B2 (en) |
KR (1) | KR101399208B1 (en) |
CN (1) | CN101622713B (en) |
TW (1) | TWI436431B (en) |
WO (1) | WO2008106304A1 (en) |
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WO2008015211A1 (en) | 2006-08-01 | 2008-02-07 | Koninklijke Philips Electronics N.V. | Effecting selectivity of silicon or silicon-germanium deposition on a silicon or silicon-germanium substrate by doping |
KR100746232B1 (en) * | 2006-08-25 | 2007-08-03 | 삼성전자주식회사 | Mos transistor having a strained channel and method of fabricating the same |
US20080248598A1 (en) * | 2007-04-09 | 2008-10-09 | Rohit Pal | Method and apparatus for determining characteristics of a stressed material using scatterometry |
US7745847B2 (en) * | 2007-08-09 | 2010-06-29 | United Microelectronics Corp. | Metal oxide semiconductor transistor |
US20100102393A1 (en) * | 2008-10-29 | 2010-04-29 | Chartered Semiconductor Manufacturing, Ltd. | Metal gate transistors |
US8124487B2 (en) * | 2008-12-22 | 2012-02-28 | Varian Semiconductor Equipment Associates, Inc. | Method for enhancing tensile stress and source/drain activation using Si:C |
US20110049582A1 (en) * | 2009-09-03 | 2011-03-03 | International Business Machines Corporation | Asymmetric source and drain stressor regions |
US8928094B2 (en) * | 2010-09-03 | 2015-01-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained asymmetric source/drain |
CN102456739A (en) * | 2010-10-28 | 2012-05-16 | 中国科学院微电子研究所 | Semiconductor structure and forming method thereof |
CN102683385B (en) * | 2012-05-30 | 2014-12-24 | 清华大学 | Semiconductor structure and forming method of semiconductor structure |
KR20140042460A (en) * | 2012-09-28 | 2014-04-07 | 삼성전자주식회사 | Semiconductor device |
KR102137371B1 (en) * | 2013-10-29 | 2020-07-27 | 삼성전자 주식회사 | Semiconductor device and method for fabricating the same |
CN106960838B (en) * | 2016-01-11 | 2019-07-02 | 中芯国际集成电路制造(上海)有限公司 | Electrostatic protection device and forming method thereof |
US10032868B2 (en) | 2016-09-09 | 2018-07-24 | Texas Instruments Incorporated | High performance super-beta NPN (SBNPN) |
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JPS6313378A (en) * | 1986-07-04 | 1988-01-20 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device and manufacture thereof |
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2008
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- 2008-02-11 CN CN2008800064701A patent/CN101622713B/en not_active Expired - Fee Related
- 2008-02-11 WO PCT/US2008/053563 patent/WO2008106304A1/en active Application Filing
- 2008-02-11 EP EP08729512A patent/EP2115778A4/en not_active Withdrawn
- 2008-02-11 JP JP2009551780A patent/JP5559547B2/en not_active Expired - Fee Related
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US6833307B1 (en) * | 2002-10-30 | 2004-12-21 | Advanced Micro Devices, Inc. | Method for manufacturing a semiconductor component having an early halo implant |
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Also Published As
Publication number | Publication date |
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TWI436431B (en) | 2014-05-01 |
CN101622713B (en) | 2013-10-23 |
JP2010520620A (en) | 2010-06-10 |
KR101399208B1 (en) | 2014-05-27 |
JP5559547B2 (en) | 2014-07-23 |
KR20090125757A (en) | 2009-12-07 |
US20080203449A1 (en) | 2008-08-28 |
US7572706B2 (en) | 2009-08-11 |
EP2115778A1 (en) | 2009-11-11 |
TW200847299A (en) | 2008-12-01 |
CN101622713A (en) | 2010-01-06 |
EP2115778A4 (en) | 2011-11-02 |
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