WO2008103454A2 - Système à plasma pulsé pour gravure des structures à semi-conducteurs - Google Patents

Système à plasma pulsé pour gravure des structures à semi-conducteurs Download PDF

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Publication number
WO2008103454A2
WO2008103454A2 PCT/US2008/002368 US2008002368W WO2008103454A2 WO 2008103454 A2 WO2008103454 A2 WO 2008103454A2 US 2008002368 W US2008002368 W US 2008002368W WO 2008103454 A2 WO2008103454 A2 WO 2008103454A2
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WIPO (PCT)
Prior art keywords
state
plasma
etch
sample
duty cycle
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PCT/US2008/002368
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English (en)
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WO2008103454A3 (fr
Inventor
Tae Won Kim
Kyeong-Tae Lee
Alexander Paterson
Valentin N. Todorow
Shashank C. Deshmukh
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Applied Materials, Inc.
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Priority claimed from US11/677,472 external-priority patent/US7718538B2/en
Priority claimed from US11/678,041 external-priority patent/US7737042B2/en
Application filed by Applied Materials, Inc. filed Critical Applied Materials, Inc.
Publication of WO2008103454A2 publication Critical patent/WO2008103454A2/fr
Publication of WO2008103454A3 publication Critical patent/WO2008103454A3/fr

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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F4/00—Processes for removing metallic material from surfaces, not provided for in group C23F1/00 or C23F3/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers

Definitions

  • the invention is in the fields of Semiconductor Structures and
  • a lithography/etch process In order to pattern semiconductor stacks into meaningful structures, a lithography/etch process is typically employed.
  • State-of-the-art etch processes include etching a semiconductor stack with a system comprising an ionized gas, i.e. a plasma.
  • Plasma etch processing may be particularly useful for etching multiple adjacent structures with fine features.
  • limitations of the plasma etch process have revealed themselves.
  • One potential limitation of plasma etching may be with respect to the fabrication of an IC with variable spacing between various semiconductor structures within a single sample.
  • the etch rate may exhibit a dependence on pattern density, a phenomenon referred to as "micro-loading."
  • micro-loading a phenomenon referred to as "micro-loading."
  • the etch rate of a material that has been patterned with a high density i.e. smaller spacings between features
  • the etch rate of the same material patterned with a low density i.e. larger spacings between features.
  • an "over-etch” may be required to fully etch all of the various structures within a single sample, i.e. the areas that are first to completely etch continue to be exposed to the etch process while areas that have not completely etched undergo completion of the etch process. In some cases, this over-etch may have a detrimental impact on the resultant semiconductor structures.
  • a plot is provided correlating the etch rate of a particular semiconductor material with the density (i.e. spacings between features) of various semiconductor structures in a single sample in which micro-loading occurs. As indicated by the decreasing slope of the correlation line, the etch rate decreases with increasing density.
  • a semiconductor stack 200 comprises a substrate 202, a semiconductor layer 204 and a mask 206.
  • the pattern of mask 206 is etched into semiconductor layer 204 with a plasma etch process.
  • Micro-loading can occur during the etch process of semiconductor stack 200, such that semiconductor layer 204 etches faster in low density region 208 than in medium density region 210 and high density region 212, as depicted in Figure 2B.
  • the etch process performed on semiconductor stack 200 is completed in low density region 208 prior to completion in medium density region 210 and in high density region 212.
  • the structures in low density region 208 are exposed to an over-etch while the etch is completed in regions of higher density.
  • some detrimental undercutting 214 may occur on structures in regions of lower density. The undercutting may vary with the density, depending on the extent of over- etch that a particular region experiences, as depicted in Figure 2D. [0006]
  • a method for etching semiconductor structures is described herein, along with a system within which the method may be conducted.
  • Figure 1 illustrates a correlation plot of Etch Rate versus Density of
  • Figures 2A-D illustrate cross-sectional views representing the effects of micro-loading during an etch process conducted on a semiconductor stack, in accordance with the prior art.
  • Figure 3 illustrates a correlation plot of Etch Rate versus Density of
  • Figures 4A-C illustrate cross-sectional views representing the effects of a significant reduction in micro-loading during a pulsed etch process conducted on a semiconductor stack, in accordance with an embodiment of the present invention.
  • Figure 5 A is a flowchart and Figure 5B is a waveform, both representing a series of steps in a pulsed plasma process, in accordance with an embodiment of the present invention.
  • Figures 6A-F illustrate cross-sectional views representing the steps of the flowchart from Figure 5 A performed on a semiconductor stack, in accordance with an embodiment of the present invention.
  • Figures 7A-C illustrate cross-sectional views representing a continuous/pulsed plasma etch process performed on a semiconductor stack, in accordance with an embodiment of the present invention.
  • Figure 8 is a flowchart representing a series of steps in a pulsed plasma process, in accordance with an embodiment of the present invention.
  • Figures 9A-D illustrate cross-sectional views representing the steps of the flowchart from Figure 8 performed on a more complex semiconductor stack, in accordance with an embodiment of the present invention.
  • Figure 10 illustrates a system in which a pulsed plasma process is conducted, in accordance with an embodiment of the present invention.
  • Figures 1 IA-B illustrate the chamber from the system of Figure 10 in a plasma ON state and a plasma OFF state, respectively, in accordance with an embodiment of the present invention.
  • Figures 12A-B illustrate the chamber from the system of Figure 10 in a plasma ON/bias OFF state and a plasma ON/bias ON state, respectively, in accordance with an embodiment of the present invention.
  • a portion of a sample may be removed by applying a pulsed plasma process, wherein the pulsed plasma process comprises a plurality of duty cycles.
  • the ON state of a duty cycle is of a duration sufficiently short to substantially inhibit micro-loading in a reaction region adjacent to the sample, while the OFF state of the duty cycle is of a duration sufficiently long to substantially enable removal of a set of etch by-products from the reaction region.
  • a first portion of a sample is removed by applying a continuous plasma process. The continuous plasma process is then terminated and a second portion of the sample is removed by applying a pulsed plasma process.
  • etch rate dependency on structure density may be mitigated.
  • an ON state of a plasma i.e. when the plasma is in the form of an ionized gas
  • etch by-products are formed.
  • these by-products may migrate away from the sample at a rate slower than in lower density regions of the sample.
  • etch by-products may hinder the etch process lending to micro-loading.
  • these by-products may be removed from all regions without competing with the etch process.
  • FIG. 3 illustrates a correlation plot of Etch Rate versus Density of Structures in a pulsed plasma etch process, in accordance with an embodiment of the present invention. As indicated by the negligible slope of the correlation line, the etch rate is substantially the same with increasing density. A semiconductor material etched in this manner may suffer less detriment from over-etch because the etch process may be completed in all portions of the sample at substantially the same time. [0022] A semiconductor stack may be etched by a pulsed plasma etch process.
  • FIGS 4A-C illustrate cross-sectional views representing the effects of a significant reduction in micro-loading during a pulsed etch process conducted on a semiconductor stack, in accordance with an embodiment of the present invention.
  • a semiconductor stack 400 comprises a substrate
  • Substrate 402 may comprise any material that can withstand a manufacturing process and upon which semiconductor layers may suitably reside, hi an embodiment, substrate 402 is comprised of group IV-based materials such as crystalline silicon, germanium or silicon/germanium, hi one embodiment, the atomic concentration of silicon atoms in substrate 402 is greater than 99%.
  • substrate 402 is comprised of a ⁇ i-V material such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide or a combination thereof.
  • substrate 402 is comprised of an epitaxial layer grown atop a distinct crystalline substrate, e.g. a silicon epitaxial layer grown atop a boron-doped bulk silicon mono-crystalline substrate.
  • Substrate 402 may also comprise an insulating layer in between a bulk crystal substrate and an epitaxial layer to form, for example, a silicon-on-insulator substrate.
  • the insulating layer is comprised of a material selected from the group consisting of silicon dioxide, silicon nitride, silicon oxy-nitride and a high-k dielectric layer.
  • substrate 402 comprises a top insulating layer, directly adjacent to etch layer 404.
  • Substrate 402 may additionally comprise charge-carrier dopant impurity atoms.
  • substrate 402 is comprised of silicon and/or germanium and the charge-carrier dopant impurity atoms are selected from the group consisting of boron, arsenic, indium, antimony or phosphorus.
  • substrate 402 is comprised of a HI- V material and the charge-carrier dopant impurity atoms are selected from the group consisting of carbon, silicon, germanium, oxygen, sulfur, selenium or tellurium.
  • Etch layer 404 may comprise any material that can be suitably patterned into an array of distinctly defined semiconductor structures.
  • etch layer 404 is comprised of a group IV-based material or a III-V material, such as those discussed above in association with substrate 402. Additionally, etch layer 404 may comprise any morphology that can suitably be patterned into an array of distinctly defined semiconductor structures, hi an embodiment, the morphology of etch layer 404 is selected from the group consisting of amorphous, single-crystalline and poly-crystalline, hi one embodiment, etch layer 404 comprises charge-carrier dopant impurity atoms, such as those described above in association with substrate 402.
  • etch layer 404 need not be limited to semiconductor materials, per se.
  • etch layer 404 is comprised of a metal layer such as but not limited to copper, aluminum, tungsten, metal nitrides, metal carbides, metal suicides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel or conductive metal oxides, e.g. ruthenium oxide.
  • etch layer 404 is comprised of an insulating layer.
  • etch layer 404 is comprised of an insulating material selected from the group consisting of silicon dioxide, silicon oxy-nitride and silicon nitride.
  • etch layer 404 is comprised of a high-K dielectric layer selected from the group consisting of hafnium oxide, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide and lead zinc niobate.
  • Mask 406 may be comprised of any material suitable for patterning via a lithography or direct- write process, hi one embodiment, mask 406 is comprised of a photo-resist material. In a specific embodiment, the photo-resist material is used in a lithographic process and is selected from the group consisting of a positive photo-resist and a negative photo-resist. Mask 406 may further comprise a material suitable for blocking a plasma etch process, such as a plasma etch process used to pattern etch layer 404.
  • mask 406 also comprises a hard-mask layer, such as a hard-mask layer selected from the group consisting of silicon dioxide, silicon oxy-nitride, silicon nitride and a metal film.
  • a hard-mask layer selected from the group consisting of silicon dioxide, silicon oxy-nitride, silicon nitride and a metal film.
  • the etch rate of all density regions 408, 410 and 412 are substantially similar when a pulsed plasma process is employed, as depicted in Figure 4B.
  • the pulsed plasma process contains a plurality of duty cycles, wherein each duty cycle represents the combination of an ON state and an OFF state of the etching plasma.
  • a duty cycle may be comprised of one ON state and one OFF state, wherein the durations of the ON state and OFF state are suitable to transfer the pattern of mask 406 into etch layer 404 at a substantially similar etch rate for density regions 408, 410 and 412.
  • the portion of each duty cycle comprised of said ON state is in the range of 5 - 95% of the duty cycle.
  • the portion of each duty cycle comprised of said ON state is in the range of 65 - 75% of the duty cycle
  • the frequency of a plurality of duty cycles is in the range of IHz - 200 kHz, i.e. each duty cycle has a duration in the range of 5 microseconds - 1 second.
  • the frequency of a plurality of duty cycles is 50 kHz and the portion of each duty cycle comprised of said ON state is 70%.
  • the method of generating a plasma for use in the pulsed plasma process for etching etch layer 404 may comprise any method suitable to strike and maintain the plasma for a duration sufficient to satisfy the duration of the ON state in a duty cycle.
  • the method of generating the plasma comprises generating a plasma selected from the group consisting of an electron cyclotron resonance (ECS) plasma, a helicon wave plasma, an inductively coupled plasma (ICP) and a surface wave plasma.
  • ECS electron cyclotron resonance
  • ICP inductively coupled plasma
  • the method of generating the plasma comprises generating an inductively coupled plasma in an Applied MaterialsTM AdvantEdge G3 etcher.
  • the plasma generated for the pulsed plasma etch process may be comprised of any reaction gas suitable to generate ions and reactive radicals to remove portions of etch layer 404 without detrimentally impacting the pattern of mask 406.
  • the reaction gas is comprised of a halide species and is used to etch a silicon-based material.
  • the reaction gas is comprised of the species HBr, He and a 70%/30% He/O 2 mixture in the approximate ratio of 300:50: 12, respectively, and the pulsed plasma is used to etch amorphous silicon, poly-silicon or single-crystal silicon.
  • the reaction gas is comprised of a fluorocarbon species and is used to etch a dielectric layer, hi a specific embodiment, the reaction gas is comprised of the species CF 4 and the pulsed plasma is used to etch silicon dioxide or carbon-doped silicon oxide.
  • the reaction gas may have a pressure suitable to provide a controlled etch rate, hi an embodiment, the pressure is in the range of 1 - 100 mTorr. hi another embodiment, the pressure is in the range of 3 - 100 mTorr.
  • the reaction gas is comprised of HBr, He and O 2
  • the pressure of the reaction gas is in the range of 30 - 50 mTorr
  • the etch rate of poly-silicon is in the range of 500 - 6000 Angstroms/minute.
  • FIG. 5A is a flowchart and Figure 5B is a waveform, both representing a series of such targeted steps in a pulsed plasma process, in accordance with an embodiment of the present invention.
  • Figures 6A-D illustrate cross-sectional views representing the steps of the flowchart from Figure 5 A as performed on a semiconductor stack.
  • a semiconductor stack 600 comprises a substrate 602, an etch layer 604 and a mask 606 at the start of a pulsed plasma etching process.
  • Mask 606 is patterned with a low density region 608, a medium density region 610 and a high density region 612.
  • Substrate 602, etch layer 604 and mask 606 may be comprised of any materials described in association with substrate 402, etch layer 404 and mask 406, respectively, from Figure 4A.
  • Semiconductor stack 600 may comprise a stack of greater complexity of material layers and/or pattern types, but is depicted in the manner shown herein for illustrative purposes.
  • the pattern of mask 606 is partially etched into etch layer 604 during the ON state of a duty cycle in a pulsed plasma etch process to form partially patterned etch layer 614A.
  • Unmasked portions of etch layer 604 are accessible by plasma etching species 620 while masked portions of etch layer 604, covered by mask 606, are protected from plasma etching species 620, as depicted in Figure 6B.
  • Etch by-products 616 are generated within reaction region 618 of semiconductor stack 600.
  • Etching species 620 may be comprised of any charged species and reactive neutrals ejected from the plasma used in a pulsed plasma etch process.
  • etching species 620 are comprised of positively charged ions and radicals.
  • the reaction gas is comprised of HBr, He and O 2 and the etching species 620 are selected from the group consisting of H + , Br + , He + , O + , H, Br and O.
  • the reaction gas is comprised of a fluorocarbon and the etching species 620 are selected from the group consisting of F + , CF + , CF 2 + , CF 3 + , F, CF, CF 2 and CF 3 .
  • Etch by-products 616 may be comprised of any combination of atoms from etch layer 604 and etching species 620.
  • the duration of the ON state of a duty cycle may be selected to maximize etch efficiency while maintaining a substantially similar etch rate for all density regions 608, 610 and 612 of partially patterned etch layer 614A.
  • etch by-products 616 are formed and reside, at least for a time, among the partially etched features of partially patterned etch layer 614A, i.e. within reaction region 618.
  • Reaction region 618 is a region adjacent semiconductor stack 600 within which etch by-products 616 that are formed may interfere with plasma etching species 620.
  • plasma etching species 620 may be hindered from accessing unmasked portions of partially patterned etch layer 604. Such hindering of plasma etching species 620 may be more severe in high structure density regions as compared to low structure density regions, slowing the etch rate in the high density regions as compared with the etch rate of the low density regions.
  • the ON state of a duty cycle in a pulsed plasma etch process is selected to be less than or, at most, correspond with the time at which a sufficient amount of etch by-products are generated to slow the etch rate of a high density region versus the etch rate of a low density region, hi one embodiment, the duration of the ON state is selected to substantially match the time at which the etch rate of the partially patterned etch layer 614A becomes dependent on the density of the pattern of mask 606. In another embodiment, the ON state is of a sufficiently short duration to substantially inhibit micro-loading within reaction region 618. In an embodiment, the duration of the ON state is within any of the ranges described for the ON state of the duty cycle discussed in association with Figure 4B.
  • step 506 of flowchart 500 and corresponding Figure 6C the plasma is in an OFF state and, thus, etching species 620 are no longer present in reaction region 618 of semiconductor stack 600. As depicted in Figure 6C, etch by-products 616 are removed from reaction region 618.
  • the duration of the OFF state of a duty cycle may be selected to allow a sufficient time for etch by-products 616 to be removed from (i.e. dissipated from or evacuated from) reaction region 618.
  • etch by-products 616 are formed within reaction region 618, as described above.
  • negatively charged ions may be ejected from the plasma gas as it neutralizes, generating a new set of etching species. These new etching species may further contribute to the quantity of etch by-products present in reaction region 618.
  • the concentration of byproducts 618 may be substantially greater inside reaction region 618 than outside of reaction region 618.
  • a natural diffusion gradient may form and etch by-products 616 may diffuse outside of reaction region 618.
  • This process may be enhanced by an additional pressure gradient. That is, along with a build-up in etch by-products 616 during the ON state, the pressure within reaction region 618 may become greater than the pressure outside of reaction region 618, enhancing the extrusion of etch by-products 616.
  • the OFF state of a duty cycle in a pulsed plasma etch process is selected to be of a sufficiently long duration to substantially enable removal of a set of etch by-products 616 from reaction region 618.
  • the quantity of etch by-products 616 removed is sufficient such that any etch by-products that remain with reaction region 618 do not substantially interfere with etching species during an ON state of a subsequent duty cycle.
  • the duration of the OFF state is selected to substantially match the time at which more than 50% of the etch by-products 616 have been removed from reaction region 618.
  • the duration of the OFF state is selected to substantially match the time at which more than 75% of the etch by-products 616 have been removed from reaction region 618. In an alternative embodiment, the duration of the OFF state is within any of the ranges described for the OFF state of the duty cycle discussed in association with Figure 4B. In an embodiment, an inert gas such as Ar or He is injected during the OFF state to enhance the by-product removal. [0041] Referring to step 508 of flowchart 500 and corresponding Figures 6D-E, the pattern of mask 606 is continued to be etched into etch layer 604 during subsequent duty cycles of a pulsed plasma etch process, forming more extensively etched partially patterned etch layer 614B. The duty cycles (i.e.
  • step 508 may be repeated until a desired amount of etch layer 604 has been etched.
  • a portion of etch layer 604 is removed with a pulsed plasma etch process comprising a plurality of duty cycles.
  • Figure 5B illustrates the timeline of a duty cycle, as represented in a waveform.
  • the pulsed plasma etch process is terminated following removal of a desired quantity of etch layer 604.
  • the etch process is completed at density regions 608, 610 and 612 at substantially the same time.
  • only a negligible amount of over-etching may be required in order to form patterned etch layer 624.
  • detrimental undercutting of the various structures of patterned etch layer 624 may be significantly mitigated, as depicted by the lack of undercut in Figure 6F.
  • the determination of when to terminate the pulsed plasma process may be made by any suitable factor.
  • the termination of the pulsed plasma etch process is determined by ending the repetition of duty cycles at a predetermined time.
  • the termination of the pulsed plasma etch process is determined by detecting a change in etch by-products 612 at the completion of the etching of etch layer 604 and the corresponding exposure of the top surface of substrate 602.
  • the termination of the pulsed plasma etch process is determined by measuring the depth of a trench using an interferometric technique.
  • a pulsed plasma etch process may be combined with a continuous plasma etch process.
  • a differential in etch rate for differing density regions of a semiconductor stack may not be significant until a portion of the semiconductor stack has already been etched, since the etch process may suffer from more severe micro-loading with increased aspect ratio of a pattern.
  • it may be more efficient to apply a continuous plasma for etching the first portion of a semiconductor stack, until a particular depth has been reached, and then to apply a pulsed plasma etch process to remove a second portion of the semiconductor stack hi accordance with an embodiment of the present invention, a semiconductor stack is etched with a continuous plasma etch process until a desired depth has been reached.
  • a continuous/pulsed plasma etch process is utilized to increase the throughput of wafers in a single- wafer processing tool.
  • This continuous/pulsed plasma etch process is illustrated in Figures 7A-C, in accordance with an embodiment of the present invention.
  • Etch layer 704 patterned with mask 712 ( Figure 7A) is partially patterned with a continuous plasma etch process ( Figure 7B).
  • a pulsed plasma etch process is subsequently employed to complete etching etch layer 704, i.e. until the etch stops on etch-stop layer 706, as depicted in Figure 7C.
  • the depth at which the plasma etch process is changed from continuous to pulsed is selected as being in the range of 0.5 - 4 times the spacing width of the region of highest structure density. In one embodiment, the depth at which the plasma etch process is changed from continuous to pulsed is selected as being substantially equal to the spacing width of the region of highest structure density, i.e. when an aspect ratio of 1 has been achieved among the highest density structures.
  • Figure 8 is a flowchart representing a series of steps combining a continuous plasma etch process with a subsequent pulsed plasma etch process, in accordance with an embodiment of the present invention.
  • Figures 9A-D illustrate cross- sectional views representing the steps of the flowchart from Figure 8 as performed on a more complex semiconductor stack.
  • a semiconductor stack 900 comprises a substrate 902, two etch layers 904 and 908, two dielectric layers 906 and 810 and a mask 912 at the start of a continuous/pulsed plasma etching process.
  • Substrate 902, etch layers 904 and 908 and mask 912 may be comprised of any materials described in association with substrate 402, etch layer 404 and mask 406, respectively, from Figure 4A.
  • Semiconductor stack 900 may comprise a stack of greater or lesser complexity of material layers, but is depicted in the manner shown herein for illustrative purposes.
  • semiconductor stack 900 is comprised of poly- silicon/SiON/poly-silicon/SiO 2 , as is found in a typical Flash memory stack.
  • Dielectric layers 906 and 910 may be comprised of any material suitable to insulate conductive portions of a semiconductor stack. In one embodiment, dielectric layers 906 and 910 are comprised of an insulating material selected from the group consisting of silicon dioxide, silicon oxy-nitride and silicon nitride.
  • dielectric layers 906 and 910 are comprised of a high-K dielectric layer selected from the group consisting of hafnium oxide, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide and lead zinc niobate.
  • a high-K dielectric layer selected from the group consisting of hafnium oxide, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide and lead zinc niobate.
  • the pattern of mask 912 is etched into etch layer 904 with a continuous plasma etch process to form patterned etch layer 914.
  • a continuous plasma etch process may be sufficient for the etching of etch layer 904 in the case that a differential in etch rate for differing density regions of a first portion of semiconductor stack 900 is not significant.
  • the method of generating a plasma for use in the continuous plasma process to form patterned etch layer 914 may comprise any method suitable to strike and maintain the plasma for a duration sufficient to satisfy the duration of the continuous etch process.
  • the method of generating the continuous plasma comprises generating a plasma selected from the group consisting of an electron cyclotron resonance (ECS) plasma, a helicon wave plasma, an inductive coupled plasma (ICP) and a surface wave plasma, hi a specific embodiment, the method of generating the continuous plasma comprises generating an inductive coupled plasma in an Applied MaterialsTM AdvantEdge G3 etcher.
  • the determination of when to terminate the continuous plasma process may be made by any suitable factor.
  • the termination of the continuous plasma etch process is determined by ending at a predetermined time based on characteristics of the material being etched, hi an alternative embodiment, the termination of the continuous plasma etch process is determined by detecting a change in etch by-products at the completion of the etching of etch layer 904 and the corresponding exposure of the top surface of dielectric layer 906, i.e. by detecting an end-point.
  • the termination of the continuous plasma etch process is determined by the real-time composition of a set of chemical species generated during the continuous etch process.
  • the exposed portions of dielectric layer 906 may be removed to form patterned dielectric layer 916 following the patterning of etch layer 904.
  • exposed portions of dielectric layer 906 are removed by an etch process selected from the group consisting of a wet etch process, a continuous plasma etch process and a pulsed plasma etch process.
  • the pattern of mask 912 is continued to be etched into semiconductor stack 900.
  • a differential in etch rate for differing density regions of etch layer 908 may be significant, requiring the application of a pulsed plasma etch process.
  • a pulsed plasma etch process is utilized to pattern semiconductor layer 908 to form patterned semiconductor layer 918.
  • the duty cycles i.e. step 812 may be repeated until a desired amount of etch layer 908 has been etched.
  • a first portion of semiconductor stack 900 is patterned with a continuous etch plasma process and a second portion of semiconductor stack 900 is patterned with a pulsed plasma etch process comprising a plurality of duty cycles.
  • the pulsed plasma etch process is terminated following removal of a desired quantity of etch layer 908.
  • the etch process is completed at various density regions at substantially the same time.
  • only a negligible amount of over-etching may be required in order to form patterned etch layer 918.
  • detrimental undercutting of the various structures of patterned etch layer 918 may be significantly mitigated, as depicted by the lack of undercut in Figure 9D.
  • the determination of when to terminate the pulsed plasma process may be made by any suitable factor.
  • the termination of the pulsed plasma etch process is determined by ending the repetition of duty cycles at a predetermined time.
  • the termination of the pulsed plasma etch process is determined by detecting a change in etch by-products at the completion of the etching of etch layer 908 and the corresponding exposure of the top surface of dielectric layer 910.
  • a first portion of a semiconductor stack is patterned with a first continuous plasma etch process
  • a second portion of the semiconductor stack is patterned with a first pulsed plasma etch process
  • a third portion of the semiconductor stack is patterned with a second continuous etch process
  • a fourth portion of the semiconductor stack is patterned with a second pulsed plasma etch process
  • etch layer 904 of semiconductor stack 900 is also patterned with a first continuous plasma etch process followed by a first pulsed plasma etch process.
  • Etch layer 908 is then patterned with a second continuous plasma etch process followed by a second pulsed plasma etch process.
  • a pulsed plasma etch process may be conducted in any processing equipment suitable to provide an etch plasma in proximity to a sample for etching.
  • Figure 10 illustrates a system in which a pulsed plasma etch process is conducted, in accordance with an embodiment of the present invention.
  • a system 1000 for conducting a pulsed plasma etch process comprises a chamber 1002 equipped with a sample holder 1004.
  • An evacuation device 1006, a gas inlet device 1008 and a plasma ignition device 1010 are coupled with chamber 1002.
  • a computing device 1012 is coupled with plasma ignition device 1010.
  • System 1000 may additionally include a voltage source 1014 coupled with sample holder 1004 and a detector 1016 coupled with chamber 1002.
  • Computing device 1012 may also be coupled with evacuation device 1006, gas inlet device 1008, voltage source 1014 and detector 1016, as depicted in Figure 10.
  • Chamber 1002 and sample holder 1004 may be comprised of any reaction chamber and sample positioning device suitable to contain an ionized gas, i.e. a plasma, and bring a sample in proximity to the ionized gas or charged species ejected therefrom.
  • Evacuation device 1006 may be any device suitable to evacuate and de-pressurize chamber 1002.
  • Gas inlet device 1008 may be any device suitable to inject a reaction gas into chamber 1002.
  • Plasma ignition device 1010 maybe any device suitable for igniting a plasma derived from the reaction gas injected into chamber 1002 by gas inlet device 1008.
  • Detection device 1016 may be any device suitable to detect an end-point of a processing step, hi one embodiment, system 1000 comprises a chamber 1002, a sample holder 1004, an evacuation device 1006, a gas inlet device 1008, a plasma ignition device 1010 and a detector 1016 similar to, or the same as, those included in an Applied MaterialsTM AdvantEdge G3 etcher.
  • Computing device 1012 comprises a processor and a memory.
  • the memory of computing device 1012 includes a set of instructions for controlling plasma ignition device 1010 to switch between an ON state and an OFF state of a plasma in a pulsed plasma etch process, hi an embodiment, the set of instructions contains machine operable code capable of effecting a plurality of duty cycles, wherein each duty cycle represents the combination of one ON state and one OFF state of the plasma.
  • the set of instructions for controlling plasma ignition device 1010 includes timing instructions for each duty cycle to have an ON state in the range of 5 - 95% of the duration of the duty cycle.
  • the set of instructions for controlling plasma ignition device 1010 includes timing instructions for each duty cycle to have an ON state in the range of 65 - 75% of the duration of the duty cycle.
  • the set of instructions for controlling plasma ignition device 1010 includes timing instructions such that the frequency of a plurality of duty cycles is in the range of IHz - 200 kHz, i.e. each duty cycle has a duration in the range of 5 micro- seconds - 1 second, hi a specific embodiment, the set of instructions for controlling plasma ignition device 1010 includes timing instructions such that the frequency of a plurality of duty cycles is 50 kHz and the portion of each duty cycle comprised of said ON state is 70%.
  • Figures 1 IA-B illustrate the chamber from the system of Figure 10 in a plasma ON state and a plasma OFF state, respectively, in accordance with an embodiment of the present invention.
  • chamber 1002 of system 1000 comprises a plasma 1100 in an ON state and in proximity to a sample 1102 on sample holder 1004.
  • a reaction region 1104 is directly adjacent to sample 1102.
  • etch by-products may be formed and reside, at least for a time, within reaction region 1102.
  • the set of instructions for controlling plasma ignition device 1010 includes timing instructions such that the ON state is of a sufficiently short duration to substantially inhibit micro-loading within reaction region 1104.
  • chamber 1002 of system 1000 comprises a plasma in an OFF state (i.e. a neutral reaction gas).
  • the set of instructions for controlling plasma ignition device 1010 includes timing instructions such that the OFF state of a duty cycle in a pulsed plasma etch process is selected to be of a sufficiently long duration to substantially enable removal of a set of etch by-products from reaction region 1104.
  • positive charge may be imparted to the sample being etched.
  • the positive charge of the sample maybe substantial enough to partially deflect the positively charged etch species ejected from a plasma. Such deflection of the etching species may result in detrimental undercut of features being etched into a particular sample.
  • the deflection of positively charged particles may be mitigated.
  • FIGs 12A-B illustrate chamber 1002 from system 1000 of Figure 10 in a plasma ON/bias OFF state and a plasma ON/bias ON state, respectively, in accordance with an embodiment of the present invention.
  • a voltage source 1014 is coupled with sample holder 1004 and may be used to bias sample holder 1004, and hence sample 1102, during an etch process.
  • voltage source 1014 is in an OFF state and positively charged etch species ejected from plasma 1100 are partially deflected near the surface of sample 1102.
  • voltage source 1014 is in an ON state (i.e.
  • voltage source 1014 is used to apply a negative bias to sample holder 1004 in the range of 100 - 200 Watts.
  • a pulsed plasma etch process (as compared with a continuous plasma etch process) may reduce the extent of positive charge build-up on sample 1102 during an etch process.
  • the additional step of biasing sample holder 1004 with voltage source 1014 may still be utilized as part of the pulsed plasma etch process in order to optimize the mitigation of undercutting of structures during the etch process. Therefore, in accordance with another embodiment of the present invention, the additional step of biasing sample holder 1004 with voltage source 1014 is used to extend the duration of the ON state of a duty cycle in a pulsed plasma etch process.
  • a pulsed plasma system for etching semiconductor structures has been disclosed.
  • a portion of a sample is removed by applying a pulsed plasma etch process, wherein the pulsed plasma etch process comprises a plurality of duty cycles.
  • the ON state of a duty cycle is of a duration sufficiently short to substantially inhibit micro-loading in a reaction region adjacent to the sample, while the OFF state of the duty cycle is of a duration sufficiently long to substantially enable removal of a set of etch by-products from the reaction region.
  • a first portion of a sample is removed by applying a continuous plasma etch process. The continuous plasma etch process is then terminated and a second portion of the sample is removed by applying a pulsed plasma etch process.

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Abstract

Cette invention concerne un système à plasma pulsé pour la gravure de structures à semi-conducteurs. Dans un mode de réalisation, une partie d'un échantillon est éliminée par application d'un traitement au plasma pulsé, ce traitement comprend plusieurs cycles de travail. La durée de l'état ACTIVÉ d'un cycle de travail est suffisamment courte pour empêcher essentiellement la micro-charge dans une zone de réaction contiguë à l'échantillon, alors que la durée de l'état DÉSACTIVÉ est suffisamment longue pour permettre sensiblement l'élimination d'un ensemble de sous-produits de gravure de la zone de réaction. Dans un autre mode de réaction, une première partie d'un échantillon est éliminée par application d'un traitement au plasma en continu. Ce traitement au plasma en continu est ensuite achevé et une seconde partie de l'échantillon est éliminée par application d'un traitement au plasma pulsé.
PCT/US2008/002368 2007-02-21 2008-02-21 Système à plasma pulsé pour gravure des structures à semi-conducteurs WO2008103454A2 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/677,472 2007-02-21
US11/677,472 US7718538B2 (en) 2007-02-21 2007-02-21 Pulsed-plasma system with pulsed sample bias for etching semiconductor substrates
US11/678,041 2007-02-22
US11/678,041 US7737042B2 (en) 2007-02-22 2007-02-22 Pulsed-plasma system for etching semiconductor structures

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EP3087586A4 (fr) * 2013-12-23 2017-08-30 Intel Corporation Techniques avancées de gravure pour des ailettes rectilignes, grandes et uniformes sur des structures à pas à ailettes multiples

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US5877407A (en) * 1997-07-22 1999-03-02 Lucent Technologies Inc. Plasma etch end point detection process
US20020052111A1 (en) * 1999-07-23 2002-05-02 Alex Paterson Method for providing pulsed plasma during a portion of a semiconductor wafer process
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US5877407A (en) * 1997-07-22 1999-03-02 Lucent Technologies Inc. Plasma etch end point detection process
US20020052111A1 (en) * 1999-07-23 2002-05-02 Alex Paterson Method for providing pulsed plasma during a portion of a semiconductor wafer process
US20060270239A1 (en) * 2005-05-27 2006-11-30 Triyoso Dina H Reverse ALD

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3087586A4 (fr) * 2013-12-23 2017-08-30 Intel Corporation Techniques avancées de gravure pour des ailettes rectilignes, grandes et uniformes sur des structures à pas à ailettes multiples
US10204794B2 (en) 2013-12-23 2019-02-12 Intel Corporation Advanced etching technologies for straight, tall and uniform fins across multiple fin pitch structures
US10643855B2 (en) 2013-12-23 2020-05-05 Intel Corporation Advanced etching technologies for straight, tall and uniform fins across multiple fin pitch structures
US10950453B2 (en) 2013-12-23 2021-03-16 Intel Corporation Advanced etching technologies for straight, tall and uniform fins across multiple fin pitch structures
EP3901992A1 (fr) * 2013-12-23 2021-10-27 INTEL Corporation Techniques avancées de gravure d'ailettes rectilignes, hautes et uniformes sur des structures à ailettes multiples à espacement variable
US11417531B2 (en) 2013-12-23 2022-08-16 Intel Corporation Advanced etching technologies for straight, tall and uniform fins across multiple fin pitch structures
US11875999B2 (en) 2013-12-23 2024-01-16 Intel Corporation Advanced etching technologies for straight, tall and uniform fins across multiple fin pitch structures
US12131912B2 (en) 2013-12-23 2024-10-29 Intel Corporation Advanced etching technologies for straight, tall and uniform fins across multiple fin pitch structures

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