WO2008086456A3 - System and method for preemptive masking and unmasking of non-secure processor interrupts - Google Patents

System and method for preemptive masking and unmasking of non-secure processor interrupts Download PDF

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Publication number
WO2008086456A3
WO2008086456A3 PCT/US2008/050689 US2008050689W WO2008086456A3 WO 2008086456 A3 WO2008086456 A3 WO 2008086456A3 US 2008050689 W US2008050689 W US 2008050689W WO 2008086456 A3 WO2008086456 A3 WO 2008086456A3
Authority
WO
WIPO (PCT)
Prior art keywords
processor
secure
unmasking
operating
interrupt signal
Prior art date
Application number
PCT/US2008/050689
Other languages
French (fr)
Other versions
WO2008086456A2 (en
Inventor
Gregory R Conti
Steven C Goss
Original Assignee
Texas Instruments Inc
Gregory R Conti
Steven C Goss
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/971,253 external-priority patent/US20090177826A1/en
Application filed by Texas Instruments Inc, Gregory R Conti, Steven C Goss filed Critical Texas Instruments Inc
Publication of WO2008086456A2 publication Critical patent/WO2008086456A2/en
Publication of WO2008086456A3 publication Critical patent/WO2008086456A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/74—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information operating in dual or compartmented mode, i.e. at least one secure mode

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Security & Cryptography (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Game Rules And Presentations Of Slot Machines (AREA)
  • Storage Device Security (AREA)

Abstract

The disclosure describes systems and methods for preemptive masking and unmasking of non-secure processor interrupts. At least some embodiments provide a system that includes a processor (170) capable of operating in a non-secure mode, and preemption logic (350) coupled to the processor (the preemption logic capable of asserting an interrupt signal (281) to the processor). If the processor is operating in the non-secure mode, the preemption logic preemptively inhibits a non-secure assertion of the interrupt signal (281) in response to a mask event. If the processor is operating in the non-secure mode, the preemption logic (35) preemptively enables the non-secure assertion of the interrupt signal in response to an unmask event.
PCT/US2008/050689 2007-01-03 2008-01-10 System and method for preemptive masking and unmasking of non-secure processor interrupts WO2008086456A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
EP7290005.3 2007-01-03
EP07290005 2007-01-03
US11/971,253 US20090177826A1 (en) 2008-01-09 2008-01-09 System and method for preemptive masking and unmasking of non-secure processor interrupts
US11/971,253 2008-01-09

Publications (2)

Publication Number Publication Date
WO2008086456A2 WO2008086456A2 (en) 2008-07-17
WO2008086456A3 true WO2008086456A3 (en) 2008-09-25

Family

ID=39609368

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2008/050689 WO2008086456A2 (en) 2007-01-03 2008-01-10 System and method for preemptive masking and unmasking of non-secure processor interrupts

Country Status (1)

Country Link
WO (1) WO2008086456A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8214574B2 (en) * 2006-09-08 2012-07-03 Intel Corporation Event handling for architectural events at high privilege levels
US9886595B2 (en) 2012-12-07 2018-02-06 Samsung Electronics Co., Ltd. Priority-based application execution method and apparatus of data processing device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050138257A1 (en) * 2003-12-23 2005-06-23 Arm Limited Interrupt masking control
US6948098B2 (en) * 2001-03-30 2005-09-20 Cirrus Logic, Inc. Circuits and methods for debugging an embedded processor and systems using the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6948098B2 (en) * 2001-03-30 2005-09-20 Cirrus Logic, Inc. Circuits and methods for debugging an embedded processor and systems using the same
US20050138257A1 (en) * 2003-12-23 2005-06-23 Arm Limited Interrupt masking control

Also Published As

Publication number Publication date
WO2008086456A2 (en) 2008-07-17

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