WO2008085523A1 - Semiconductor device having improved interface adhesion of gate stack films and method of manufacturer therefore - Google Patents

Semiconductor device having improved interface adhesion of gate stack films and method of manufacturer therefore Download PDF

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Publication number
WO2008085523A1
WO2008085523A1 PCT/US2007/060434 US2007060434W WO2008085523A1 WO 2008085523 A1 WO2008085523 A1 WO 2008085523A1 US 2007060434 W US2007060434 W US 2007060434W WO 2008085523 A1 WO2008085523 A1 WO 2008085523A1
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layer
metal
forming
method recited
polysilicon
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PCT/US2007/060434
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French (fr)
Inventor
Sailesh M. Merchant
Nace M. Rossi
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Agere Systems, Inc.
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Priority to PCT/US2007/060434 priority Critical patent/WO2008085523A1/en
Publication of WO2008085523A1 publication Critical patent/WO2008085523A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers
    • H01L21/32053—Deposition of metallic or metal-silicide layers of metal-silicide layers

Definitions

  • the invention is directed, in general, to a method of manufacturing a semiconductor device and, more specifically, to a method of manufacturing a semiconductor device having an improved interface adhesion between the gate stack films.
  • Doped polycrystalline silicon (“poly-Si”) is often used as a gate electrode in metal oxide semiconductor (“MOS”) -based circuits. Due to the shrinking size of electrical components in general, MOS devices have also become smaller, and as their size has decreased, the resistivity of the poly-Si, unfortunately, has also increased, which, in turn, has affected the device RC- delay (“RC”) . This is disadvantageous to the device because RC delays caused by high sheet resistance between 20-100 ohms/square of poly-Si runners, limit the performance of the integrated circuits with n+ doped poly- Si, and their performance also deteriorates as the length of these runners increases.
  • poly-Si/silicide a polycide stack
  • the poly-Si is clad with a low-resistivity suicide such that the sheet resistance of the polycide is between 5-10 ohms/sq from 20-100 ohms/sq without the silicide.
  • the manufacturing processes typically used to form the polysilicon/silicide gate stacks often lead to a device where the silicide layer peels away from the polysilicon layer. This peeling can lead to shorts and significant yield loss. Accordingly, there is a need to provide a process and device that does not suffer from the disadvantages associated with present manufacturing processes.
  • FIG. 1 illustrates a semiconductor device as provided by one embodiment of the invention
  • FIGS. 2-3 illustrate views of one embodiment of a semiconductor device during various stages of fabrication wherein the polysilicon layer and suicide layer are formed;
  • FIGS. 4A-4C illustrate an embodiment where a crystalline silicon layer is formed at an interface between the suicide layer and the polysilicon layer prior to patterning the polysilicon and suicide layers;
  • FIGS. 5A-5C illustrate an alternative embodiment where a crystalline silicon layer is formed at an interface between the suicide layer and the polysilicon layer prior to the formation of spacers; and FIG. 6 illustrates the semiconductor device configured as an integrated circuit.
  • FIG. 1 illustrates a general, partial view of one embodiment of a semiconductor device 100.
  • the semiconductor device 100 includes a substrate 110, such as a semiconductor wafer.
  • the substrate materials include silicon, silicon-germanium, gallium arsenide, or indium-containing substrates.
  • the substrate 110 may be the wafer itself or any material layer deposited on the wafer, such as an epitaxial layer.
  • the semiconductor device 100 also includes isolation regions 120 that isolate wells 125 and 130. Conventional processes may be used to form the isolation regions 120 and the well 125, 130.
  • the wells 125, 130 are appropriately doped for an NMOS or PMOS device, and they may be arranged to form a complementary device, such as a CMOS device.
  • the illustrated embodiment further includes transistors 135 that include gate electrodes 140 located over a gate oxide layer 145 and spacers 150 located adjacent the gate electrodes 140.
  • the transistors 135 also include the previously mentioned wells 125, 130 in which conventional source/drains 155 may be formed.
  • the gate electrodes 140 of the embodiment of FIG. 1 further include a polysilicon layer 140a and a suicide layer 140b.
  • a crystalline silicon layer 145 is located at an interface between the polysilicon layer 140a and the suicide layer 140b.
  • the way in which the crystalline silicon layer 145 is formed provides a semiconductor device 100 that has improved adhesion between the polysilicon layer 140a and the suicide layer 140b.
  • peeling of the silicide layer 140b form the polysilicon layer 140a that can occur in conventional devices is reduced, which in turn, increases product yield.
  • FIG. 2 illustrates a partial view of one embodiment of the semiconductor device 100 illustrated in FIG. 1 at an early stage of manufacture.
  • a polysilicon layer 210 has been deposited over the gate oxide layer 215.
  • the thickness of the layer may vary, but in one embodiment, the thickness may be about 100 nm.
  • Conventional process, such as chemical vapor deposition, and thermal oxidation process may be used to form the polysilicon layer 210 and the gate oxide layer 215, respectively.
  • the polysilicon layer 210 may be appropriately doped for proper conductivity using conventional processes.
  • FIG. 3 illustrates the semiconductor device 100 of FIG. 2, after the formation of a silicide layer 310 over the polysilicon layer 210.
  • the silicide layer 310 may also be deposited using conventional processes, such as chemical vapor deposition or physical vapor (sputter) deposition.
  • the silicide layer 310 may be deposited as an amorphous layer or as a crystalline layer. In those embodiments where it is deposited has an amorphous layer, a subsequent anneal will be conducted to transform the amorphous layer to a crystalline layer.
  • the silicide layer 310 is a metal silicide layer and may comprise metals, such as tungsten, molybdenum, nickel, cobalt, titanium/ or tantalum.
  • a target comprised of silicon and the selected metal may be used.
  • the target is silicon rich.
  • the metal suicide layer 310 may have stoichiometric ratio of silicon to metal that may range from about 2.0:1 to about 2.8:1, and in another embodiment, the ratio may range from, about 2.2:1 to about 2.5:1.
  • the metal suicide layer 310 can be formed by sputtering atoms from a conventional metal suicide target that comprises metals as those examples noted above .
  • the metal suicide target is subject to degradation; that is, since more silicon is removed than metal during the deposition process, the silicon on the target reaches a point where there is not a sufficient amount of silicon to maintain the required ratio of excess silicon to metal.
  • the metal suicide layer 310 may be deposited to a thickness of about 50-100 nm under a pressure to 2-7 milli-torr and a temperature of about 300-400. degree . C.
  • the ratio of silicon to metal can be monitored and determined, for example on control wafers by such known methods as Rutherford back scattering spectroscopy, x-ray fluorescence or mass balance calculations.
  • the substrate/wafer can be moved to a silicon deposition chamber in which the metal suicide layer 310 is deposited.
  • the semiconductor is moved to silicon deposition chamber to receive an amount of silicon to bring the ratio to the predetermined level.
  • the ratio is at the predetermined level, then any other conventional steps that are necessary to complete the production of the semiconductor device 100 are taken.
  • the polysilicon layer 210 and the suicide layer 310 are subjected to a process 410 that forms a crystalline silicon layer 415 at the interface between the suicide layer 310 and the polysilicon layer 210, as illustrated in HTG. 4A.
  • the process 410 is an anneal in which the temperature may range from about 700°C to about 900°C.
  • the silicon present in the suicide layer 310 epitaxially precipitates out to form the crystalline silicon layer 415.
  • the suicide layer may be silicon rich, that is, it may contain a high ratio of silicon to metal.
  • precipitation and anchoring mechanisms are optimized when the process 410 occurs after suicide deposition and no later than spacer deposition, during the fabrication sequence of the device.
  • the process 410 may be a silicon implant, wherein silicon is implanted through the suicide layer 310 and to the interface between the polysilicon layer 210 and the suicide layer 310. In such embodiments, this implant may be followed by an optional anneal step. Those who are skilled in the art would know at what parameters to conduct the implant.
  • FIG. 4B illustrates one embodiment where a conventional masking material, such as a photoresist, has been conventionally deposited and patterned to form a mask 420 over the polysilicon layer 210, the suicide layer 310 after the formation of the crystalline silicon layer 415.
  • FIG. 4C illustrates the device of FIG. 4B following a conventional etch process that forms gate electrodes 425.
  • the gate electrodes 425 include the crystalline silicon layer 415.
  • the process 410 that forms the crystalline silicon layer 415 is conducted prior to the patterning of the gate electrode 425. It is believed that because the process 410 is conducted prior to the formation of multiple overlying material layers and conducted primarily on these layers, the effectiveness of the process 410 that forms the crystalline silicon layer 415 improves its adhesion properties by causing a greater number of silicon bonds to be formed between the polysilicon layer 210 and the suicide layer 310. The increased number of silicon bonds present as the result of the crystalline silicon layer 415 at the interface more securely anchors the polysilicon layer 210 and the suicide layer 310 together more securely.
  • FIG. 5A illustrates another embodiment of the semiconductor device 100.
  • the polysilicon layer 210 and the suicide layer 310 are formed in the manner described above. However, at this point, the crystalline layer has not been formed.
  • a lithographic mask 510 is deposited and patterned over these layers in the same manner previously discussed. This step may be followed by the same conventional etch process mentioned regarding FIG. 4C.
  • the etch forms gate electrodes 515 wherein each electrode includes the patterned gate oxide layer 215, the polysilicon layer 210 and the suicide layer 310, as shown in FIG. 5B.
  • a process 520 which may be the same pxocess as process 410 discussed above, is conducted that forms a crystalline silicon layer 525 between the polysilicon layer 210 and the suicide layer 310. It is believed that forming the crystalline silicon layer 525 in this manner can provide the same improvements in the adhesion between the polysilicon layer 210 and the suicide layer 310, as discussed above regarding other embodiments .
  • conventional processes may then be conducted to form source/drains 530, spacers 535, suicide contacts 540 on opposing sides of the gate electrodes 515 to complete the formation of transistors 545.
  • a dielectric layer 550 may then be formed over the transistors and in which contact plugs can be conventionally formed.
  • the semiconductor device 100 can be configured into an integrated circuit (IC) 600.
  • IC integrated circuit
  • the transistors 545 conventional processes can be used to complete the fabrication of the IC 600.
  • the IC 600 includes the contact dielectric layer 540 and additional interlevel dielectric layers 610.
  • Interconnects 615 which are generally designated, are formed over and within the dielectric layers 610 that interconnect the transistors 550 to form the IC 600.

Abstract

In one aspect, there is provided a method of manufacturing a semiconductor device that includes the steps of forming a polysilicon layer over a substrate, forming a silicide layer on the polysilicon layer, and forming a crystalline silicon layer at an interface between the silicide layer and the polysilicon layer prior to patterning the polysilicon and silicide layers. In another aspect, the crystalline silicon layer is formed prior to forming the contact plugs in a contact or window one dielectric layer.

Description

SEMICONDUCTOR DEVICE HAVING IMPROVED INTERFACE ADHESION OF GATE STACK FIIiMS AND METHOD OF MANUFACTURER THEREFORE
TECHNICAL FIELD
The invention is directed, in general, to a method of manufacturing a semiconductor device and, more specifically, to a method of manufacturing a semiconductor device having an improved interface adhesion between the gate stack films.
BACKGROUND
Doped polycrystalline silicon ("poly-Si") is often used as a gate electrode in metal oxide semiconductor ("MOS") -based circuits. Due to the shrinking size of electrical components in general, MOS devices have also become smaller, and as their size has decreased, the resistivity of the poly-Si, unfortunately, has also increased, which, in turn, has affected the device RC- delay ("RC") . This is disadvantageous to the device because RC delays caused by high sheet resistance between 20-100 ohms/square of poly-Si runners, limit the performance of the integrated circuits with n+ doped poly- Si, and their performance also deteriorates as the length of these runners increases. To overcome the problems associated with this increased resistance, a polycide stack ( "poly-Si/silicide") is extensively used. Typically, the poly-Si is clad with a low-resistivity suicide such that the sheet resistance of the polycide is between 5-10 ohms/sq from 20-100 ohms/sq without the silicide. Unfortunately, however, the manufacturing processes typically used to form the polysilicon/silicide gate stacks often lead to a device where the silicide layer peels away from the polysilicon layer. This peeling can lead to shorts and significant yield loss. Accordingly, there is a need to provide a process and device that does not suffer from the disadvantages associated with present manufacturing processes. SUMMARY
The various embodiments discussed herein address the above-discussed deficiencies of the prior art. Those skilled in the art understand that various embodiments of the invention, in addition to those discussed herein, can readily be recognized given the disclosure set forth herein and should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS
For a more complete understanding of the present invention, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
FIG. 1 illustrates a semiconductor device as provided by one embodiment of the invention;
FIGS. 2-3 illustrate views of one embodiment of a semiconductor device during various stages of fabrication wherein the polysilicon layer and suicide layer are formed;
FIGS. 4A-4C illustrate an embodiment where a crystalline silicon layer is formed at an interface between the suicide layer and the polysilicon layer prior to patterning the polysilicon and suicide layers;
FIGS. 5A-5C illustrate an alternative embodiment where a crystalline silicon layer is formed at an interface between the suicide layer and the polysilicon layer prior to the formation of spacers; and FIG. 6 illustrates the semiconductor device configured as an integrated circuit.
DETAILED DESCRIPTION
FIG. 1 illustrates a general, partial view of one embodiment of a semiconductor device 100. In this embodiment, the semiconductor device 100 includes a substrate 110, such as a semiconductor wafer. Some examples of the substrate materials include silicon, silicon-germanium, gallium arsenide, or indium-containing substrates. The substrate 110 may be the wafer itself or any material layer deposited on the wafer, such as an epitaxial layer. The semiconductor device 100 also includes isolation regions 120 that isolate wells 125 and 130. Conventional processes may be used to form the isolation regions 120 and the well 125, 130. The wells 125, 130 are appropriately doped for an NMOS or PMOS device, and they may be arranged to form a complementary device, such as a CMOS device. The illustrated embodiment further includes transistors 135 that include gate electrodes 140 located over a gate oxide layer 145 and spacers 150 located adjacent the gate electrodes 140. The transistors 135 also include the previously mentioned wells 125, 130 in which conventional source/drains 155 may be formed. The gate electrodes 140 of the embodiment of FIG. 1 further include a polysilicon layer 140a and a suicide layer 140b. A crystalline silicon layer 145 is located at an interface between the polysilicon layer 140a and the suicide layer 140b.
As explained below, the way in which the crystalline silicon layer 145 is formed, some embodiments of which are discussed herein, provides a semiconductor device 100 that has improved adhesion between the polysilicon layer 140a and the suicide layer 140b. Thus, peeling of the silicide layer 140b form the polysilicon layer 140a that can occur in conventional devices is reduced, which in turn, increases product yield.
FIG. 2 illustrates a partial view of one embodiment of the semiconductor device 100 illustrated in FIG. 1 at an early stage of manufacture. In this view, a polysilicon layer 210 has been deposited over the gate oxide layer 215. The thickness of the layer may vary, but in one embodiment, the thickness may be about 100 nm. Conventional process, such as chemical vapor deposition, and thermal oxidation process may be used to form the polysilicon layer 210 and the gate oxide layer 215, respectively. The polysilicon layer 210 may be appropriately doped for proper conductivity using conventional processes.
FIG. 3 illustrates the semiconductor device 100 of FIG. 2, after the formation of a silicide layer 310 over the polysilicon layer 210. The silicide layer 310 may also be deposited using conventional processes, such as chemical vapor deposition or physical vapor (sputter) deposition. The silicide layer 310 may be deposited as an amorphous layer or as a crystalline layer. In those embodiments where it is deposited has an amorphous layer, a subsequent anneal will be conducted to transform the amorphous layer to a crystalline layer. In one embodiment, the silicide layer 310 is a metal silicide layer and may comprise metals, such as tungsten, molybdenum, nickel, cobalt, titanium/ or tantalum.
In those embodiments where the silicide layer is deposited by sputter deposition, a target comprised of silicon and the selected metal may be used. In one particular embodiment, the target is silicon rich. For example, in such embodiments, the metal suicide layer 310 may have stoichiometric ratio of silicon to metal that may range from about 2.0:1 to about 2.8:1, and in another embodiment, the ratio may range from, about 2.2:1 to about 2.5:1. The metal suicide layer 310 can be formed by sputtering atoms from a conventional metal suicide target that comprises metals as those examples noted above .
The metal suicide target, however, is subject to degradation; that is, since more silicon is removed than metal during the deposition process, the silicon on the target reaches a point where there is not a sufficient amount of silicon to maintain the required ratio of excess silicon to metal. In certain embodiments, the metal suicide layer 310 may be deposited to a thickness of about 50-100 nm under a pressure to 2-7 milli-torr and a temperature of about 300-400. degree . C. The ratio of silicon to metal can be monitored and determined, for example on control wafers by such known methods as Rutherford back scattering spectroscopy, x-ray fluorescence or mass balance calculations. When the measured ratio of silicon to metal falls below the predetermined level, the substrate/wafer can be moved to a silicon deposition chamber in which the metal suicide layer 310 is deposited. For example, if the ratio of silicon to metal is 1.8:1, then the semiconductor is moved to silicon deposition chamber to receive an amount of silicon to bring the ratio to the predetermined level. On the other hand, if the ratio is at the predetermined level, then any other conventional steps that are necessary to complete the production of the semiconductor device 100 are taken.
Following the deposition of the suicide layer 310, in one embodiment, the polysilicon layer 210 and the suicide layer 310 are subjected to a process 410 that forms a crystalline silicon layer 415 at the interface between the suicide layer 310 and the polysilicon layer 210, as illustrated in HTG. 4A. In one example, the process 410 is an anneal in which the temperature may range from about 700°C to about 900°C. During the anneal, the silicon present in the suicide layer 310 epitaxially precipitates out to form the crystalline silicon layer 415. As mentioned above, the suicide layer may be silicon rich, that is, it may contain a high ratio of silicon to metal. Without being bound to any particular theory, it is believed that during the anneal, the excess silicon precipitates out to form more silicon bonds between the polysilicon layer 210 and the suicide layer 310 than those found in conventional fabrication processes. It is believed that this increased number of silicon bond strengthens the adhesion coefficient between the two layers and thereby reduces peeling that typically occurs in conventional processes.
Additionally, it has been observed that the precipitation and anchoring mechanisms are optimized when the process 410 occurs after suicide deposition and no later than spacer deposition, during the fabrication sequence of the device.
In another embodiment, the process 410 may be a silicon implant, wherein silicon is implanted through the suicide layer 310 and to the interface between the polysilicon layer 210 and the suicide layer 310. In such embodiments, this implant may be followed by an optional anneal step. Those who are skilled in the art would know at what parameters to conduct the implant. FIG. 4B illustrates one embodiment where a conventional masking material, such as a photoresist, has been conventionally deposited and patterned to form a mask 420 over the polysilicon layer 210, the suicide layer 310 after the formation of the crystalline silicon layer 415. FIG. 4C illustrates the device of FIG. 4B following a conventional etch process that forms gate electrodes 425. In this embodiment, the gate electrodes 425 include the crystalline silicon layer 415. Thus in this particular embodiment, the process 410 that forms the crystalline silicon layer 415 is conducted prior to the patterning of the gate electrode 425. It is believed that because the process 410 is conducted prior to the formation of multiple overlying material layers and conducted primarily on these layers, the effectiveness of the process 410 that forms the crystalline silicon layer 415 improves its adhesion properties by causing a greater number of silicon bonds to be formed between the polysilicon layer 210 and the suicide layer 310. The increased number of silicon bonds present as the result of the crystalline silicon layer 415 at the interface more securely anchors the polysilicon layer 210 and the suicide layer 310 together more securely.
FIG. 5A illustrates another embodiment of the semiconductor device 100. In this embodiment, the polysilicon layer 210 and the suicide layer 310 are formed in the manner described above. However, at this point, the crystalline layer has not been formed. A lithographic mask 510 is deposited and patterned over these layers in the same manner previously discussed. This step may be followed by the same conventional etch process mentioned regarding FIG. 4C. The etch forms gate electrodes 515 wherein each electrode includes the patterned gate oxide layer 215, the polysilicon layer 210 and the suicide layer 310, as shown in FIG. 5B.
Following the patterning of the gate electrodes 515, the semiconductor device 100, a process 520, which may be the same pxocess as process 410 discussed above, is conducted that forms a crystalline silicon layer 525 between the polysilicon layer 210 and the suicide layer 310. It is believed that forming the crystalline silicon layer 525 in this manner can provide the same improvements in the adhesion between the polysilicon layer 210 and the suicide layer 310, as discussed above regarding other embodiments .
In FIG. 5C, conventional processes may then be conducted to form source/drains 530, spacers 535, suicide contacts 540 on opposing sides of the gate electrodes 515 to complete the formation of transistors 545. A dielectric layer 550 may then be formed over the transistors and in which contact plugs can be conventionally formed.
As seen in FIG. 6, the semiconductor device 100 can be configured into an integrated circuit (IC) 600. Upon formation of the transistors 545, conventional processes can be used to complete the fabrication of the IC 600. In the illustrated embodiments, the IC 600 includes the contact dielectric layer 540 and additional interlevel dielectric layers 610. Interconnects 615, which are generally designated, are formed over and within the dielectric layers 610 that interconnect the transistors 550 to form the IC 600. Although the present invention has been described in detail, those skilled in the art should understand that they can make various changes, substitutions and alterations (e.g., determining the amount of separation from a point at or near the depletion edge of the collector to at or near the depletion edge of the isolation region) herein without departing from the spirit and scope of the invention in its broadest form.

Claims

WHAT IS CLAIMED IS:
1. A method of manufacturing a semiconductor device, comprising: forming a polysilicon layer over a substrate; forming a silicide layer on the polysilicon layer; and forming a crystalline silicon layer at an interface between the silicide layer and the polysilicon layer prior to patterning the polysilicon and silicide layers.
2. The method recited in Claim 1, wherein forming the crystalline silicon layer includes annealing the silicide layer and the polysilicon layer to cause the crystalline silicon to precipitate from the silicide layer.
3. The method recited in Claim 2 wherein the annealing temperature ranges from about 700 0C to about 9000C.
4. The method recited in Claim 1 wherein forming the crystalline silicon layer includes implanting silicon through the silicide layer and to the interface.
5. The method recited in Claim 1, wherein forming the silicide layer includes depositing the silicide layer by sputter deposition.
6. The method recited in Claim 5, wherein the sputter deposition forms a silicon rich silicide layer, wherein a stoichiometeric ratio of silicon to metal ranges from about 2.0:1 to about 2.85:1.
7. The method recited in Claim 5, wherein a metal of the suicide layer is tungsten, molybdenum, nickel, cobalt, titanium, or tantalum.
8. The method recited in Claim 1, wherein forming the suicide layer includes depositing the suicide layer by chemical vapor deposition.
9. The method recited in Claim 8, wherein a metal of the suicide layer is tungsten, molybdenum, nickel, cobalt, titanium, or tantalum.
10. A method of manufacturing a semiconductor device, comprising: forming a polysilicon layer over a semiconductor substrate; forming a metal suicide layer on the polysilicon layer; and annealing the polysilicon layer and the metal silicide layer to form a crystalline silicon layer between an interface of the metal silicide layer and the polysilicon layer prior to forming sidewall spacers adjacent the polysilicon layer and the metal silicide layer .
11. The method recited in Claim 10, wherein the annealing causes the crystalline silicon to precipitate from the metal silicide layer and anchor the metal silicide layer to the polysilicon layer.
12. The method recited in Claim 10, wherein the annealing is conducted prior or subsequent to patterning the polysilicon and metal silicide layers.
13. The method recited in Claim 10 wherein the annealing temperature ranges from about 7000C to about 9000C.
14. The method recited in Claim 10, wherein forming the metal suicide layer includes depositing the metal suicide layer by sputter deposition.
15. The method recited in Claim 14, wherein the sputter deposition forms a silicon rich metal suicide layer, wherein a stoichiometeric ratio of silicon to metal ranges from about 2.0:1 to about 2.85:1.
16. The method recited in Claim 14, wherein the metal of the metal silicide layer is tungsten, molybdenum, nickel, cobalt, titanium, or tantalum.
17. The method recited in Claim 10, wherein forming the metal silicide layer includes forming the metal silicide layer by chemical vapor deposition.
18. The method recited in Claim 17, wherein the metal of the metal silicide layer is tungsten, molybdenum, nickel, cobalt, titanium, or tantalum.
19. A method of manufacturing a semiconductor device, comprising: forming a polysilicon layer over a semiconductor substrate; forming a metal silicide layer on the polysilicon layer; and annealing the polysilicon layer and the metal silicide layer at a temperature ranging from about 7000C to about 900 °C to form a crystalline silicon layer between an interface of the metal silicide layer and the polysilicon layer prior to patterning the polysilicon and metal silicide layers, and wherein a stoichiometeric ratio of silicon to metal in the metal suicide layer ranges from about 2.0:1 to about 2.85:1.
20. The method recited in Claim 19, wherein forming the metal suicide layer includes depositing the metal suicide layer by sputter deposition.
21. The method recited in Claim 20, wherein the metal of the metal suicide layer is tungsten, molybdenum, nickel, cobalt, titanium, or tantalum.
22. The method recited in Claim 19, wherein forming the metal suicide layer includes forming the metal suicide layer by chemical vapor deposition.
PCT/US2007/060434 2007-01-12 2007-01-12 Semiconductor device having improved interface adhesion of gate stack films and method of manufacturer therefore WO2008085523A1 (en)

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