WO2008084440A1 - Method of forming an interconnect structure - Google Patents
Method of forming an interconnect structure Download PDFInfo
- Publication number
- WO2008084440A1 WO2008084440A1 PCT/IB2008/050049 IB2008050049W WO2008084440A1 WO 2008084440 A1 WO2008084440 A1 WO 2008084440A1 IB 2008050049 W IB2008050049 W IB 2008050049W WO 2008084440 A1 WO2008084440 A1 WO 2008084440A1
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- dielectric material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A method of forming an interconnect structure for a semiconductor device involving etching patterns of openings (18, 22) in a layer (12) of thermally decomposable filler material and forming either pillars (8) of dielectric 5 material or conductive interconnections in respective patterns of openings. The filler material is subsequently decomposed to form cavities (30) between the pillars and adjacent interconnections, so that air forms the dielectric material therebetween.
Description
DESCRIPTION
METHOD OF FORMING AN INTERCONNECT STRUCTURE
The present invention relates to a method of forming an interconnect structure for an integrated circuit semiconductor device, and more particularly to formation of such a structure with reduced capacitance between the interconnections.
The feature size of integrated circuit semiconductor devices has decreased steadily and as a result the performance of the interconnections between different portions of the device has become an increasingly significant factor in the performance of the device as a whole.
Such interconnects may be manufactured using the so-called "damascene" process, in which a dielectric layer is formed and then etched away leaving a pattern of trenches defining the paths of the desired interconnections. Interconnect metal is then deposited to fill the trenches. This leaves an uneven surface formed by excess metal. A chemical-mechanical polishing (CMP) step is then used to planarize the structure, removing the excess metal from the surface to provide a flat surface suitable for further processing.
Typically, a multi-layer structure is built up from alternating trench layers and via layers. The trench layers include the horizontal interconnects and the via layers provide the vertical connections between the different levels of the multiple interconnect layers and to the underlying semiconductor device.
An important performance characteristic for interconnect structures is minimisation of transmission delays. Such delays are typically determined by the resistance and capacitance of the interconnect. For this reason, copper is increasingly preferred due to its relatively low resistance. Copper can be combined with insulating materials with low dielectric constants, known as low-k materials, to provide interconnects with good performance.
The use of insulating material between adjacent interconnects which has a lower dielectric constant reduces the capacitance of interconnects in the same layer and interconnects in different layers. Reducing the dielectric constant of the intervening material allows the spacing between conductors to be reduced without increasing the associated capacitance, allowing a further reduction in device dimensions.
Use of air as the dielectric provides the lowest possible dielectric constant and it has been proposed to form interconnect structures having air gaps between adjacent interconnects. US-A-5998293 discloses a structure of this form. Spaced apart coplanar pillars of dielectric material are formed and the spaces between the pillars are then filled with a sacrificial material. The air gaps are formed by dissolving the sacrificial material. Vias may be formed within one or more of the pillars.
An alternative approach is described in "Air Gap Integration for the 45nm Node and Beyond" by R Daamen et al, Proceedings of NTC (2005). In this approach, air gaps are formed by decomposing a thermally degradable polymer (PDP). A porous oxide-like hard mask enables out-diffusion of the organic decomposition products. The authors found that certain areas of test structures with wide air gaps were susceptible to collapse of the hard mask, particularly spaces greater than 1 micron across. It is suggested that "dummy" metal interconnect structures may be used to provide support across such wide spaces, but this may increase cross-talk or other electrical interference.
The present invention provides a method of forming an interconnect structure for a semiconductor device, comprising the steps of:
(a) depositing a layer of thermally decomposable filler material over a substrate;
(b) depositing a layer of dielectric material over the filler material;
(c) patterning the dielectric material layer; (d) anisotropically etching away the filler material layer where it is exposed by the dielectric material layer to form an opening which extends through the filler material layer;
(θ) depositing further dielectric material to fill the opening in the filler material layer and so form a pillar therein;
(f) patterning the dielectric material layer to define a layout of interconnections for the interconnect structure; (g) anisotropically etching away the filler material layer where it is exposed by the dielectric material layer to form further openings which extend through the filler material layer;
(h) depositing electrically conductive material to fill the further openings in the filler material layer and form the layout of interconnections; and (i) heating the structure to decompose the filler material and thereby form cavities between the pillar and adjacent interconnections.
The incorporation of supporting pillars of dielectric material in this manner avoids collapse of the overlying dielectric material layer without significantly compromising the reduction of cross-talk achieved by the provision of air cavities/gaps between adjacent interconnections.
The present method may enable the space between an interconnect and an adjacent pillar to be substantially fully replaced by air, without a layer of dielectric material overlying the sidewall of the interconnect for example, to further reduce cross-coupling between adjacent conductors. Preferably, the pillar dielectric material is a low-k dielectric material having a dielectric constant below 3. In a preferred embodiment, the dielectric material layer of the hard mask is formed of the same material as the pillar.
Two or more pillars may be formed between adjacent interconnections where appropriate to provide sufficient support over wider gaps to avoid collapse of the overlying dielectric material layer.
The lateral width of each pillar may be substantially the same as that of the interconnections. Where wider gaps are present, the pillar width may be greater than this to provide additional support. For example, the pillar width may range from 50nm up to 200nm. It will be appreciated that the pillars may be elongated in plan view in the same direction of elongation of adjacent interconnect structures.
The filler material may be an organic material, such as a TDP material, this type of material often being referred to as porogen material.
Suitable choices for the porogen material include polymers of the (meth)acrylate family including resists, which may be fluorinated. Several suitable materials are available from vendors which may include Shipley XP0733 (TM), JRSMicro TDP-C1002 (TM) and Dow Chemical's Houdini (TM).
Suitable materials to form the dielectric material layers and the pillars include porous materials such as the materials sold as Black Diamond (TM) or Aurora (TM). Further examples are BD2x (TM) and Coral (TM).
An embodiment of the invention will now be described by way of example and with reference to the accompanying schematic drawings, wherein:
Figures 1 to 9 show cross-sectional side views of successive stages in the formation of an interconnect structure according to an embodiment of the invention.
An alternative method of forming supporting pillars will then be described with reference to Figures 10 to 13 which show cross-sectional side views of successive stages in such a process.
It should be noted that the Figures are diagrammatic and not drawn to scale. Relative dimensions and proportions of parts of these Figures have been shown exaggerated or reduced in size, for the sake of clarity and convenience in the drawings. The same reference signs are generally used to refer to corresponding or similar features in modified and different embodiments.
Figure 1 shows an initial stage in a process for manufacturing an interconnect structure in accordance with embodiment of the present invention. A layer of TDP material 12 is deposited over a substrate 10. A hard mask layer 14 of dielectric material is then formed over the TDP layer. The substrate may be a dielectric-covered semiconductor substrate or a dielectric-covered layer of interconnect, for example.
As shown in Figure 2, a layer 16 of photoresist material is then deposited and patterned lithographically to define a window 16a. The exposed portions of TDP layer 12 and dielectric layer 14 are then etched away anisotropically. The patterned photoresist layer is then stripped away to leave the structure shown in Figure 3, in which a trench-shaped opening 18 (or pattern of openings in practice) extends completely through dielectric layer 14 and TDP layer 12 to expose a portion of the underlying substrate 10.
Further dielectric material 14' is then deposited so as to fill the opening 18 as shown in Figure 4. This forms a pillar 8 extending vertically through TDP layer 12. Preferably, this further dielectric material is the same as that used to form dielectric material layer 14. This avoids adhesion problems or a mismatch between the coefficients of thermal expansion of the dielectric material layers.
The overlying area of dielectric material 14' is then planarised to form a thinner overlying layer 14" as shown in Figure 5. Known chemical-mechanical polishing techniques may be used to carry out this planarisation step. The use of the same dielectric material for layers 14 and 14' is also advantageous in that it reduces the risk of over etch or dishing which might arise with materials having different etch selectivities during a chemical-mechanical polishing process. A further photoresist layer 20 is provided and patterned photolithographically as shown in Figure 6. The pattern in this layer defines a layout of interconnections for the interconnect structure to be formed in the TDP layer 12. Portions of the dielectric layer 14" and TDP layer 12 directly beneath windows 20a in the photoresist layer 20 are anisotropically etched away to form further trench-shaped openings 22 as shown in Figure 7.
A thin barrier or liner layer (not shown in the Figures) of TaN/Ta for example is formed over exposed surfaces of the structure, before deposition of metallic interconnect material 24, which is typically copper. A planarisation process, such as chemical-mechanical polishing is carried out to remove the conductive material overlying dielectric layer 14". This forms conductive interconnects 26.
The TDP material is then removed by heating the structure sufficiently to cause thermal decomposition thereof. Typically, this may involve heating the structure in a furnace for one hour at around 425 degrees C in a nitrogen atmosphere. The resulting structure is as shown in Figure 9 which includes air gaps or cavities 30 in place of the TDP material. The thin barrier layer may remain over the sidewalls of interconnects 26, but essentially the air gaps 30 extend directly from the sidewalls to the intermediate pillar 8. The pillar 8 supports dielectric layer 14" where it extends over a wide gap between interconnects 26 to prevent collapse thereof. An alternative method of forming pillar structures in combination with air gaps in an interconnect structure will now be described with reference to Figures 10 to 13. A relatively thick layer of dielectric material 52 is deposited over a substrate 50. A pair of trenches 54 is etched through the dielectric material layer 52 as shown in Figure 10 using a patterned photoresist mask layer 56.
The width of the portion 56a of the photoresist layer extending between the trenches 54 is then reduced laterally to the same extent at each edge as shown in Figure 1 1 . A further anisotropic etch of the dielectric material layer is then carried out to remove material from the majority of its thickness to define step 58. This procedure is then repeated with approximately even decrements in the width of photoresist layer portion 56a to form an approximately triangular pillar 60 as shown in Figure 12.
TDP material 62 is deposited and planarised so as to fill the spaces on either side of pillar 60. A further photoresist layer is then deposited and patterned so as to define the required layout of interconnections for the interconnect structure. Trenches 64 are etched through dielectric layer 52 using the photoresist mark as shown in Figure 13. A similar procedure as described above is used to form interconnects 66 of conductive material in the trenches 64. The regions 62 of TDP material are then removed by thermal decomposition thereof in the manner described above so as to leave air gaps
68 on either side of pillar 60 as shown in the finished structure illustrated in Figure 13.
Simulations of the embodiments described above have been carried out using 45nm node dimensions in order to determine the expected interlayer capacitance values for the spacing values of 1 , 2 and 3 microns. Results achieved with rectangular and triangular support cross-sections are shown in Table 1 below alongside results obtained in an ideal situation where no pillar is present.
It can be seen that the presence of the support pillars does not significantly affect the interline capacitance values for wide spaces.
In the simulations, copper interconnects are modelled which are 65nm wide and 140nm high. The dielectric layer spanning between adjacent interconnects has a thickness of 35nm. The distance between the base of the triangular supports and an adjacent interconnect was set at 200nm. The lateral width of the rectangular pillars was defined as 65nm, and their height as 105nm (equal to the height of the interconnect minus the thickness of the dielectric layer).
Table 1 : Comparison of interline capacitance for various schemes
Although Claims have been formulated in this Application to particular combinations of features, it should be understood that the scope of the disclosure of the present invention also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation thereof, whether or not it relates to the same invention as presently claimed in any Claim and whether or not it mitigates any or all of the same technical problems as does the present invention.
Features which are described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable subcombination. The Applicants hereby give notice that new Claims may be formulated to such features and/or combinations of such features during the prosecution of the present Application or of any further Application derived therefrom.
Claims
1 . A method of forming an interconnect structure for a semiconductor device, comprising the steps of: (a) depositing a layer (12) of thermally decomposable filler material over a substrate (10);
(b) depositing a layer of dielectric material (14) over the filler material;
(c) patterning the dielectric material layer;
(d) anisotropically etching away the filler material layer where it is exposed by the dielectric material layer to form an opening (18) which extends through the filler material layer;
(e) depositing further dielectric material to fill the opening in the filler material layer and so form a pillar (8) therein;
(f) patterning the dielectric material layer to define a layout of interconnections for the interconnect structure;
(g) anisotropically etching away the filler material layer where it is exposed by the dielectric material layer to form further openings (22) which extend through the filler material layer;
(h) depositing electrically conductive material to fill the further openings in the filler material layer (12) and form the layout of interconnections (26); and (i) heating the structure to decompose the filler material and thereby form cavities (30) between the pillar (8) and adjacent interconnections (26).
2. A method of claim 1 wherein the pillar (8) is formed of the same material as the dielectric material layer (14).
3. A method of claim 1 or claim 2 wherein two or more pillars (8) are formed between adjacent interconnections (26).
4. A method of any preceding claim wherein the filler material (12) is an organic material.
5. A method of claim 4 wherein the filler material (12) is a porogen material.
6. A method of any preceding claim wherein the dielectric material (14) is a low-k dielectric material having a dielectric constant below 3.
7. A method of any preceding claim wherein the pillar (8) is formed of a low-k dielectric material having a dielectric constant below 3.
8. A method of forming an interconnect structure for a semiconductor device substantially as described herein with reference to the accompanying drawings.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP07100394 | 2007-01-11 | ||
| EP07100394.1 | 2007-01-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2008084440A1 true WO2008084440A1 (en) | 2008-07-17 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/IB2008/050049 WO2008084440A1 (en) | 2007-01-11 | 2008-01-08 | Method of forming an interconnect structure |
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| WO (1) | WO2008084440A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8795952B2 (en) | 2010-02-21 | 2014-08-05 | Tokyo Electron Limited | Line pattern collapse mitigation through gap-fill material application |
| US11163236B2 (en) | 2019-08-16 | 2021-11-02 | Tokyo Electron Limited | Method and process for stochastic driven detectivity healing |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5798559A (en) * | 1996-03-29 | 1998-08-25 | Vlsi Technology, Inc. | Integrated circuit structure having an air dielectric and dielectric support pillars |
| US5908318A (en) * | 1995-12-08 | 1999-06-01 | Advanced Micro Devices, Inc. | Method of forming low capacitance interconnect structures on semiconductor substrates |
| JP2000260864A (en) * | 1999-03-12 | 2000-09-22 | Toshiba Corp | Semiconductor device and manufacture thereof |
| US20040102031A1 (en) * | 2002-11-21 | 2004-05-27 | Kloster Grant M. | Low-K dielectric structure and method |
| US20040222533A1 (en) * | 2003-04-28 | 2004-11-11 | Naofumi Nakamura | Semiconductor device and method of manufacturing the same |
| WO2005109490A1 (en) * | 2004-04-21 | 2005-11-17 | Intel Corporation | Formation of an interconnect structure by decomposing a photosensitive dielectric layer |
-
2008
- 2008-01-08 WO PCT/IB2008/050049 patent/WO2008084440A1/en active Application Filing
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5908318A (en) * | 1995-12-08 | 1999-06-01 | Advanced Micro Devices, Inc. | Method of forming low capacitance interconnect structures on semiconductor substrates |
| US5798559A (en) * | 1996-03-29 | 1998-08-25 | Vlsi Technology, Inc. | Integrated circuit structure having an air dielectric and dielectric support pillars |
| JP2000260864A (en) * | 1999-03-12 | 2000-09-22 | Toshiba Corp | Semiconductor device and manufacture thereof |
| US20040102031A1 (en) * | 2002-11-21 | 2004-05-27 | Kloster Grant M. | Low-K dielectric structure and method |
| US20040222533A1 (en) * | 2003-04-28 | 2004-11-11 | Naofumi Nakamura | Semiconductor device and method of manufacturing the same |
| WO2005109490A1 (en) * | 2004-04-21 | 2005-11-17 | Intel Corporation | Formation of an interconnect structure by decomposing a photosensitive dielectric layer |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8795952B2 (en) | 2010-02-21 | 2014-08-05 | Tokyo Electron Limited | Line pattern collapse mitigation through gap-fill material application |
| US9454081B2 (en) | 2010-02-21 | 2016-09-27 | Tokyo Electron Limited | Line pattern collapse mitigation through gap-fill material application |
| US11163236B2 (en) | 2019-08-16 | 2021-11-02 | Tokyo Electron Limited | Method and process for stochastic driven detectivity healing |
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