WO2008082999A3 - Configuration d'interface lba hôte comprenant une mémoire flash - Google Patents

Configuration d'interface lba hôte comprenant une mémoire flash Download PDF

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Publication number
WO2008082999A3
WO2008082999A3 PCT/US2007/088172 US2007088172W WO2008082999A3 WO 2008082999 A3 WO2008082999 A3 WO 2008082999A3 US 2007088172 W US2007088172 W US 2007088172W WO 2008082999 A3 WO2008082999 A3 WO 2008082999A3
Authority
WO
WIPO (PCT)
Prior art keywords
flash memory
blocks
memory
configuration
interface
Prior art date
Application number
PCT/US2007/088172
Other languages
English (en)
Other versions
WO2008082999A2 (fr
Inventor
Alan Welsh Sinclair
Barry Wright
Original Assignee
Sandisk Corp
Alan Welsh Sinclair
Barry Wright
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/616,228 external-priority patent/US7917686B2/en
Priority claimed from US11/616,231 external-priority patent/US8209461B2/en
Application filed by Sandisk Corp, Alan Welsh Sinclair, Barry Wright filed Critical Sandisk Corp
Publication of WO2008082999A2 publication Critical patent/WO2008082999A2/fr
Publication of WO2008082999A3 publication Critical patent/WO2008082999A3/fr

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0628Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638Organizing or formatting or addressing of data
    • G06F3/0643Management of files
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/0223User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023Free address space management
    • G06F12/0238Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0602Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0608Saving storage space on storage systems
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0602Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061Improving I/O performance
    • G06F3/0611Improving I/O performance in relation to response time
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0628Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638Organizing or formatting or addressing of data
    • G06F3/064Management of blocks
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0668Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671In-line storage system
    • G06F3/0673Single storage device
    • G06F3/0679Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10Providing a specific technical effect
    • G06F2212/1016Performance improvement
    • G06F2212/1024Latency reduction
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72Details relating to flash memory management
    • G06F2212/7201Logical to physical mapping or translation of blocks or pages
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72Details relating to flash memory management
    • G06F2212/7202Allocation control and policies

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)

Abstract

Selon l'invention, des fichiers de données sont attribués à des adresses dans un ou plusieurs blocs logiques d'une interface d'espace adresse logique continu (interface LBA) de type courant d'un système de mémoire flash comprenant des blocs de cellules de mémoire physique. Cette attribution peut être réalisée par le dispositif hôte qui en général, mais pas nécessairement, produit les fichiers de données. Le nombre de blocs logiques contenant des données d'un type quelconque est régulé de façon à réduire l'ampleur de la fragmentation des données de fichier dans les blocs de mémoire physique, ce qui permet de maintenir un bon rendement de mémoire. L'hôte peut configurer les blocs logiques de l'espace adresse en réponse à l'apprentissage des propriétés physiques d'une mémoire à laquelle il est connecté.
PCT/US2007/088172 2006-12-26 2007-12-19 Configuration d'interface lba hôte comprenant une mémoire flash WO2008082999A2 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/616,228 2006-12-26
US11/616,231 2006-12-26
US11/616,228 US7917686B2 (en) 2006-12-26 2006-12-26 Host system with direct data file interface configurability
US11/616,231 US8209461B2 (en) 2006-12-26 2006-12-26 Configuration of host LBA interface with flash memory

Publications (2)

Publication Number Publication Date
WO2008082999A2 WO2008082999A2 (fr) 2008-07-10
WO2008082999A3 true WO2008082999A3 (fr) 2008-10-02

Family

ID=39523331

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/088172 WO2008082999A2 (fr) 2006-12-26 2007-12-19 Configuration d'interface lba hôte comprenant une mémoire flash

Country Status (2)

Country Link
TW (1) TW200842578A (fr)
WO (1) WO2008082999A2 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8219781B2 (en) 2008-11-06 2012-07-10 Silicon Motion Inc. Method for managing a memory apparatus, and associated memory apparatus thereof
TWI410795B (zh) * 2009-06-23 2013-10-01 Phison Electronics Corp 用於快閃記憶體的資料寫入方法及其控制電路與儲存系統
TWI426528B (zh) * 2009-09-30 2014-02-11 Phison Electronics Corp 用於快閃記憶體的區塊管理方法、控制器與儲存系統

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1496437A1 (fr) * 2002-04-15 2005-01-12 Sony Corporation Appareil de stockage de donnees
US20060004950A1 (en) * 2004-06-30 2006-01-05 Jeffrey Wang Flash memory file system having reduced headers
WO2006133597A1 (fr) * 2005-06-15 2006-12-21 Intel Corporation Utilisation d'ecritures de transaction et de mecanisme de mise en antememoire pour ameliorer la performance d'ecriture dans une memoire flash de cellule multi-niveau

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1496437A1 (fr) * 2002-04-15 2005-01-12 Sony Corporation Appareil de stockage de donnees
US20060004950A1 (en) * 2004-06-30 2006-01-05 Jeffrey Wang Flash memory file system having reduced headers
WO2006133597A1 (fr) * 2005-06-15 2006-12-21 Intel Corporation Utilisation d'ecritures de transaction et de mecanisme de mise en antememoire pour ameliorer la performance d'ecriture dans une memoire flash de cellule multi-niveau

Also Published As

Publication number Publication date
TW200842578A (en) 2008-11-01
WO2008082999A2 (fr) 2008-07-10

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