WO2008082976A3 - Method for leakage reduction in fabrication of high -density fram arrays - Google Patents

Method for leakage reduction in fabrication of high -density fram arrays Download PDF

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Publication number
WO2008082976A3
WO2008082976A3 PCT/US2007/088074 US2007088074W WO2008082976A3 WO 2008082976 A3 WO2008082976 A3 WO 2008082976A3 US 2007088074 W US2007088074 W US 2007088074W WO 2008082976 A3 WO2008082976 A3 WO 2008082976A3
Authority
WO
WIPO (PCT)
Prior art keywords
etching
ferroelectric capacitor
ashing
capacitor structure
fabrication
Prior art date
Application number
PCT/US2007/088074
Other languages
French (fr)
Other versions
WO2008082976A2 (en
Inventor
Francis Gabriel Celli
Kezhakkedath R Udayakumar
Gregory B Shinn
Theodore S Moise
Scott R Summerfelt
Original Assignee
Texas Instruments Inc
Francis Gabriel Celli
Kezhakkedath R Udayakumar
Gregory B Shinn
Theodore S Moise
Scott R Summerfelt
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc, Francis Gabriel Celli, Kezhakkedath R Udayakumar, Gregory B Shinn, Theodore S Moise, Scott R Summerfelt filed Critical Texas Instruments Inc
Publication of WO2008082976A2 publication Critical patent/WO2008082976A2/en
Publication of WO2008082976A3 publication Critical patent/WO2008082976A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region

Abstract

A method is provided for fabricating a ferroelectric capacitor structure including a method for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The method comprises etching portions of an upper electrode, etching ferroelectric material (20), and etching a lower electrode to define a patterned ferroelectric capacitor structure, and etching a portion of a lower electrode diffusion barrier structure (30a, 30b). The method further comprises ashing the patterned ferroelectric capacitor structure using a first ashing process, where the ash comprises an oxygen/nitrogen/water-containing ash, performing a wet clean process after the first ashing process, and ashing the patterned ferroelectric capacitor structure using a second ashing process.
PCT/US2007/088074 2006-12-27 2007-12-19 Method for leakage reduction in fabrication of high -density fram arrays WO2008082976A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US87729906P 2006-12-27 2006-12-27
US60/877,299 2006-12-27
US11/706,722 2007-02-15
US11/706,722 US8093070B2 (en) 2004-12-17 2007-02-15 Method for leakage reduction in fabrication of high-density FRAM arrays

Publications (2)

Publication Number Publication Date
WO2008082976A2 WO2008082976A2 (en) 2008-07-10
WO2008082976A3 true WO2008082976A3 (en) 2008-08-21

Family

ID=39261591

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/088074 WO2008082976A2 (en) 2006-12-27 2007-12-19 Method for leakage reduction in fabrication of high -density fram arrays

Country Status (2)

Country Link
US (1) US8093070B2 (en)
WO (1) WO2008082976A2 (en)

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US7727897B2 (en) * 2005-08-30 2010-06-01 Sharp Laboratories Of America, Inc. Method of etching a TE/PCMO stack using an etch stop layer
JP2008294194A (en) * 2007-05-24 2008-12-04 Seiko Epson Corp Method for manufacturing ferroelectric capacitor, and the ferroelectric capacitor
US8445913B2 (en) * 2007-10-30 2013-05-21 Spansion Llc Metal-insulator-metal (MIM) device and method of formation thereof
KR20100072525A (en) * 2008-12-22 2010-07-01 한국전자통신연구원 Non-volatile memory devices and method of forming the same
US8907446B2 (en) * 2009-05-19 2014-12-09 Texas Instruments Incorporated Integrated circuit structure with capacitor and resistor and method for forming
FR2993705B1 (en) * 2012-07-20 2015-05-29 Thales Sa DEVICE COMPRISING A PLURALITY OF THIN LAYERS
EP2711984A1 (en) * 2012-09-21 2014-03-26 Nxp B.V. Metal-insulator-metal capacitor formed within an interconnect metallisation layer of an integrated circuit and manufacturing method thereof
US9305998B2 (en) * 2013-02-11 2016-04-05 Texas Instruments Incorporated Adhesion of ferroelectric material to underlying conductive capacitor plate
US9548348B2 (en) * 2013-06-27 2017-01-17 Cypress Semiconductor Corporation Methods of fabricating an F-RAM
US10446335B2 (en) * 2013-08-08 2019-10-15 Zhuhai Access Semiconductor Co., Ltd. Polymer frame for a chip, such that the frame comprises at least one via in series with a capacitor
US9111944B2 (en) 2013-09-09 2015-08-18 Cypress Semiconductor Corporation Method of fabricating a ferroelectric capacitor
US9590174B2 (en) * 2014-10-08 2017-03-07 Kabushiki Kaisha Toshiba Magnetoresistive memory device and manufacturing method of the same
US9515075B1 (en) 2015-08-31 2016-12-06 Cypress Semiconductor Corporation Method for fabricating ferroelectric random-access memory on pre-patterned bottom electrode and oxidation barrier
US10319635B2 (en) * 2017-05-25 2019-06-11 Sandisk Technologies Llc Interconnect structure containing a metal slilicide hydrogen diffusion barrier and method of making thereof
US10861929B2 (en) * 2018-06-27 2020-12-08 Taiwan Semiconductor Manufacturing Co., Ltd. Electronic device including a capacitor
US10847201B2 (en) * 2019-02-27 2020-11-24 Kepler Computing Inc. High-density low voltage non-volatile differential memory bit-cell with shared plate line
US11476261B2 (en) 2019-02-27 2022-10-18 Kepler Computing Inc. High-density low voltage non-volatile memory with unidirectional plate-line and bit-line and pillar capacitor
US20220216297A1 (en) * 2021-01-05 2022-07-07 Changxin Memory Technologies, Inc. Electrode layer, capacitor and methods for electrode layer and capacitor manufacture
US11812606B2 (en) * 2021-03-05 2023-11-07 Micron Technology, Inc. Semiconductor device having gate trench
US11659714B1 (en) 2021-05-07 2023-05-23 Kepler Computing Inc. Ferroelectric device film stacks with texturing layer, and method of forming such
TWI775427B (en) 2021-05-07 2022-08-21 財團法人工業技術研究院 Ferroelectric memories
US11527277B1 (en) 2021-06-04 2022-12-13 Kepler Computing Inc. High-density low voltage ferroelectric memory bit-cell
US11837268B1 (en) 2022-03-07 2023-12-05 Kepler Computing Inc. Multi-element ferroelectric gain memory bit-cell having stacked and folded planar capacitors with lateral offset
US11741428B1 (en) 2022-12-23 2023-08-29 Kepler Computing Inc. Iterative monetization of process development of non-linear polar material and devices

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4961820A (en) * 1988-06-09 1990-10-09 Fujitsu Limited Ashing method for removing an organic film on a substance of a semiconductor device under fabrication
US20050045590A1 (en) * 2003-05-28 2005-03-03 Hall Lindsey H. FRAM capacitor stack clean
US20060134808A1 (en) * 2004-12-17 2006-06-22 Texas Instruments Incorporated Ferroelectric capacitor stack etch cleaning methods

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000045429A1 (en) * 1999-01-26 2000-08-03 Hitachi, Ltd. Method for fabricating semiconductor integrated circuit device
US6534327B2 (en) 2000-04-13 2003-03-18 Texas Instruments Incorporated Method for reworking metal layers on integrated circuit bond pads
US6500678B1 (en) * 2001-12-21 2002-12-31 Texas Instruments Incorporated Methods of preventing reduction of IrOx during PZT formation by metalorganic chemical vapor deposition or other processing
US6656748B2 (en) * 2002-01-31 2003-12-02 Texas Instruments Incorporated FeRAM capacitor post stack etch clean/repair
US7309448B2 (en) * 2003-08-08 2007-12-18 Applied Materials, Inc. Selective etch process of a sacrificial light absorbing material (SLAM) over a dielectric material

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4961820A (en) * 1988-06-09 1990-10-09 Fujitsu Limited Ashing method for removing an organic film on a substance of a semiconductor device under fabrication
US20050045590A1 (en) * 2003-05-28 2005-03-03 Hall Lindsey H. FRAM capacitor stack clean
US20060134808A1 (en) * 2004-12-17 2006-06-22 Texas Instruments Incorporated Ferroelectric capacitor stack etch cleaning methods

Also Published As

Publication number Publication date
WO2008082976A2 (en) 2008-07-10
US8093070B2 (en) 2012-01-10
US20080081380A1 (en) 2008-04-03

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