WO2008080321A1 - Fixed pattern noise elimination circuit for cmos image sensor - Google Patents

Fixed pattern noise elimination circuit for cmos image sensor Download PDF

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Publication number
WO2008080321A1
WO2008080321A1 PCT/CN2007/070870 CN2007070870W WO2008080321A1 WO 2008080321 A1 WO2008080321 A1 WO 2008080321A1 CN 2007070870 W CN2007070870 W CN 2007070870W WO 2008080321 A1 WO2008080321 A1 WO 2008080321A1
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sram
sub
input
correction values
image sensor
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Wenge Hu
Jingjun Fu
Liangjie Qi
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BYD Co Ltd
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BYD Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/67—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response
    • H04N25/671—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response for non-uniformity detection or correction
    • H04N25/677—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response for non-uniformity detection or correction for reducing the column or line fixed pattern noise
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors

Definitions

  • the present invention relates to a CMOS image sensor, more particularly to a fixed pattern noise elimination circuit for eliminating the fixed pattern noise in CMOS image sensor.
  • CMOS image sensor technique develops rapidly.
  • CMOS image sensor technique has substituted CCD sensing technique in the low-end image and video market, and it is also developing towards the medium-range and the high-end market.
  • CCD image sensor CMOS image sensor has some advantages such as low power consumption, wide dynamic range, high-speed video, high integration, and low cost, etc., and it is suitable for the application fields such as mini digital cameras, portable video telephones, and PC camera, etc.; in addition, CMOS image sensor can also be used in the military reconnaissance and the satellite.
  • the fixed pattern noise exists in CMOS sensor due to the defects in CMOS process and the nonuniformity of the transistor characteristic parameters and passive element parameters;
  • the fixed pattern noise is a kind of intrinsic noise in CMOS image sensor, and human eyes are very sensitive to such kind of noise; therefore, the fixed pattern noise severely effect the imaging quality and must be eliminated in high performance CMOS image sensors.
  • V out / Gain ⁇ V in z +V bias /
  • V ou t* is the output voltage of column / '
  • V 1n / is the input voltage of column / '
  • Vbias* is the bias voltage of column / '
  • / ' is the serial number of the column
  • Gain is the gain of ASP. It is seen from above equation, if the bias voltage values between columns match each other completely for the CMOS image sensor, then Vbias* is a constant value.
  • CDS Correlated Double Sample
  • the aim of present invention is to provide a FPN elimination circuit used for CMOS image sensor, which can eliminate the FPN resulted from the mismatch of the bias values between columns of the processing circuit of CMOS image sensor.
  • the fixed pattern noise elimination circuit for CMOS image sensor in accordance with the present invention comprises a static random access memory (SRAM), a shift register, an analog signal processor (ASP), an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), and a comparator; wherein said SRAM stores the match correction values for each column of the image signal and sends the match correction values to the shift register and DAC; said shift register holds the match correction values; said DAC converts the match correction values to analog values and inputs the analog values to the first input end of said analog signal processor; the second input end of said analog signal processor is the signal input end of the fixed pattern noise elimination circuit for CMOS image sensor; said analog signal processor works with the following transfer function: , where Y O uti is the output voltage of column / ' , V 1n / is the input voltage of column / ' , Vbias* is the bias voltage of column / ' , Vboffseti is the analog voltage of the match correction value for column
  • said input signals input from the second input end of the ASP comprises dark row signals and normal row signals, and the dark row signal is input before the normal row signal for each signal frame.
  • the control signal adjusts the match correction values of each corresponding columns which are stored in the shift register as: if the digital value is greater than the target value, decreases the match correction values; if the digital value is smaller than the target value, increases the match correction value; if the digital value is equal to the target value, keeps the match correction values unchanged.
  • the fixed pattern noise elimination circuit for CMOS image sensor in accordance with the present invention further comprises a decoder, and said SRAM comprises a first Sub-SRAM and a second Sub-SRAM; wherein the first Sub-SRAM stores the match correction values for each columns, and its output is connected to the DAC and the shift register; the decoder generates the addresses for read or write the first Sub-SRAM and the second Sub-SRAM, and the adjusted match correction values in said shift register are written into the second Sub-SRAM as the new match correction values; the values stored in the first Sub-SRAM are updated with the new match correction values stored in the second Sub-SRAM.
  • the SRAM further comprises a multiplexer (MUX) connected between the second Sub-SRAM and the decoder, and designed to control the shift between the read address and the write address of said second Sub-SRAM.
  • MUX multiplexer
  • the multiplexer comprises two AND gates and one OR gate; the read control signal for the second Sub-SRAM and the write address addr[n] of the second Sub-SRAM are input to one of the AND gate, and the write control signal for the second Sub-SRAM and the read address addr[n+m] of the first Sub-SRAM are input to the other AND gate; the output ends of the two AND gates are connected to the input ends of the OR gate, and the OR gate outputs the read/write address for the second Sub-SRAM by connecting its output end to the second Sub-SRAM, where m is the shift between the write address addr[n] of the second Sub-SRAM and the read address addr[n+m] of the first Sub-SRAM.
  • the FPN of the CMOS image sensor is eliminated and the imaging quality of the CMOS image sensor is improved greatly by correcting the nonuniformity resulted from the bias between columns of the CMOS image sensor for each frame.
  • the processing circuit for the CMOS image sensor can work in pipeline mode by adjusting the clock latency between the input signal of the analog signal processor and the output signal of the ADC.
  • Fig. l is a schematic diagram of the fixed pattern noise elimination circuit in accordance with the present invention.
  • Fig.2 is a schematic diagram of the fixed pattern noise elimination circuit in accordance with a preferred embodiment of the present invention
  • Fig.3 is a logic circuit diagram of the multiplexer in accordance with a preferred embodiment of the present invention.
  • the fixed pattern noise elimination circuit comprises a static random access memory (SRAM), a shift register, an analog signal processor (ASP), an ADC, a DAC, and a comparator; wherein said SRAM stores the match correction values for each columns of the image signal and sends the match correction values to the shift register and DAC; the shift register holds the match correction values ; the DAC converts the match correction values to analog values and inputs them to the first input end of the control circuit of said analog signal processor; the second input end of said analog signal processor is the signal input end of the fixed pattern noise elimination circuit; the analog signal processor works with the following transfer function:
  • V out / Gain ⁇ V in z +Vbia S /+Vboff se t/ , where V ou t* ' is the output voltage of column i, V 1n / is the input voltage of column / ' , Vbi as / is the bias voltage of column / ' , Vboffset/ is the analog value converted by the DAC from said match correction value, i is the serial number of the column, and Gain is the gain of said analog signal processor.
  • the voltage V ou t* output from the analog signal processor is input to the input end of the ADC which converts the analog voltage into digital value representing the input analog voltage; the comparator compares the output of said ADC with the target value, and produces a control signal to adjust the match correction values of each corresponding columns which are stored in said shift register; if the digital value is higher than the target value, the match correction value will be decreased a unit n; if the digital value is lower than the target value, the match correction value for the corresponding column will be increased a unit n; if the digital value is equal the target value, the match correction value for the corresponding column will not be adjusted.
  • the adjusted match correction values stored in the shift register will be used as the new match correction values and written into said SRAM.
  • CMOS image sensor includes a black level calibration module which is configured to enable the CMOS image sensor outputs a non-zero constant value in dark condition, and the non-zero constant value is the target value.
  • the function of the black level calibration module is making the image lighter by adjusting the non-zero constant value according to the users' needed.
  • the example of the target value is 32 (as the maximum output value of the sensor is 1024).
  • the recommend value of the target value is any power of 2 (2 X ) which is between 2 and 64.
  • the target value can be got by some circuit implementations, and it is obtained from the ASP in accordance with the present invention.
  • said SRAM comprises two parts, i.e., the first Sub- SRAM and the second Sub- SRAM; the first Sub- SRAM stores the match correction values for each columns, and its output is connected to said DAC and said shift register; a decoder is used to produce the read/write addresses for the first Sub-SRAM and the second Sub-SRAM; said DAC converts the digital signals which are stored in said SRAM into analog signals, and inputs the analog signals to the first input end of said analog signal processor in order to adjust the bias for each columns.
  • Said shift register is used to hold the data output from the first Sub-SRAM, so as to adapt to the clock latency between said analog signal processing circuit (ASP) and the output signal of ADC; the analog signal input V 1n is input to the second input end of said ASP.
  • ASP analog signal processing circuit
  • the output processed by ASP is input to the ADC;
  • ADC converts the analog signals to digital signals;
  • said comparator compares the output data of ADC with the target value which is set to 32; if the data is not equal to 32, the comparator will produce a control signal to increase or decrease the value of the shift register by 1 automatically;
  • the multiplexer (MUX) control the shift between the read address and the write address of the second Sub-SRAM to write the new register value to the address of the second Sub-SRAM; the data stored in the second Sub-SRAM is written to the address of the first Sub-SRAM in the next cycle after the dark row is read, to provide the basis for data correction for the next frame.
  • the present invention employs a feedback method to control bias mismatch between the columns.
  • the transfer function of ASP is as follows: Gain ⁇ V m z +VbW-Vb O ff S et/ , where Vboffset* is the analog voltage value converted by DAC from the match correction value stored in the first Sub-SRAM.
  • VbW VbW is the corrected bias value
  • the transfer function of ASP can be rewritten as: Gain ⁇ V m z + V offse t/'.
  • V ou tz VbW- Therefore, in that case, the VbW values for the columns can be obtained by inputting the entire dark line signals in sequence; VbW reflects the bias values between columns of the CMOS image sensor.
  • the VbW values are compared with the target value after converted into digital signals by ADC, whether the bias values are greater than or smaller than the target value can be determined; then, the value stored in the shift register can be increased or decreased by 1 accordingly, and then updated to the SRAM and applied to the circuit through DAC. Above process is executed for each frame; therefore, it is a continuous control process.
  • the match correction values for the columns are stored in the first Sub-SRAM in digital form, and they are converted into analog signals by DAC and then added to the input of the bias control circuit of ASP.
  • the data in the first Sub-SRAM must be updated, so as to adjust the bias value for every image frame.
  • the new match correction values for the columns will be stored into the second Sub-SRAM.
  • the new match correction values will be read out from the second Sub-SRAM in sequence and written into the first Sub-SRAM in the next cycle for the next row. That update approach is the approach employed in the preferred embodiment of the present invention.
  • the present invention can implement with other methods to update the data in the SRAM.
  • the processing circuit for the CMOS image sensor usually works in pipeline mode, which will result in a latency of several clock cycles between the input signal to ASP and the output signal from ADC.
  • the present invention employs a shift register to hold the SRAM data.
  • a MUX array is applied to control the shift between the read address and the write address of the second Sub-SRAM.
  • the logic circuit of the MUX is shown in Fig.3.
  • Said MUX comprises two AKD gates and a OR gate; read and write control signals output from the timing and control module of the CMOS image sensor are used to control the read and write processes of the second Sub-SRAM; there is a shift m between the write address addr[n] of the second Sub-SRAM and the read address addr[n+m] of the first Sub-SRAM; read control signal and the write address addr[n] of the second Sub-SRAM input to one AND gate, and write control signal and the read address addr[n+m] of the first Sub-SRAM input to the other AND gate; the outputs of the two AND gates are used as the input signals to the OR gate, and the output of the OR gate is used as the read/write address signal for the second Sub-SRAM.
  • Said shift m is the clock latency between the input signal of ASP and the output signal of ADC.
  • the data in the first Sub-SRAM is read out and input to the input of the bias control circuit of ASP via the DAC, write operation is performed for the second Sub-SRAM at the same time.
  • the output from ADC is the signal of column 0; therefore, the match correction value written into the second Sub-SRAM is the match correction value for column 0. Therefore, after the dark row is read out, when the match correction value in the second Sub-SRAM is written into the first Sub-SRAM during the next row scan cycle time, the address must be added with m, so that the match correction value in the first Sub-SRAM can be updated correctly.
  • the target value for VbW is set to 32; the target value can be set by the dark background control circuit. Therefore, the present invention can be used in conjunction with the dark background control circuit. In addition, the present invention can also be used with CDS technique.

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Abstract

The present invention discloses a fixed pattern noise elimination circuit for CMOS image sensor, comprising a static random access memory (SRAM), a shift register, an analog signal processor (ASP), an analog-to-digital converter (ADC), a digital-to-analog converter (DAC) and a comparator. With the present invention, the nonuniformity resulted from the bias mismatch between columns of the CMOS image sensor can be corrected for each frame; therefore, the fixed pattern noise (FPN) in the CMOS image sensor can be eliminated, the imaging quality of the CMOS image sensor can be improved greatly, and the processing circuit for the CMOS image sensor can work in pipeline mode.

Description

Fixed Pattern Noise Elimination Circuit for CMOS Image Sensor
Field of the Invention
The present invention relates to a CMOS image sensor, more particularly to a fixed pattern noise elimination circuit for eliminating the fixed pattern noise in CMOS image sensor.
Background Art
As CMOS process and the solid image sensor technique improve, CMOS image sensor technique develops rapidly. CMOS image sensor technique has substituted CCD sensing technique in the low-end image and video market, and it is also developing towards the medium-range and the high-end market. Compared to CCD image sensor, CMOS image sensor has some advantages such as low power consumption, wide dynamic range, high-speed video, high integration, and low cost, etc., and it is suitable for the application fields such as mini digital cameras, portable video telephones, and PC camera, etc.; in addition, CMOS image sensor can also be used in the military reconnaissance and the satellite.
However, the fixed pattern noise (FPN) exists in CMOS sensor due to the defects in CMOS process and the nonuniformity of the transistor characteristic parameters and passive element parameters; the fixed pattern noise is a kind of intrinsic noise in CMOS image sensor, and human eyes are very sensitive to such kind of noise; therefore, the fixed pattern noise severely effect the imaging quality and must be eliminated in high performance CMOS image sensors.
In a CMOS image sensor without the FPN elimination circuit, the transfer function of ASP is:
Vout/ = Gain χVinz +Vbias/ , where Vout* is the output voltage of column /', V1n/ is the input voltage of column /', Vbias* is the bias voltage of column /', /' is the serial number of the column, and Gain is the gain of ASP. It is seen from above equation, if the bias voltage values between columns match each other completely for the CMOS image sensor, then Vbias* is a constant value. However, since the non-idealization of the manufacturing technique and the nonuniformity of the parasitical parameter, it is impossible that the sample and hold circuits and buffers can match each other completed between the columns, i.e., it is inevitable that the bias values don't match to each other between the columns; as a result the FPN exists in the CMOS image sensor.
Although the prior art of Correlated Double Sample (CDS) technology can eliminate the FPN resulted from the nonuniformity of the transistors parameters of the pixel unit, other subsequent CMOS processing circuits, such as the sampling circuit and the column buffer, etc., introduce a great deal of FPN. Such kind of FPN must be eliminated in order to obtain high performance CMOS image sensors.
Summary of the Invention The aim of present invention is to provide a FPN elimination circuit used for CMOS image sensor, which can eliminate the FPN resulted from the mismatch of the bias values between columns of the processing circuit of CMOS image sensor.
The fixed pattern noise elimination circuit for CMOS image sensor in accordance with the present invention comprises a static random access memory (SRAM), a shift register, an analog signal processor (ASP), an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), and a comparator; wherein said SRAM stores the match correction values for each column of the image signal and sends the match correction values to the shift register and DAC; said shift register holds the match correction values; said DAC converts the match correction values to analog values and inputs the analog values to the first input end of said analog signal processor; the second input end of said analog signal processor is the signal input end of the fixed pattern noise elimination circuit for CMOS image sensor; said analog signal processor works with the following transfer function:
Figure imgf000003_0001
, where YOuti is the output voltage of column /', V1n/ is the input voltage of column /', Vbias* is the bias voltage of column /', Vboffseti is the analog voltage of the match correction value for column i which is converted by the DAC, i is the serial number of the column, and Gain is the gain of the ASP; the voltage Vout* output from the ASP is input to the input end of the ADC, the ADC converts the input analog voltage into digital value which represent the input analog voltage; the comparator compares the digital value output from the ADC with the target value and produces a control signal used to adjust the match correction values of each corresponding columns which are stored in the shift register; and the adjusted match correction values in the shift register will be used as the new match correction values and written into the SRAM.
Preferably, said input signals input from the second input end of the ASP comprises dark row signals and normal row signals, and the dark row signal is input before the normal row signal for each signal frame. Preferably, the control signal adjusts the match correction values of each corresponding columns which are stored in the shift register as: if the digital value is greater than the target value, decreases the match correction values; if the digital value is smaller than the target value, increases the match correction value; if the digital value is equal to the target value, keeps the match correction values unchanged. Preferably, the fixed pattern noise elimination circuit for CMOS image sensor in accordance with the present invention further comprises a decoder, and said SRAM comprises a first Sub-SRAM and a second Sub-SRAM; wherein the first Sub-SRAM stores the match correction values for each columns, and its output is connected to the DAC and the shift register; the decoder generates the addresses for read or write the first Sub-SRAM and the second Sub-SRAM, and the adjusted match correction values in said shift register are written into the second Sub-SRAM as the new match correction values; the values stored in the first Sub-SRAM are updated with the new match correction values stored in the second Sub-SRAM.
Preferably, the SRAM further comprises a multiplexer (MUX) connected between the second Sub-SRAM and the decoder, and designed to control the shift between the read address and the write address of said second Sub-SRAM.
Preferably, the multiplexer comprises two AND gates and one OR gate; the read control signal for the second Sub-SRAM and the write address addr[n] of the second Sub-SRAM are input to one of the AND gate, and the write control signal for the second Sub-SRAM and the read address addr[n+m] of the first Sub-SRAM are input to the other AND gate; the output ends of the two AND gates are connected to the input ends of the OR gate, and the OR gate outputs the read/write address for the second Sub-SRAM by connecting its output end to the second Sub-SRAM, where m is the shift between the write address addr[n] of the second Sub-SRAM and the read address addr[n+m] of the first Sub-SRAM.
With the present invention, the FPN of the CMOS image sensor is eliminated and the imaging quality of the CMOS image sensor is improved greatly by correcting the nonuniformity resulted from the bias between columns of the CMOS image sensor for each frame. In addition, the processing circuit for the CMOS image sensor can work in pipeline mode by adjusting the clock latency between the input signal of the analog signal processor and the output signal of the ADC.
Brief Description of the Drawings
Fig. l is a schematic diagram of the fixed pattern noise elimination circuit in accordance with the present invention;
Fig.2 is a schematic diagram of the fixed pattern noise elimination circuit in accordance with a preferred embodiment of the present invention; and Fig.3 is a logic circuit diagram of the multiplexer in accordance with a preferred embodiment of the present invention.
Detailed Description of the Embodiments
As shown in Fig. l, the fixed pattern noise elimination circuit comprises a static random access memory (SRAM), a shift register, an analog signal processor (ASP), an ADC, a DAC, and a comparator; wherein said SRAM stores the match correction values for each columns of the image signal and sends the match correction values to the shift register and DAC; the shift register holds the match correction values ; the DAC converts the match correction values to analog values and inputs them to the first input end of the control circuit of said analog signal processor; the second input end of said analog signal processor is the signal input end of the fixed pattern noise elimination circuit; the analog signal processor works with the following transfer function:
Vout/ = Gain χVinz +VbiaS/+Vboffset/ , where Vout*' is the output voltage of column i, V1n/ is the input voltage of column /', Vbias/ is the bias voltage of column /', Vboffset/ is the analog value converted by the DAC from said match correction value, i is the serial number of the column, and Gain is the gain of said analog signal processor. The voltage Vout* output from the analog signal processor is input to the input end of the ADC which converts the analog voltage into digital value representing the input analog voltage; the comparator compares the output of said ADC with the target value, and produces a control signal to adjust the match correction values of each corresponding columns which are stored in said shift register; if the digital value is higher than the target value, the match correction value will be decreased a unit n; if the digital value is lower than the target value, the match correction value for the corresponding column will be increased a unit n; if the digital value is equal the target value, the match correction value for the corresponding column will not be adjusted. The adjusted match correction values stored in the shift register will be used as the new match correction values and written into said SRAM. The target value can be adjusted as the users' needed. Generally, CMOS image sensor includes a black level calibration module which is configured to enable the CMOS image sensor outputs a non-zero constant value in dark condition, and the non-zero constant value is the target value. The function of the black level calibration module is making the image lighter by adjusting the non-zero constant value according to the users' needed. According to the present invention, the example of the target value is 32 (as the maximum output value of the sensor is 1024). The recommend value of the target value is any power of 2 (2X) which is between 2 and 64. The target value can be got by some circuit implementations, and it is obtained from the ASP in accordance with the present invention.
Hereunder the present invention will be described with a preferred embodiment of the present invention. As shown in Fig.2, said SRAM comprises two parts, i.e., the first Sub- SRAM and the second Sub- SRAM; the first Sub- SRAM stores the match correction values for each columns, and its output is connected to said DAC and said shift register; a decoder is used to produce the read/write addresses for the first Sub-SRAM and the second Sub-SRAM; said DAC converts the digital signals which are stored in said SRAM into analog signals, and inputs the analog signals to the first input end of said analog signal processor in order to adjust the bias for each columns. Said shift register is used to hold the data output from the first Sub-SRAM, so as to adapt to the clock latency between said analog signal processing circuit (ASP) and the output signal of ADC; the analog signal input V1n is input to the second input end of said ASP. The output processed by ASP is input to the ADC; ADC converts the analog signals to digital signals; said comparator compares the output data of ADC with the target value which is set to 32; if the data is not equal to 32, the comparator will produce a control signal to increase or decrease the value of the shift register by 1 automatically; the multiplexer (MUX) control the shift between the read address and the write address of the second Sub-SRAM to write the new register value to the address of the second Sub-SRAM; the data stored in the second Sub-SRAM is written to the address of the first Sub-SRAM in the next cycle after the dark row is read, to provide the basis for data correction for the next frame.
In order to eliminate the FPN, the present invention employs a feedback method to control bias mismatch between the columns. As shown in Fig.2, the transfer function of ASP is as follows:
Figure imgf000007_0001
Gain χVmz +VbW-VbOffSet/ , where Vboffset* is the analog voltage value converted by DAC from the match correction value stored in the first Sub-SRAM. Let VbW
Figure imgf000007_0002
(VbW is the corrected bias value), then the transfer function of ASP can be rewritten as:
Figure imgf000007_0003
Gain χVmz + Voffset/'.
As indicated in above transfer function, when the input signal V1n/ is 0, (i.e., the input signal is a dark row signal), Voutz = VbW- Therefore, in that case, the VbW values for the columns can be obtained by inputting the entire dark line signals in sequence; VbW reflects the bias values between columns of the CMOS image sensor. The VbW values are compared with the target value after converted into digital signals by ADC, whether the bias values are greater than or smaller than the target value can be determined; then, the value stored in the shift register can be increased or decreased by 1 accordingly, and then updated to the SRAM and applied to the circuit through DAC. Above process is executed for each frame; therefore, it is a continuous control process. In the embodiment, the match correction values for the columns are stored in the first Sub-SRAM in digital form, and they are converted into analog signals by DAC and then added to the input of the bias control circuit of ASP. The data in the first Sub-SRAM must be updated, so as to adjust the bias value for every image frame. In this embodiment, after the signals of an entire dark row are processed, the new match correction values for the columns will be stored into the second Sub-SRAM. The new match correction values will be read out from the second Sub-SRAM in sequence and written into the first Sub-SRAM in the next cycle for the next row. That update approach is the approach employed in the preferred embodiment of the present invention. Of course, the present invention can implement with other methods to update the data in the SRAM.
In order to output video at a high frame rate, the processing circuit for the CMOS image sensor usually works in pipeline mode, which will result in a latency of several clock cycles between the input signal to ASP and the output signal from ADC. To adapt to that operation mode, the present invention employs a shift register to hold the SRAM data. In the optimal embodiment of the present invention, in order to ensure the data in the first Sub-SRAM can be updated correctly, a MUX array is applied to control the shift between the read address and the write address of the second Sub-SRAM. The logic circuit of the MUX is shown in Fig.3. Said MUX comprises two AKD gates and a OR gate; read and write control signals output from the timing and control module of the CMOS image sensor are used to control the read and write processes of the second Sub-SRAM; there is a shift m between the write address addr[n] of the second Sub-SRAM and the read address addr[n+m] of the first Sub-SRAM; read control signal and the write address addr[n] of the second Sub-SRAM input to one AND gate, and write control signal and the read address addr[n+m] of the first Sub-SRAM input to the other AND gate; the outputs of the two AND gates are used as the input signals to the OR gate, and the output of the OR gate is used as the read/write address signal for the second Sub-SRAM. Said shift m is the clock latency between the input signal of ASP and the output signal of ADC. When the data in the first Sub-SRAM is read out and input to the input of the bias control circuit of ASP via the DAC, write operation is performed for the second Sub-SRAM at the same time. However, due to the existence of clock latency, the data written into the second Sub-SRAM doesn't map to the data read from the first Sub-SRAM. For example, if m=3, then the match correction value of column 3 in the first Sub-SRAM is read out, i.e., ASP adjusts the match correction value for column 3. However, at that time, the output from ADC is the signal of column 0; therefore, the match correction value written into the second Sub-SRAM is the match correction value for column 0. Therefore, after the dark row is read out, when the match correction value in the second Sub-SRAM is written into the first Sub-SRAM during the next row scan cycle time, the address must be added with m, so that the match correction value in the first Sub-SRAM can be updated correctly.
In above embodiment, the target value for VbW is set to 32; the target value can be set by the dark background control circuit. Therefore, the present invention can be used in conjunction with the dark background control circuit. In addition, the present invention can also be used with CDS technique.

Claims

Claims
1. A fixed pattern noise elimination circuit for CMOS image sensor, comprising a static random access memory (SRAM), a shift register, an analog signal processor (ASP), an analog-to-digital converter (ADC), a digital-to-analog converter (DAC) and a comparator; wherein said SRAM stores the match correction values for each column of the image signal and sends the match correction values to the shift register and DAC; said shift register holds the match correction values; said DAC converts the match correction values to analog values and inputs the analog values to the first input end of said ASP; the second input end of said ASP is the signal input end of the fixed pattern noise elimination circuit; said ASP works with the following transfer function:
Figure imgf000009_0001
, where Vout* is the output voltage of column /', V1n/ is the input voltage of column /', Vbias* is the bias voltage of column /', Vboffset* is the analog voltage of the match correction value for column i which is converted by the DAC, i is the serial number of the column, and Gain is the gain of the ASP; the voltage Vout* output from said ASP is input to the input ends of said ADC; said ADC converts the input analog voltage into digital value which represent the input analog voltage; said comparator compares the digital value output from said ADC with the target value and produces a control signal used to adjust the match correction values of each corresponding columns which are stored in said shift register; and the adjusted match correction values in said shift register will be used as new match correction values and written into said SRAM.
2. The fixed pattern noise elimination circuit for CMOS image sensor of claim 1, wherein the signals input from the second input end of said ASP comprises dark row signals and normal row signals, and for each frame the signal input order is: the dark row signal is input before the normal row signal.
3. The fixed pattern noise elimination circuit for CMOS image sensor of claim 1, wherein said control signal adjusts the match correction values of each corresponding columns which are stored in said shift register as: if the digital value is greater than the target value, decreases the match correction values; if the digital value is smaller than the target value, increases the match correction value; if the digital value is equal to the target value, keeps the match correction values unchanged.
4. The fixed pattern noise elimination circuit for CMOS image sensor of claim 1, further comprising a decoder, and said SRAM comprises a first Sub-SRAM and a second
Sub- SRAM; the first Sub-SRAM stores the match correction values for each columns and its output end is connected to the DAC and the shift register; the decoder generates the addresses for read or write the first Sub-SRAM and the second Sub-SRAM, and the adjusted match correction values in said shift register are written into the second Sub-SRAM as the new match correction values; the match correction values stored in the first Sub-SRAM are updated with the new match correction values stored in the second Sub-SRAM.
5. The fixed pattern noise elimination circuit for CMOS image sensor of claim 4, wherein said SRAM further comprises a multiplexer (MUX) connected between said second Sub-SRAM and said decoder, and designed to control the shift between the read address and the write address of said second Sub-SRAM.
6. The fixed pattern noise elimination circuit for CMOS image sensor of claim 5, wherein said multiplexer comprises two AND gates and one OR gate; the read control signal for the second Sub-SRAM and the write address addr[n] of the second Sub-SRAM are input to one of the AND gate, and the write control signal for the second Sub-SRAM and the read address addr[n+m] of the first Sub-SRAM are input to the other AND gate; the outputs ends of the two AND gates are connected to the input ends of the OR gate, and the OR gate outputs the read/write address for the second Sub-SRAM by connecting its output end to the second Sub-SRAM, where m is the shift between the write address addr[n] of the second Sub-SRAM and the read address addr[n+m] of the first Sub-SRAM.
7. The fixed pattern noise elimination circuit for CMOS image sensor of claim 6, wherein said shift m is the clock latency between the input signals to said ASP and the output signals from said ADC.
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