WO2008078564A1 - 情報処理装置、集積回路、方法、およびプログラム - Google Patents

情報処理装置、集積回路、方法、およびプログラム Download PDF

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Publication number
WO2008078564A1
WO2008078564A1 PCT/JP2007/074006 JP2007074006W WO2008078564A1 WO 2008078564 A1 WO2008078564 A1 WO 2008078564A1 JP 2007074006 W JP2007074006 W JP 2007074006W WO 2008078564 A1 WO2008078564 A1 WO 2008078564A1
Authority
WO
WIPO (PCT)
Prior art keywords
cpu
program
information processing
processing device
integrated circuit
Prior art date
Application number
PCT/JP2007/074006
Other languages
English (en)
French (fr)
Inventor
Takayuki Ito
Manabu Maeda
Yoshikatsu Ito
Original Assignee
Panasonic Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corporation filed Critical Panasonic Corporation
Priority to EP07850527A priority Critical patent/EP2040192A4/en
Priority to JP2008551030A priority patent/JP5161791B2/ja
Priority to US12/375,977 priority patent/US8060716B2/en
Publication of WO2008078564A1 publication Critical patent/WO2008078564A1/ja

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/468—Specific access rights for resources, e.g. using capability register
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/74—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information operating in dual or compartmented mode, i.e. at least one secure mode

Abstract

　処理能力の向上を図りつつ、保護されるべきプログラムやデータを安全に扱うことができる情報処理装置を提供することを目的とする。 　複数のＣＰＵを搭載したシステムＬＳＩ１００において、ＣＰＵ－１　１０２が保護モードへ遷移する場合、先ず、ＣＰＵ－１　１０２とＣＰＵ－２　１０３にリセットを行う。保護モード実行中には、ＣＰＵ－１　１０２のみで保護プログラムを実行し、ＣＰＵ－２　１０３にはリセット信号を投入し続けることでＣＰＵ－２　１０３の動作を停止させる。
PCT/JP2007/074006 2006-12-22 2007-12-13 情報処理装置、集積回路、方法、およびプログラム WO2008078564A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP07850527A EP2040192A4 (en) 2006-12-22 2007-12-13 INFORMATION PROCESSING DEVICE, INTEGRATED CIRCUIT, METHOD, AND PROGRAM
JP2008551030A JP5161791B2 (ja) 2006-12-22 2007-12-13 情報処理装置、集積回路、方法、およびプログラム
US12/375,977 US8060716B2 (en) 2006-12-22 2007-12-13 Information processing device for securely processing data that needs to be protected using a secure memory

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2006-346714 2006-12-22
JP2006346714 2006-12-22

Publications (1)

Publication Number Publication Date
WO2008078564A1 true WO2008078564A1 (ja) 2008-07-03

Family

ID=39562358

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/074006 WO2008078564A1 (ja) 2006-12-22 2007-12-13 情報処理装置、集積回路、方法、およびプログラム

Country Status (4)

Country Link
US (1) US8060716B2 (ja)
EP (1) EP2040192A4 (ja)
JP (1) JP5161791B2 (ja)
WO (1) WO2008078564A1 (ja)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010055371A (ja) * 2008-08-28 2010-03-11 Fujitsu Ltd 情報漏洩防止プログラムおよび情報漏洩防止方法
JP2010102694A (ja) * 2008-10-22 2010-05-06 Internatl Business Mach Corp <Ibm> 高スレッド化ネットワーク・オン・ア・チップ・プロセッサにおけるスループットをユーザが損なうのを防止するためのセキュリティ方法
JP2010170387A (ja) * 2009-01-23 2010-08-05 Toshiba Corp 画像処理装置、方法、及びプログラム
JP2010182296A (ja) * 2009-01-08 2010-08-19 Panasonic Corp プログラム実行装置、制御方法、制御プログラム及び集積回路
JP2012174228A (ja) * 2011-02-24 2012-09-10 Kyocera Corp プログラム保護装置および通信装置

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8219772B2 (en) * 2009-07-02 2012-07-10 Stmicroelectronics (Research & Development) Limited Loading secure code into a memory
US20120054773A1 (en) * 2010-08-31 2012-03-01 International Business Machines Corporation Processor support for secure device driver architecture
US20120162449A1 (en) * 2010-12-23 2012-06-28 Matthias Braun Digital image stabilization device and method
US9087196B2 (en) * 2010-12-24 2015-07-21 Intel Corporation Secure application attestation using dynamic measurement kernels
US8713262B2 (en) * 2011-09-02 2014-04-29 Nvidia Corporation Managing a spinlock indicative of exclusive access to a system resource
JP5541275B2 (ja) * 2011-12-28 2014-07-09 富士通株式会社 情報処理装置および不正アクセス防止方法
US9171170B2 (en) * 2012-08-17 2015-10-27 Broadcom Corporation Data and key separation using a secure central processing unit
US9881161B2 (en) 2012-12-06 2018-01-30 S-Printing Solution Co., Ltd. System on chip to perform a secure boot, an image forming apparatus using the same, and method thereof
EP3506143B1 (en) * 2017-12-27 2024-02-14 Siemens Aktiengesellschaft Interface for a hardware security module
TWI741271B (zh) * 2018-10-02 2021-10-01 智微科技股份有限公司 資料保護方法以及相關儲存裝置
US11144217B2 (en) * 2018-10-02 2021-10-12 Jmicron Technology Corp. Data protection method and associated storage device
JP7210238B2 (ja) * 2018-11-15 2023-01-23 キヤノン株式会社 情報処理装置、情報処理装置の制御方法、及び、プログラム

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003085497A2 (en) * 2002-03-29 2003-10-16 Intel Corporation System and method for execution of a secured environment initialization instruction
WO2003090074A2 (en) * 2002-04-18 2003-10-30 Advanced Micro Devices, Inc. Initialization of a computer system including a secure execution mode-capable processor
WO2004015553A1 (en) * 2002-08-13 2004-02-19 Nokia Corporation Computer architecture for executing a program in a secure of insecure mode
JP2005099984A (ja) 2003-09-24 2005-04-14 Toshiba Corp オンチップマルチコア型耐タンパプロセッサ
WO2006057316A1 (ja) * 2004-11-26 2006-06-01 Matsushita Electric Industrial Co., Ltd. プロセッサ、セキュア処理システム

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6938164B1 (en) 2000-11-22 2005-08-30 Microsoft Corporation Method and system for allowing code to be securely initialized in a computer
AU2003231070A1 (en) * 2002-04-18 2003-11-03 Advanced Micro Devices Inc. A computer system including a secure execution mode - capable cpu and a security services processor connected via a secure communication path
US7603551B2 (en) * 2003-04-18 2009-10-13 Advanced Micro Devices, Inc. Initialization of a computer system including a secure execution mode-capable processor
EP1535124B1 (en) * 2002-08-13 2011-02-02 Nokia Corporation Computer architecture for executing a program in a secure of insecure mode
JP2005011336A (ja) 2003-05-29 2005-01-13 Matsushita Electric Ind Co Ltd オペレーティングシステム切り替え可能な情報処理装置
US7503049B2 (en) 2003-05-29 2009-03-10 Panasonic Corporation Information processing apparatus operable to switch operating systems
WO2006082990A1 (en) 2005-02-07 2006-08-10 Sony Computer Entertainment Inc. Methods and apparatus for secure processor collaboration in a multi-processor system

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003085497A2 (en) * 2002-03-29 2003-10-16 Intel Corporation System and method for execution of a secured environment initialization instruction
WO2003090074A2 (en) * 2002-04-18 2003-10-30 Advanced Micro Devices, Inc. Initialization of a computer system including a secure execution mode-capable processor
WO2004015553A1 (en) * 2002-08-13 2004-02-19 Nokia Corporation Computer architecture for executing a program in a secure of insecure mode
JP2005099984A (ja) 2003-09-24 2005-04-14 Toshiba Corp オンチップマルチコア型耐タンパプロセッサ
WO2006057316A1 (ja) * 2004-11-26 2006-06-01 Matsushita Electric Industrial Co., Ltd. プロセッサ、セキュア処理システム

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2040192A4 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010055371A (ja) * 2008-08-28 2010-03-11 Fujitsu Ltd 情報漏洩防止プログラムおよび情報漏洩防止方法
JP2010102694A (ja) * 2008-10-22 2010-05-06 Internatl Business Mach Corp <Ibm> 高スレッド化ネットワーク・オン・ア・チップ・プロセッサにおけるスループットをユーザが損なうのを防止するためのセキュリティ方法
JP2010182296A (ja) * 2009-01-08 2010-08-19 Panasonic Corp プログラム実行装置、制御方法、制御プログラム及び集積回路
JP2010170387A (ja) * 2009-01-23 2010-08-05 Toshiba Corp 画像処理装置、方法、及びプログラム
JP2012174228A (ja) * 2011-02-24 2012-09-10 Kyocera Corp プログラム保護装置および通信装置

Also Published As

Publication number Publication date
US8060716B2 (en) 2011-11-15
JP5161791B2 (ja) 2013-03-13
EP2040192A1 (en) 2009-03-25
US20100005264A1 (en) 2010-01-07
JPWO2008078564A1 (ja) 2010-04-22
EP2040192A4 (en) 2011-03-30

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