WO2008077411A2

WO2008077411A2 - Method of extracting data from a serial data stream

Info

Publication number: WO2008077411A2
Application number: PCT/DK2007/050202
Authority: WO
Inventors: Morten Lave
Original assignee: The Tc Group A/S
Priority date: 2006-12-22
Filing date: 2007-12-20
Publication date: 2008-07-03
Also published as: WO2008077411A3

Abstract

The invention relates to a method of extracting data from an input serial data stream, comprising the steps of over-sampling said input serial data stream by establishing at least two samples per time window of said input serial data stream, evaluating said established samples to determine at least one time window representative sample per time window of said input serial data stream to provide as part of an output serial data stream.

Description

METHOD OF EXTRACTING DATA FROM A SERIAL DATA STREAM

Cross-reference to related application

This application claims the benefit under 35 U.S. C. §119(e) of the earlier filing date of U.S. Provisional Application Serial Number 60/876,602 filed on December 22, 2006, which is hereby incorporated by reference.

Field of the invention

The present invention relates to receivers for serial data streams.

Background of the invention

Typically, transmission of digital audio is performed by serial data interfaces, capable of transmitting at least one, typically two, and in some protocols even eight or more channels per interface. Popular digital audio interfaces comprise, e.g., the consumer S/PDIF standard and the professional AES/EBU and ADAT standards. Typically, the AES/EBU standard is used with wired XLR connections, while the S/PDIF standard is used in both wired phono connections and optical connections, e.g.. CP340 or Tos-link, and the ADAT standard typically in optical connections. Typically, the S/PDIF and AES/EBU standards are used for transmitting two audio channels and auxiliary data, while the ADAT standard is capable of transmitting eight 24-bit audio channels and auxiliary data.

Common to all the protocols described above, and other serial data protocols, is that the data stream is grouped into frames, where each frame comprises one data word of each included channel and auxiliary data. Moreover, each frame includes a unique pattern in order to facilitate the receiver to synchronize to the data stream by searching for that pattern. In the AES/EBU protocol, for example, a frame contains 64 bits made up by 4 bit preamble "start of frame", 24 bit audio channel "A", 4 bit auxiliary data, e.g. check bit, parity, user data, etc., another 4 bit preamble "start of 2^nd channel", another 24 bit audio channel "B" and finally another 4 bit auxiliary data. This is illustrated in figure IA, where HA and HB illustrate preambles, 12A and 12B illustrate audio data of channel "A" and "B" respectively, and 13A and 13B illustrate auxiliary data. The bit stream is in the physical layer encoded in a bi-phase-mark format. The preamble 1 IA, which indicates the start of each frame is, however, encoded differently and thus forms a signal pattern that can never occur in the data fields. Furthermore, for each 192 frames, yet a different preamble HA is used. Thereby receivers can monitor the stream for the unique preambles HA and thereby synchronize themselves to the data stream.

In the ADAT protocol illustrated in figure IB, for example see US Patent 5,297,181 to Alesis, hereby incorporated by reference, a frame contains 256 bits made up by 8 audio channels 22A, 22B, 22C, 22D, 22E, 22F, 22G, 22H, encoded by 6 four-bit groups divided by a single bit with the value 1, illustrated by a slash. The encoding used by the ADAT protocol is the NRZI encoding, "inverted non return to zero", where l 's cause a signal change, i.e. low to high or high to low, and O's cause no change regardless of the current state. The ADAT protocol thus causes the signal to contain at least one change for each 5 bits (4 bits of data). Subsequent to the data groups of all eight audio channels is encoded a 10 bit long field 21 of O's followed by a single 1, which thus cause the line to be static, either high or low, for exactly 10 bits, and then change again. Finally, the frame contains a 4-bit group 23 of auxiliary data followed by a single 1. By this protocol each frame contains one, and only one, field of exactly ten O's, i.e. no changes, by which the receivers may synchronize to the stream.

Known receivers for digital serial data streams utilizes conventional phase locked loop (PLL) technology for synchronizing to the frame indicators described above.

This typically includes using a PLL to lock to the frame rate, and establish a data sampling clock by stepping up the frame rate by, e.g., 64 or 192*64 in the event of an AES/EBU protocol with 64 bits per frame or 192 frames per group, or, e.g., 256 in the event of an ADAT protocol with 256 bits per frame. Problems connected with this conventional method include, among others, that the locking is typically based on basically analogue techniques, and even extremely small deficiencies of the frame locking cause unacceptable jitter to the sampling rate, which targets time fields of only, e.g., 1/256 of a frame period.

Furthermore, when more serial data stream receivers are implemented in a single device, they conventionally requires PLL and locking circuitry for each receiver, and/or require the incoming streams to be in complete synchrony and share inter- symbol jitter. As PLL's are relatively expensive and cumbersome components, particularly in on-chip implementations, the need for several PLL's is a problem in cost-efficient, state-of-the-art, on-chip digital serial data stream receivers.

An object of the invention is therefore to provide an alternative serial data stream receiver which facilitates more precise and reliable sampling of data bits.

A further object of the invention is to provide a way for several serial data stream receivers to share logic, in particular a single PLL, and thereby improve the cost- efficiency of providing several such receivers in a single device.

Summary of the invention

The invention relates to a method of extracting data from an input serial data stream, comprising the steps of

over-sampling said input serial data stream by establishing at least two samples per time window of said input serial data stream, evaluating said established samples to determine at least one time window representative sample per time window of said input serial data stream to provide as part of an output serial data stream.

According to the present invention, an extremely stable receiver for serial data streams, in particular serial audio data streams, e.g. ADAT, S/PDIF or AES/EBU, etc., is provided. It facilitates ultra efficient implementation where several receivers may be implemented in a single device with only very little extra logic required per instance. Due to the efficient implementation, the receiver or several receivers may be implemented on-chip, e.g. in field programmable gate arrays FPGA or digital signal processors DSP, e.g. dedicated audio DSP's. Most of the receiver circuitry, except for the actual sampling of the physical data stream, may even be implemented by software.

A receiver according to a preferred embodiment of the present invention is more cost-efficient than conventional serial data stream receivers, while being more robust and extremely reliable. It enables multiple receivers to share logic, without requiring or assuming that the multiple input streams are in phase or share intersymbol jitter. One major advantage of the method of the present invention is the excellent jitter tolerance, which is significantly superior to conventional receivers, and which allows reliable data extraction from even very distorted input streams

Time window is in the context of the present invention understood to designate a bit period, also referred to as unit interval UI, e.g. approximately 80 ns corresponding to a bit rate of approximately 12 MHz in an incoming ADAT signal to be read and reestablished. The over-sampling rate in this connection may be, e.g. 48 MHz if an over sampling degree of 4 times is desired, hence causing establishment of 4 samples per ADAT bit or unit interval. It is noted that the position and length of the bit periods in the incoming signal is in principle not known or at least not absolute at the receiving end, e.g. due to jitter and amplitude noise etc., but pre-estimated. Pre-estimation may be established according to a specific knowledge of the bit-rate of the incoming signal, e.g. from knowing the frame rate, and the number of bits per frame. Alternatively this pre-establishment may be established by an initial or runtime analysing of the signal, e.g. based on detection of frame indicators or smallest detectable time windows.

An input serial data stream according to the present invention may be any stream of data representing symbols or bits. It may comprise data in any physical or virtual encoding, and is typically electrically represented signals of various origin, e.g. optically or electro magnetically represented signals converted into electrically represented signals or simply mere electrically represented signals, but may also comprise, e.g., an actual optical data stream, whereby the establishment of samples comprises utilizing an optical detector means. In preferred embodiments, the input serial data stream represents audio data and comprises, e.g., ADAT, AES/EBU or S/PDIF encoded audio. The present invention may however be used for receiving any serial data stream of any protocol. In this connection it should be noted that a parallel data stream may be seen as several serial data streams, e.g. 8 serial data streams in synchrony for one 8-bit parallel bus, and may certainly be picked up and reconstructed by a method according to the present invention, e.g. by providing 8 parallel receivers according to the present invention, and serve their outputs in synchrony on a parallel data bus.

The evaluation of the samples may according to the present invention comprise a short-sighted evaluation of just a few consecutive samples as in a preferred embodiment of the invention, e.g. only evaluating a sample on the basis of information that is approximately one time window old, e.g. information about the sample that was considered most optimal in the previous time window. In alternative embodiments, the evaluation may be based on a larger statistical basis, and comprise more or less statistical processing. In such embodiments, e.g. information about the estimated or determined quality of samples of several previous time windows may be used as basis for determining a quality distribution for samples of the generic time window, and on this basis estimate which samples are most optimal to use in the subsequent time window. It should be noted that any statistical or simpler evaluation method that serves the purpose of estimating or determining the quality of the samples and thereby suggest or determine the most optimal sample to use for the reconstructed data stream is within the scope of the present invention. It should further be noted that the evaluation need not be performed continuously or for every single sample or time window. According to an embodiment of the present invention, the evaluation results in a reliability and stability measure, i.e. a measure of the quality of the input stream, and thereby a measure of the probability of the current selection algorithm staying correct for a number of succeeding time windows in the future. Such quality and probability measure may be used for determining how often the evaluation should be performed and the selection of time window representing samples be updated. Hence, when the incoming data stream is substantially free from jitter and other noise, phase and frequency drift, and the sample clock is completely frequency locked to the incoming stream, the evaluation may be performed rather infrequently, with several frames between evaluations, or performed continuously but based on only a part of the total samples, e.g. evenly distributed over time. The quality and probability information may furthermore be provided for other purposes, e.g. provided to subsequent processing stages as auxiliary information about the data stream, or to a user for optimizing the transmission means, etc.

According to the present invention, the purpose of the evaluation is to determine time window representing samples to provide as an output stream, i.e. samples that reliably and actually represents the real data intended to be represented within the particular time window, i.e. the value of the bit encoded in the time window. In a preferred embodiment this comprises determining one reliable sample for each time window, and outputting them consecutively on the output. Thereby is provided an advantageous and intelligent method of extracting data, as the output samples are not only established on the basis of a frame-locked sample clock as in known receivers, but are furthermore intelligently and adaptively evaluated for quality and reliability, whereby the output is established from only samples that represent real information. The method of the present invention is thus superior to known oversampling-and- averaging methods, as the traditional averaging methods will actually work to the worse for certain kinds of noise and/or above certain degrees of noise and distortion. The present invention facilitates intelligent selection of only reliable samples even in situations where all but a few of the over-sampled samples are garbage. It should be noted that whenever averaging is mentioned in the scope of the present invention, it does not primarily refer to simple averaging of consecutive, over-sampled samples within one time window, but averaging of the statistical basis over preferably far longer time than one time window.

An output serial data stream is in preferred embodiments a reconstructed data stream corresponding to the input serial data stream, i.e. a stream with the same data, rate and encoding as the input serial data stream, just preferably comprising less jitter and other noise, and being in synchrony with a clock in the receiver system. In alternative embodiments within the scope of the present invention, the output serial data stream may however comprise data established on the basis of data in the input serial data stream, of different rate and encoded differently than the input stream. Hence, the receiver may receive an S/PDIF input serial data stream, and establish an ADAT serial data stream that comprises the same audio data as the S/PDIF input serial data stream, but with different symbol rate and encoding. Evidently any conversion between formats of the input and output streams is within the scope of the present invention. The output serial data stream may be represented electrically, optically, electro-magnetically or any other way suitable for the particular protocol used and the relevant needs, in either digital or analogue encodings. In a preferred embodiment the established output serial data stream is provided directly to subsequent processing means, e.g. a decoder for establishing, e.g., a PCM signal from the encoded serial signal, or an audio amplifier. Such subsequent processing means are preferably implemented on the same chip device, and the transmission thus comprising only internal conducting means. Obviously, the output serial data stream may within the scope of the present invention also be transmitted through any other means to any kind of subsequent processing means. In a preferred embodiment of the invention, the output serial data stream is actually not provided for transmission, but is internally immediately decoded to a parallel data stream such as a pulse code modulated signal (PCM-signal) or other appropriate format that is ready for processing, and provided on an internal data bus.

When said input serial data stream comprises physically encoded data representations, an advantageous embodiment of the present invention is obtained.

When said input serial data stream comprises time discrete data representing symbols, an advantageous embodiment of the present invention is obtained.

When said input serial data stream comprises audio representing data, an advantageous embodiment of the present invention is obtained.

When said input serial data stream comprises an ADAT stream, an advantageous embodiment of the present invention is obtained.

When said input serial data stream is transmitted at least partly by an optical interface, an advantageous embodiment of the present invention is obtained.

When said method is carried out by a processing means, an advantageous embodiment of the present invention is obtained.

When said method is carried out by a digital signal processor, an advantageous embodiment of the present invention is obtained.

When said over-sampling is performed in accordance with an over-sampling clock, an advantageous embodiment of the present invention is obtained.

When said over-sampling clock is frequency-locked to said input serial data stream, an advantageous embodiment of the present invention is obtained.

When said over-sampling clock is a substantially jitter- free clock, an advantageous embodiment of the present invention is obtained. When said over-sampling clock is an audio clock, an advantageous embodiment of the present invention is obtained.

When said over-sampling establishes at least four samples per time window of said input serial data stream, an advantageous embodiment of the present invention is obtained.

When said time-window of said input serial data stream corresponds to a bit period of said input serial data stream, an advantageous embodiment of the present invention is obtained.

When the value of said time window representative sample corresponds to the value intentionally represented by said time window, an advantageous embodiment of the present invention is obtained.

When said output serial data stream comprises a reconstruction of said input serial data stream, an advantageous embodiment of the present invention is obtained.

When said determining at least one time window representative sample per time window comprises storing a sample offset number, an advantageous embodiment of the present invention is obtained.

Sample offset number is also referred to as sample index in the present description, and represents the sample number within each time window that is assumed to most optimally represent the bit value.

When said sample offset number is used to select samples to be provided as part of said output serial data stream, an advantageous embodiment of the present invention is obtained. When said evaluating said established samples comprises determining the reliability of said samples, an advantageous embodiment of the present invention is obtained.

When said evaluating said established samples comprises determining the probability of said samples to reliably represent the value of the corresponding bits, an advantageous embodiment of the present invention is obtained.

When said probability of the value reliability for a sample is determined on the basis of at least one previous sample by means of sample value comparison, an advantageous embodiment of the present invention is obtained.

When said probability of the value reliability for a sample is determined on the basis of the previous sample by means of sample value comparison, an advantageous embodiment of the present invention is obtained.

When said probability of the value reliability for a sample is determined on historical information of previous samples, an advantageous embodiment of the present invention is obtained.

When said historical information comprises a distribution of number of value changes over different sample offset numbers, an advantageous embodiment of the present invention is obtained.

When said over-sampling comprises over-sampling by approximately a pre- determined multiple of the time window rate of said input serial data stream, evaluating said established samples comprises counting the samples with a counter that wraps for each said pre-determined multiple, storing a sample offset number of said time window representing sample in a register, each time the value of said counter equals said sample offset number of said register providing the current sample to said output serial data stream, an advantageous embodiment of the present invention is obtained. When said evaluating said established samples comprises counting the samples with a counter that wraps for each said pre-determined multiple, storing a sample offset number of said time window representing sample in a register, each time the value of said counter equals said sample offset number of said register comparing the current sample with the previous sample and if a sample value change is detected increment the sample offset number of said register, an advantageous embodiment of the present invention is obtained.

When said evaluation is performed on a run-time basis, an advantageous embodiment of the present invention is obtained.

The present invention further relates to a method of sampling data, comprising the steps of

establishing samples by measuring said data frequently,

establishing an output stream of data-representing samples by evaluating said samples according to a quality scale.

According to the present invention an intelligent and adaptive sampling method is provided, that performs evaluation of the samples to only provide samples that reliably represents the data. The method of the present invention thus differs from known methods in that it does not inevitably provide all samples at the output, and neither does it merely provide automatic averages of a number of samples. Instead the method of the present invention evaluates samples to determine what samples comprise real information, and which comprise only garbage.

A quality scale according to the present invention may be any information or condition that can be used to determine wanted samples from unwanted samples, i.e. typically sample that comprise information or highly reliable information from samples that comprise garbage or less reliable information. The quality scale may thus, according to a preferred embodiment of the present invention, provide for a selection of one sample out of all samples within a determined or pre-determined time window. The sample to select is in a preferred embodiment the sample of the time window samples that most reliably represents the data at the particular time. This may, in a preferred embodiment, be one sample out of every, e.g., approximately four samples. The evaluation and quality scale may be based on a statistical basis comprising information about the data and previous samples. The amount of statistical data, i.e. the time duration on which the evaluation is based, may be determined on the basis of the type and purity of the data, and the desired degree of reliability of the output. In a simple preferred embodiment the evaluation is based only a few samples, e.g. representing one or two time windows, whereas, in a more advanced preferred embodiment, the evaluation is based on samples of several time windows.

When said evaluating said samples is performed on a one -by-one basis, an advantageous embodiment of the present invention is obtained.

When said measuring of said data frequently comprises measuring the level of said data by an over-sampling method, an advantageous embodiment of the present invention is obtained.

According to an embodiment of the present invention, the data are measured, i.e. sampled, e.g. by a D-fiip-flop, at a rate that is at least twice as high as the frequency content of the data. It is noted that by frequency content of the data is for digitally represented data referred to the bit rate or symbol rate.

When said method comprises a method of extracting data from an input serial data stream according to any of the above, an advantageous embodiment of the present invention is obtained.

The present invention further relates to a method of reconstructing an input serial data stream, said method comprising receiving said input serial data stream by at least two different serial data stream receivers simultaneously and evaluating quality information provided by said serial data stream receivers to determine one of said different serial data stream receivers to provide an output data stream by reconstructing said input serial data stream.

According to the present invention an advantageous method of determining the optimal settings for a serial data stream receiver, e.g. an ADAT receiver, is provided. The method comprises using several, differently implemented receivers to read the incoming stream and determine the quality of the read data. By comparing the determined quality information from the different receivers, it can be determined which of the receivers read the incoming stream most correctly, and should thus be used for providing the output stream, i.e. a reconstruction of the input stream.

The differences between the at least two receivers may comprise different filters, different sampling methods, different bit extraction methods, different sample clocks, or any other differences that may cause one receiver implementation to read a data stream more reliably than another. In a preferred embodiment, the differences comprise different cable-length compensating filters, i.e. cable equalizers, e.g. one receiver with a 10 meter compensating filter, one receiver with a 30 meter compensating filter, and one receiver with a 50 meter compensating filter. If the incoming stream is transmitted by, e.g., a 30 meter optical cable, the receiver with the 30 meter compensating filter will provide the most reliable reconstruction of the input stream. By means of the present invention this can be determined by having the receivers determine and provide information about the quality, e.g. reliability, of the reconstruction. In a preferred embodiment, the receivers determine the quality information by using an oversampling method, and evaluating which and how many of the samples that represent the real data.

When the difference of said at least two different serial data stream receivers comprises differently implemented cable equalizers, an advantageous embodiment of the present invention is obtained. When the difference of said at least two different serial data stream receivers comprises differently implemented data extraction methods, an advantageous embodiment of the present invention is obtained.

When said quality information represents the estimated ability to reconstruct said input serial data stream, an advantageous embodiment of the present invention is obtained.

When said quality information is based on estimated reliability of individual samples established by an over-sampling method within each of said receivers, an advantageous embodiment of the present invention is obtained.

When said receivers implements a method of extracting data from an input serial data stream according to any of the above, an advantageous embodiment of the present invention is obtained.

When said receivers implements a method of sampling data according to any of the above, an advantageous embodiment of the present invention is obtained.

The present invention further relates to a method of establishing a clock that is phase-locked to an incoming stream, comprising establishing a stream of samples by over-sampling said incoming stream, evaluating said stream of samples to determine phase information of said incoming stream, selecting a part of said samples according to said determined phase information, and establishing said clock by providing said selected samples.

According to the invention, intelligent phase locking to an incoming stream, e.g. a serial data stream, e.g. an ADAT stream, may be advantageously performed by over- sampling the incoming stream, and adaptively selecting samples that represents the phase and output them as an output clock. In a preferred embodiment the amount of samples to output as output clock, e.g. 1/4 of all samples, corresponds to the degree of over-sampling, e.g. 4 times. In a preferred embodiment, the samples that are considered best representing the phase are the samples that most reliably represent the incoming stream value between edges.

When said evaluation comprises run-time evaluation, an advantageous embodiment of the present invention is obtained.

When said method is adaptive, an advantageous embodiment of the present invention is obtained.

When said over-sampling is based on an over-sampling clock which is frequency locked to said incoming stream, an advantageous embodiment of the present invention is obtained.

When said over-sampling is based on a fixed over-sampling clock, an advantageous embodiment of the present invention is obtained.

When said method comprises a method of sampling data according to any of the above, an advantageous embodiment of the present invention is obtained.

When said receivers implements a method of reconstructing an input serial data stream according to any of the above, an advantageous embodiment of the present invention is obtained.

The present invention further relates to a serial data stream receiver R; Rl, R2, Rn comprising a sample means SM; SMl, SM2, SMn for sampling a serial data stream IS; ISl, IS2, ISn according to an over-sample clock OSC and providing a sampled stream SSl, SS2, SSn, and a bit extractor BEl, BE2, BEn for selecting samples from said sampled stream to provide as an output stream OS; OSl, OS2, OSn. When said over-sample clock is established by means of a frame sync means FMS, an advantageous embodiment of the present invention is obtained.

When said frame sync means establishes said over-sample clock in the basis of said serial data stream, an advantageous embodiment of the present invention is obtained.

When said over-sample clock is frequency locked to said serial data stream, an advantageous embodiment of the present invention is obtained.

When said bit-extractor comprises an edge detector ED, a counter CNT and a register REG, an advantageous embodiment of the present invention is obtained.

When said output stream comprises a bit rate corresponding to said serial data stream, an advantageous embodiment of the present invention is obtained.

When said over-sample clock comprises a clock rate corresponding to at least twice the bit rate of said serial data stream, preferably four times said bit rate, an advantageous embodiment of the present invention is obtained.

When said bit extractor comprises memory, an advantageous embodiment of the present invention is obtained.

When said bit extractor comprises means for selecting samples according to statistical methods, an advantageous embodiment of the present invention is obtained.

When said serial data stream comprises physically encoded data representations, an advantageous embodiment of the present invention is obtained.

When said serial data stream comprises time discrete data representing symbols, an advantageous embodiment of the present invention is obtained. When said serial data stream comprises audio representing data, an advantageous embodiment of the present invention is obtained.

When said serial data stream comprises an ADAT stream, an advantageous embodiment of the present invention is obtained.

When said serial data stream is transmitted at least partly by an optical interface, an advantageous embodiment of the present invention is obtained.

When said serial data stream receiver comprises processing means, an advantageous embodiment of the present invention is obtained.

When said serial data stream receiver comprises a digital signal processor, an advantageous embodiment of the present invention is obtained.

When said over-sample clock is a substantially jitter- free clock, an advantageous embodiment of the present invention is obtained.

When said over-sample clock is an audio clock, an advantageous embodiment of the present invention is obtained.

When said over-sample clock is established by means of a phase locked loop, an advantageous embodiment of the present invention is obtained.

When said sampling according to said over-sample clock establishes at least four samples per time window of said serial data stream, an advantageous embodiment of the present invention is obtained.

When said time-window of said serial data stream corresponds to a bit period of said serial data stream, an advantageous embodiment of the present invention is obtained. When the values of said selected samples correspond to the values intentionally represented by said time windows, an advantageous embodiment of the present invention is obtained.

When said output stream comprises a reconstruction of said serial data stream, an advantageous embodiment of the present invention is obtained.

When said bit-extractor stores a sample offset number, an advantageous embodiment of the present invention is obtained.

When said sample offset number is used to select samples to be provided as part of said output stream, an advantageous embodiment of the present invention is obtained.

When said bit extractor comprises means for determining the reliability of the samples of said sampled stream, an advantageous embodiment of the present invention is obtained.

When said bit extractor comprises means for determining the probability of the samples of said sampled stream to reliably represent the value of the corresponding bits, an advantageous embodiment of the present invention is obtained.

When said probability of the value reliability for a sample is determined on the basis of at least one previous sample by means of sample value comparison, an advantageous embodiment of the present invention is obtained. When said probability of the value reliability for a sample is determined on the basis of the previous sample by means of sample value comparison, an advantageous embodiment of the present invention is obtained.

When said serial data stream receiver comprises means for carrying out a method of extracting data from an input serial data stream according to any of the above, an advantageous embodiment of the present invention is obtained.

When said serial data stream receiver comprises means for carrying out a method of sampling data according to any of the above, an advantageous embodiment of the present invention is obtained.

When said serial data stream receiver comprises means for carrying out a method of reconstructing an input serial data stream according to any of the above, an advantageous embodiment of the present invention is obtained.

When said serial data stream receiver comprises means for carrying out a method of establishing a clock that is phase-locked to an incoming stream according to any of the above, an advantageous embodiment of the present invention is obtained.

The present invention further relates to a data sampling device comprising a sampling means, an evaluation means and an output means, wherein said sampling means establishes samples of said data and said evaluation means comprises means for determining a quality scale and selecting according to said quality scale a part of said samples and providing them to said output means.

When said data sampling device comprises a serial data stream receiver according to any of the above, an advantageous embodiment of the present invention is obtained.

When said data sampling device comprises means for carrying out a method of extracting data from an input serial data stream according to any of the above, an advantageous embodiment of the present invention is obtained.

When said data sampling device comprises means for carrying out a method of sampling data according to any of the above, an advantageous embodiment of the present invention is obtained.

When said data sampling device comprises means for carrying out a method of reconstructing an input serial data stream according to any of the above, an advantageous embodiment of the present invention is obtained.

When said data sampling device comprises means for carrying out a method of establishing a clock that is phase-locked to an incoming stream according to any of the above, an advantageous embodiment of the present invention is obtained.

The present invention further relates to a serial data stream receiver comprising at least two differently implemented receivers comprising means for determining a quality information regarding their performance, an evaluation means comprising means for evaluating said receivers on the basis of said quality information and determining one of said receivers to provide a reconstruction of said serial data stream to an output means.

When the difference of said at least two differently implemented receivers comprises differently implemented cable equalizers. When the difference of said at least two differently implemented receivers comprises differently implemented data extraction methods.

When said quality information represents the estimated ability to reconstruct said input serial data stream.

When said quality information is based on estimated reliability of individual samples established by an over-sampling method within each of said receivers.

When at least one of said differently implemented receivers comprises a serial data stream receiver according to any of the above, an advantageous embodiment of the present invention is obtained.

When at least one of said differently implemented receivers comprises a data sampling device according to any of the above, an advantageous embodiment of the present invention is obtained.

When at least one of said differently implemented receivers comprises means for carrying out a method of extracting data from an input serial data stream according to any of the above, an advantageous embodiment of the present invention is obtained.

When at least one of said differently implemented receivers comprises means for carrying out a method of sampling data according to any of the above, an advantageous embodiment of the present invention is obtained.

When at least one of said differently implemented receivers comprises means for carrying out a method of reconstructing an input serial data stream according to any of the above, an advantageous embodiment of the present invention is obtained.

When at least one of said differently implemented receivers comprises means for carrying out a method of establishing a clock that is phase-locked to an incoming stream according to any of the above, an advantageous embodiment of the present invention is obtained.

The present invention further relates to a processing means for carrying out a method of extracting data from an input serial data stream according to any of the above.

The present invention further relates to a processing means for carrying out a method of sampling data according to any of the above.

The present invention further relates to a processing means for carrying out a method of reconstructing an input serial data stream according to any of the above.

The present invention further relates to a processing means for carrying out a method of establishing a clock that is phase-locked to an incoming stream according to any of the above.

When said processing means comprises a microchip, an advantageous embodiment of the present invention is obtained.

When said processing means comprises a digital signal processor, an advantageous embodiment of the present invention is obtained.

According to the invention processing means may comprise central processing units CPU's, digital signal processors DSP's, field programmable gate arrays FPGA's, or any other processing means suitable for carrying out the above-described methods. In a preferred embodiment, the processing means comprises a dedicated audio DSP.

The present invention further relates to a data carrier storing instructions that cause a method according to any of the above to be carried out when performed by a processing means. According to the invention instructions or commands, e.g. computer instructions, DSP instructions, FPGA programming data, etc., may be stored by a suitable data carrier, e.g. a CD-ROM, a flash memory, random access memory, etc., and loaded into a processing means, e.g. a CPU, a DSP, a microcontroller, an FPGA, etc.

The drawings

The invention will in the following be described with reference to the drawings where

figure IA illustrates the AES/EBU digital audio serial data protocol, figure IB illustrates the ADAT digital audio serial data protocol, figure 2A illustrates an example of a data stream signal, figure 2B illustrates the problem with amplitude noise, figure 2C illustrates the problem with jitter and amplitude noise, figure 3 illustrates a principle of an embodiment of the present invention, figure 4 illustrates the working of an embodiment of the present invention on a per sample basis, figure 5 illustrates an embodiment of the present invention providing multiple data stream receivers, figure 6 illustrates a frame sync means according to an embodiment of the present invention, figure 7 illustrates a receiver according to an embodiment of the present invention, and figure 8 illustrates an embodiment of the present invention providing multiple receivers with different cable equalizers.

Detailed description

In order to illustrate a problem connected with extraction of data from digital data streams, figures 2A - 2C are provided. Figure 2A illustrates 6 bits of an arbitrary square wave digital signal that has suffered from some degree of deformation, e.g. due to a non-ideal digital-to-analogue driver or converter, low-pass filtering by transmission through wires, asymmetry of an optical component in the transmission path, etc. In the example, the signal value is high in bit no. 0, low in bit no. 1, high in bits 2 and 3, and low in bits 4 and 5. Due to the high degree of deformation, the signal value is actually undefined for a relatively long period between each bit, before it rests at a well-defined high or low level. This makes it crucial to read, i.e. sample, the bits at the time where they are well-defined, i.e. in the middle of each bit, indicated by the dashed vertical lines. At those times, the signal amplitude is farthest away from the undefined amplitude centre line, the dashed horizontal line.

When looking at one bit in principle, not knowing its actual value, it must be assumed that it can look like any of the possibilities illustrated in figure 2B, where one bit x is shown by combining the possibilities illustrated in figure 2A above each other. This makes it even clearer that in order to sample an arbitrary bit with an unknown value reliably, it is important to sample it in the middle of the bit period where the amplitude is as well-defined as possible.

Real-world signals, however, not only suffers from deformation to the square wave properties, but also from jitter. Jitter has to do with the transition between bits being displaced along the time axis, thereby causing the actual start and end of a bit to become undefined, and may occur due to imperfect clock generators, inaccurate oscillators, quantization errors, etc. Also the transmission line cause intersymbol jitter, which actually dominates over the clock jitter in most systems. A possible result of these phenomenons applied to the generic bit of figure 2B is illustrated in figure 2C. As shown, the start and end of the unknown bit is undefined, but may be expected to be approximately at certain times according to the rate and phase of the signal. The time wherein a bit is expected, or from another point of view, the length of the bit, may also within the present invention be referred to as time window, bit period or unit interval UI. Together, the amplitude error and the jitter, i.e. errors that appear vertically and horizontally when illustrated as in figure 2C, cause the illustration to look like an eye, where the optimal time that a sampling may cause a reliable and well-defined result is in the time centre of the so-called eye opening. It is noted that due to the unpredictability of the jitter, and to the often asymmetric amplitude error, the time centre of the eye opening is not necessarily in the time centre of the bit period as indicated by the short vertical lines in the truly symmetric illustration of figure 2C. Hence, the best time to sample the bits of a serial data stream is somewhat unpredictable and may vary over time, or from bit to bit.

As explained above, conventional data stream receivers lock to the frame rate of the incoming stream and establish on that basis a sample clock that corresponds to the number of bits per frame. The phase of the sample clock is typically determined by a leading or trailing edge of the unique frame indicator or some other particularity of the signal. As the sample clock is however, e.g., 256 times as fast as occurrences of the frame indicator and thereby the phase determining edge, even a small error on the phase will cause a significant error on the exact sample time of each bit. Together with the probable amplitude and jitter error on the data stream signal, these inaccuracies easily cause the actual sampling times of some samples to step outside the eye opening of well-defined bits and thereby cause errors in the sampled data.

In an embodiment of the present invention, the data stream is sampled at a rate that is several times higher than the bit rate of the signal, e.g. 4 times higher, which in the case of an ADAT signal is 1024 times the frame rate. Thereby each bit is sampled 4 consecutive times and the samples are analysed in order to find the sample(s) that was taken within the eye opening where the bit was best defined. The sample that is chosen as the most reliable one is forwarded as the bit value, whereby is established a sampled data stream of the appropriate bit rate with all well-defined and reliable bits. Figure 3 illustrates a principle of the present invention. It illustrates the generic, arbitrary, unknown bit x, with the possible and probable jitter and amplitude noise. Compared with figure 2C, the noise is illustrated somewhat asymmetric for the sake of explanation and clarity. The single bit, which has no well-defined start or end but a known duration, time window, bit period, unit interval, being defined as, e.g. in the ADAT case, 256 times the frame rate, is according to the present invention sampled 4 times by samples x₀, X₁, x₂ and x₃. As seen from the illustration, only same x₂ is well-defined, marked by "d", whereas samples x₀, X₁ and x₃ are undefined, marked by "u".

Evidently, whereas the above serves as illustration, it is not possible to determine from a single bit of the data stream, as such bit would have not more than two transitions, possibly only one or none at all, and because it would be impossible from one bit to know which of the samples resemble the bit value most reliably.

According to an embodiment of the invention, the samples for several bits are instead compared in order to determine the reliability of the individual samples. This is illustrated in figure 4, which shows 12 bits, 00, 01, 02, ..., 12 of a digital signal suffering from deformation and jitter. Due to clarity of the explanation, the signal is encoded by the simplest possible encoding where O's have the signal value low, and l 's have the signal value high. The intended values of the 12 bits are 1-0-1-0, 1-0-0- 1, 0-1-0-1. This is, however, not unproblematic to determine, as the edges of the bits are very inconsistently placed due to jitter and the best times for sampling therefore somewhat undefined. According to an embodiment of the present invention, the signal of figure 4 is sampled at a rate 4 times as high as the bit rate, where by the timeslot for each bit is sampled 4 times, indicated by the sample numbers 43 for each bit. In the example of figure 4 the actual samples are in the centre of each sample period, as indicated by the dots on the signal curve. Evidently any kind of sample technique is within the scope of the present invention, e.g. sampling at the front or back of the sample period, calculating a mean value during the sample period, etc. The value of each sample is indicated by 0 or 1 in the row referred to as 41. This value is determined by the sample dot being above or below the amplitude middle value. With only this information, it is still impossible to reliably tell the actual intended value of each bit. For example, the sampling of bit 04 has resulted in two O's and two l 's. From this alone, there is a risk of 50% of getting the actual bit value wrong. Therefore, according to the present invention, further information is established in that also sample value changes are identified. In this example, each sample value is compared with the previous value in order to determine whether or not a change has occurred. Of course, any way of establishing information on the changes of the sample values may be used in various embodiments of the present invention and are thus within the scope thereof. Also any method of performing this comparison in a circuit is within the scope of the present invention, e.g. the use of adders or subtractors for calculating if a difference occurred, the use of comparators, AND-gates or other appropriate logic, etc. The result of the comparison for each sample is illustrated in the row referred to as 42, where s indicates stability, i.e. no change from the previous sample, and c indicates a change from the previous sample. The identification of the changes provides information about the reliability of a certain sample number. Hence, if sample number 0 is changed for each bit, it may not be the most reliable sample to read from, as the position of the actual change, i.e. the edge of the square wave, can be anywhere from between the centre of the sample number 3 of the previous bit to the centre of sample number 0, and furthermore even include edges that were moved into the time slot of sample number 0 because of jitter. Hence, by analysing the changes, information that actually resembles the principle illustration of figure 3 may be provided. An analysis of the changes within the 12 bits of figure 4 reveals that 5 changes have occurred to sample number 0, 2 changes has occurred to sample number 1, no changes have occurred to sample number 2 and 4 changes have occurred to sample number 3. According to this, sample number 2 may be determined as the most reliable sample to read the data from, and a stream of all the number 2 samples thus provides the original data stream, i.e. 1-0-1-0, 1-0-0-1, 0-1-0-1.

Of course the signal example of figure 4 would look different in a different encoding, e.g. the NRZI encoding used with the ADAT protocol, but the principle of the present invention that over-sampling and analysis of the different samples over time provides information about the most reliable sample time for each bit, holds for any signal encoding format, and such are therefore within the scope of the present invention.

In the above-described example, 4 samples are made for each bit in the data stream. Of course any number of samples per bit is within the scope of the present invention. For very unreliable signals or for certain data stream protocols, the degree of over- sampling, i.e. the number of samples per symbol in the data stream, may have to be higher, e.g. 6 times, 8 times or 16 times. For very reliable signals, an embodiment of the present invention with only 2 samples per bit may suffice. Hence, any degree of over-sampling is within the scope of the present invention.

Also the amount of samples to analyse in order to reach a reliable result regarding which sample to use for data extraction may vary for different signal types, environments, etc., and with the degree of over-sampling. In the example of figure 4, the statistical basis is made up by 12 bits, i.e. 48 samples, which apparently gives a reliable result for that case. Obviously, the larger the amount of samples to analyse, the more reliable the result, but this is only true as long as the sample rate is exactly the desired multiple of the signal bit rate, as long as the sample rate is not changing at all, and as long as the bit rate is not changing at all. In real systems, however, none of these conditions are fulfilled at all times, and therefore the eye opening of the incoming data stream will drift a little relative to the sample clock signal, which again means that by time, the best sample to use for each bit may change. This fact requires the memory of the sample analysis to be short enough to allow such a change to be observed and acted upon. In a system with fairly good clocks and locking capabilities, a preferred length of the analysis memory is samples from 12 bits of the serial data stream, but the most optimal length of memory in a certain implementation should be determined on the basis of the actual components, signal types and capabilities of the processing means, i.e. over-sampling and analysis capabilities. It is noted that the analysis according to the present invention may comprise a simple finite histogram function as used in the above example, or it may utilize more advanced statistical methods such as recursive or finite filters, e.g. running average filters, etc. In an alternative embodiment, a normal distribution or other distribution representing the amount of changes in each sample of a generic bit is derived from the samples, and the sample closest to the centre of the normal distribution is considered the best sample to use. By continuously or frequently updating the distribution, any movement of the distribution relative to the expected time window of the bits may be detected and tracked. Furthermore, some implementations may benefit from differentiating the accumulated amount of changes in each sample slot in order to predict the speed and direction of the phase drifting. All such statistical and analysis methods for improving the information about the most optimal data extraction times are within the scope of the present invention.

In a preferred embodiment of the invention, the analysis of the over-sampled stream is performed in a somewhat simpler and more straightforward way, by just considering the present sample, and whether or not a change occurred from the previous to the present sample. Hence, having again as example 4 samples per bit, a first sample slot is at initialisation considered the most optimal sample, i.e. the sample that never contains a change from the previous sample. Using the input stream of figure 4 as example, the sample indexed 0 in row 43 is considered the most optimal sample to use out of the 4 possible samples, until a change is detected from sample 3 to sample 0. Such change is detected between sample 3 of bit 00 and sample 0 of bit 01, and sample 0 is therefore discarded as being the optimal sample. Instead the next sample is assumed as being optimal for the time being, i.e. the sample indexed 1. Next time around, no change is detected from sample 0 to sample 1 in bit 02 and still not in bit 03. However, when comparing sample 1 with sample 0 in bit 04 a change is detected, and also sample 1 is discarded as the best sample. Instead, sample 2 is now assumed as being optimal. For the rest of the bits shown in figure 4, no changes occur from sample 1 to sample 2, and at least for as long as the sample indexed 2 is actually the most optimal one to use, which corresponds with the result obtained by the more statistical methods described above. As long as no change is detected from the previous sample to the assumed optimal sample, that sample is actually within the eye opening of the incoming stream. If for some reason, e.g. especially heavy jitter, drift of phase or frequency, etc., a change should occur in the optimal sample and therefore cause the next sample to be considered optimal, the method will quickly, within a few frames, find the optimal sample again. This preferred embodiment is very simple to implement and finds the optimal sample quickly and locks strongly to it. However, if the incoming stream is very noisy, or the degree of over-sampling is too low, so that a change occurs in all samples from time to time, the present embodiment may regularly loose the grip and need to search for the optimal sample again. In such conditions, an embodiment with memory and averaging properties as described above may be more reliable. It is noted, however, that experiments have shown that even the preferred, simple embodiment of the present invention is advantageous over known ADAT receivers. In a preferred embodiment, a high-quality PLL of the frame sync means FSM that generates a over- sample clock that is tightly frequency locked, but not necessarily phase locked, to the incoming stream, facilitates a relative low degree of oversampling, e.g. 4 times, and still provides a very advantageous serial data stream receiver.

The adaptability of the system to always find the best data extraction time within each bit's time slot may in a further embodiment of the present invention be used to facilitate the use of a sample clock that is only frequency locked, but not phase locked, to the incoming serial data stream. As the sampling is performed at a rate that is a fixed multiple of the bit rate, e.g. 4 times the bit rate, and as the system finds the best sampling time within each 4 samples, it is not really important for the system to phase lock the sample rate clock to the data signal. The system according to an embodiment of the present invention will automatically choose the best sample time and does not rely on knowing or assuming the positions of the pulse edges in the data signal in order to sample in the middle thereof, or any other assumptions made by conventional receivers.

In yet a further embodiment of the present invention is even facilitated the use of a sample clock that is not even perfectly frequency locked to the incoming serial data stream. A sample rate that is relatively close to, but not exactly an integer multiple of the bit rate of the data stream, e.g. approximately 8, 16 or 32 times the bit rate, is facilitated with this embodiment of the present invention. This is possible due to the system being able to adapt to relative drifting between the data signal phase and the sample clock phase. A non-integer number of samples for each data stream bit will cause drifting, but not different to any other drifting caused by non-perfect clocks and locking, which the system can handle. The only requirement is that the degree of over-sampling is determined from the expected inherent errors in the signal, i.e. amplitude errors and signal jitter, as well as the substantially known drifting caused by a non-integer number of samples per data bit. In this embodiment, the degree of over-sampling typically needs to be somewhat higher than in the simple, preferred embodiment.

This preferred embodiment of the present invention facilitates the serial data stream receiver to use a system clock that is not locked to the incoming data stream, e.g. a system clock that is used in other parts of the system, or for some other reasons may not be possible to lock to the incoming data stream. An example of such a reason is in a preferred embodiment of the present invention, where a single system comprises several serial data stream receivers. Instead of providing each receiver with a PLL for locking to each incoming stream, a single PLL may be locked to one of the streams, and the other receivers, implemented according to the present invention, may use the established sample clock, even though it is not phase locked exactly to their incoming streams.

Hence, a very preferred embodiment of the present invention, illustrated in figure 5, comprises a shared frame sync means FSM for locking to and multiplying the frame indicator rate from a master incoming serial data stream ISl and establishing an over-sample clock OSC. The frame sync means FSM is itself clocked by a system clock SC. Optionally, the frame sync means also outputs a frame rate output FR. The embodiment further comprises n receivers Rl, R2, Rn, for reading each of n incoming streams ISl, IS2, ISn, master as well as slave streams. The receivers each comprise sample means SMl, SM2, SMn for sampling the streams at the over- sample clock rate OSC and establishing sampled streams SSl, SS2, SSn, and bit extraction means BEl, BE2, BEn for determining the best samples to use in each data stream and establishing output streams OSl, OS2, OSn comprising those samples. For explanatory purposes, the rates in the different signal may, for example, be: input streams ISl-ISn with frame rates of 48 kHz and bit rates of 12 MHz, system clock SC of 48 MHz, over-sample clock OSC of 48 MHz, i.e. 4 times the bit rate and 1024 times the frame rate, sampled streams SSl-SSn of 48 MHz, and output streams OSl-OSn of 12 MHz.

Figure 6 illustrates a possible embodiment of a shared frame sync means FSM according to the present invention. All components are clocked by a system clock SC. The frame sync means FSM comprises a D flip-flop DF for sampling the input stream IS and providing a sampled input stream SIS to a pattern recognizer PR that detects the unique frame indicator of the incoming stream. In the case of an ADAT stream, the pattern recognizer may simply count the lengths of periods of non- activity to determine the frame indicator, whereas, in the case of, e.g., an AES/EBU stream, it may compare the sampled signal with the known characteristics of the frame indicator of that protocol. The pattern recognizer PR establishes a frame rate signal FR that somehow represents the detected frame indicators, e.g. by a pulse for each frame indicator, or other suitable representation. The frame rate detected in this way may typically be somewhat jittery, e.g. comprising jitter amounting to possibly 20 ns compared with bit lengths of, e.g., 80 ns in the ADAT case. The frame rate FR is used as input for a phase locked loop PLL that locks to the frame rate signal, removes the jitter, and multiplies the rate, e.g. 1024 times, in order to establish a master stream locked over-sample clock OSC to use in the receivers. The phase locked loop PLL may comprise any suitable means for the above-mentioned purpose. In a preferred embodiment, the phase locked loop comprises a dual-loop PLL comprising a numeric PLL and an analogue PLL, e.g. a PLL as disclosed in the international patent application PCT/GB2003/001441, hereby incorporated by reference. In a preferred embodiment, the PLL is shared with other components of the system, e.g. components requiring a jitter free clock for audio processing.

However, it is noted that any suitable means for detecting frame indicators and establishing a multiplied clock locked thereto is within the scope of the present invention for shared frame sync means. Furthermore, it is within the scope of the present invention to provide a frame sync means FSM for each stream and receiver, instead of the preferred embodiment providing a shared frame sync means.

A very advantageous feature of the present invention is that the PLL, and in particular its feed-back loop, is made independent of the serial stream data and sync extraction, whereby can be used the PLL which will be present anyhow in almost any digital audio system and/or the rest of the system can use the PLL of the frame sync means. This is caused by the PLL in embodiments of the present invention is merely a jitter cleaner which is forward fed from, preferably, an asynchronous Iy sync detector.

Figure 7 illustrates a preferred embodiment of a receiver R according to the present invention. It comprises a sample means SM that is clocked by the over-sample clock OSC preferably provided by a frame sync means FSM according to the present invention, but may alternatively be provided by any means for providing a clock with a rate that higher than the bit rate of the data stream. The sample means SM samples the incoming data stream IS and provides thereby a digital version of the incoming stream. In a preferred example, the sampled signal comprises approximately 4 samples per bit of the stream. The receiver R output is an output stream OS which is a reconstructed version of the input stream IS. Preferably it contains exactly the same data as the input stream, but with less amplitude and jitter noise, and in substantially complete synchrony with the over-sampling clock OSC. The bit rate of the output stream OS is in a preferred embodiment 1/4 of the over-sampling clock rate, i.e. corresponding to the input stream rate. The output stream OS is established by using approximately every fourth sample of the over-sampled input stream, e.g. by means of a D flip-flop DF that is triggered by an optimal sample selecting circuitry. The circuitry that selects the optimal samples comprises, in the present preferred embodiment, a counter CNT, a register REG, an edge detector ED and further logic for processing the data. The counter CNT counts the samples, e.g. by counting the pulses of the over-sample clock OSC. In a preferred embodiment with an over- sample degree of 4 times the bit rate, the counter CNT is preferably a 2-bit wrapping counter, thus capable of counting from 0 to 3. The register REG holds the sample index that is currently the best sample to use, and is in a preferred embodiment a 2- bit register thus capable of storing numbers from 0 to 3. The edge detector ED comprises logic that detects when a value change occurs in the input stream IS. Preferably, the edge detector compares the current sample with the previous sample, and if they are different, the edge detector goes high. The edge detector may thus comprise a D flip-flop or other delay means for storing the previous sample until a comparison with the most recent sample has been made.

In the embodiment of figure 7, the counter CNT and register REG are initialized with arbitrary values, e.g. 0. This means that the receiver initially assumes the samples indexed by the initial value, e.g. 0, are the best sample in each time window to use for each data extraction. Whenever the counter CNT and the register REG contain the same value, e.g. 0, which may be determined by a comparator means CMP, a signal is sent to the D flip-flop DF or other sample selection circuitry to provide the current sample, i.e. index 0, at the output OS. Hence, each time the counter reaches the index stored in the register, which it, in a preferred embodiment, will for every 4 samples as long as the register remains unchanged, a sample is provided at the output OS. In order to facilitate the receiver to find and keep track of the most optimal sample index, the register REG is incremented by appropriate means, each time the edge detector finds an input change in the same sample that is stored in the register as the best sample index, i.e. whenever an edge is detected and the counter value equals the register index, the register is incremented in order to try using the next sample index as best sample further on. With this receiver R according to a preferred embodiment of the present invention, the receiver will find and store in the register the best sample index to use for bit extraction within a few frames, even in worst case scenarios, according to the experiments performed.

In an embodiment for receiving, e.g., AES/EBU encoded streams, the over-sampling may preferably comprise 8 times the bit rate of the stream, as the bi-phase encoding used in such streams may changed during the bit period. According to a preferred embodiment, several receivers may be implemented together and may thus share the frame sync means FSM for establishing the over- sample clock OSC and also share the counter CNT. Each receiver should comprise its own edge detector ED and best sample register REG.

However, it is noted that any suitable means for determining the most optimal samples according to any of the above-described methods, and any suitable means for extracting the samples determined as most optimal and establishing an output stream according to those samples, is within the scope of the present invention.

Figure 8 illustrates a further embodiment of the present embodiment. It comprises several receivers Rl, R2, Rn all receiving the same input stream IS. A frame sync means FSM according to the present invention may be provided for establishing an over-sampling clock, but in alternative embodiments the over-sampling clock may be established in other ways, e.g. input from a sync-input, etc. Each receiver comprises a cable equalizer CEl, CE2, CEn. The cable equalizers are filters of any suitable kind, that compensates for the filtering, typically low-pass filtering, that has been applied to the input stream by the cables, optical cables, etc. As the deformation and low-pass filtering of the stream depends heavily on the length and quality of cabling, in such a degree that it may be impossible to interpret a received input stream with a incorrectly tuned compensation filter, i.e. cable equalizer, it is in some application very important to provide correctly tuned cable equalizers. This relates in particular to long transmission distances, e.g. 10, 50 or 200 meters. In the embodiment of figure 8, several receivers with different cable equalizers are provided, whereby some of the receivers will be unable to reconstruct the input stream because of incorrect cable equalizers, but one or more of them will probably comprise a filter that match the actual cabling used. The different cable equalizers are preferably tuned for different cable lengths and/or qualities. Because of the receivers of embodiments of the present invention being able to estimate quality information about the reliability of the output data, e.g. by determining the number of level changes in the samples that are selected for the output stream, it is possible to determine if a receiver of the present invention is unable to reconstruct the input stream, or to what degree the output may be relied on. In the present embodiment, each receiver output quality information QIl, QI2, QIn, together with the established output streams OSl, 0S2, OSn. An evaluation means EM is provided for comparing the quality information of the different receivers, and selecting an output stream OSl, 0S2, OSn to provide as the overall output stream OS. When the transmission cabling is changed, e.g. for public address setups or concert equipment possibly set up several times a week, other cable lengths or qualities may be used, and the present embodiment of the invention will automatically find the receiver best suited for reconstruction.

In an alternative embodiment, the receivers may share quality information with each other to determine which of them is best suited for reconstructing the actual input stream. In yet an alternative embodiment, the cable equalizers may be adjustable equalizers, and the evaluation means may comprise means for adjusting the cable equalizers until a reliable output stream is established. In yet an alternative embodiment of the invention, there is only one receiver comprising an adjustable cable equalizer, which is adjusted according to quality information generated by the receiver. The adjustment may, e.g., comprise trial-and-error principles.

In an embodiment of the present invention, the receivers may be differently implemented in other ways than just by different cable equalizers. In an embodiment of the present invention, the different receivers comprise different bit extraction algorithms, quality estimation algorithms, frame sync algorithms, over-sampling methods, etc. By means of evaluating and/or comparing the quality information, it can be determined which receiver implementation best suites reconstruction of the actual input stream.

The use of several receivers for purposes as explained above, is made practically and economically attractive by the receiver of the present invention being cost-effective and easily implemented compared to conventional receivers.

Claims

Patent Claims

1. Method of extracting data from an input serial data stream, comprising the steps of

over-sampling said input serial data stream by establishing at least two samples per time window of said input serial data stream,

evaluating said established samples to determine at least one time window representative sample per time window of said input serial data stream to provide as part of an output serial data stream.

2. Method of extracting data from an input serial data stream according to claim 1, whereby said input serial data stream comprises physically encoded data representations.

3. Method of extracting data from an input serial data stream according to claim 1 or 2, whereby said input serial data stream comprises time discrete data representing symbols.

4. Method of extracting data from an input serial data stream according to any of the claims 1 to 3, whereby said input serial data stream comprises audio representing data.

5. Method of extracting data from an input serial data stream according to any of the claims 1 to 4, whereby said input serial data stream comprises an ADAT stream.

6. Method of extracting data from an input serial data stream according to any of the claims 1 to 5, whereby said input serial data stream is transmitted at least partly by an optical interface.

7. Method of extracting data from an input serial data stream according to any of the claims 1 to 6, whereby said method is carried out by a processing means.

8. Method of extracting data from an input serial data stream according to any of the claims 1 to 7, whereby said method is carried out by a digital signal processor.

9. Method of extracting data from an input serial data stream according to any of the claims 1 to 8, whereby said over-sampling is performed in accordance with an over- sampling clock.

10. Method of extracting data from an input serial data stream according to any of the claims 1 to 9, whereby said over-sampling clock is frequency-locked to said input serial data stream.

11. Method of extracting data from an input serial data stream according to any of the claims 1 to 10, whereby said over-sampling clock is a substantially jitter- free clock.

12. Method of extracting data from an input serial data stream according to any of the claims 1 to 11 , whereby said over-sampling clock is an audio clock.

13. Method of extracting data from an input serial data stream according to any of the claims 1 to 12, whereby said over-sampling establishes at least four samples per time window of said input serial data stream.

14. Method of extracting data from an input serial data stream according to any of the claims 1 to 13, whereby said time-window of said input serial data stream corresponds to a bit period of said input serial data stream.

15. Method of extracting data from an input serial data stream according to any of the claims 1 to 14, whereby the value of said time window representative sample corresponds to the value intentionally represented by said time window.

16. Method of extracting data from an input serial data stream according to any of the claims 1 to 15, whereby said output serial data stream comprises a reconstruction of said input serial data stream.

17. Method of extracting data from an input serial data stream according to any of the claims 1 to 16, whereby said determining at least one time window representative sample per time window comprises storing a sample offset number.

18. Method of extracting data from an input serial data stream according to any of the claims 1 to 17, whereby said sample offset number is used to select samples to be provided as part of said output serial data stream.

19. Method of extracting data from an input serial data stream according to any of the claims 1 to 18, whereby said evaluating said established samples comprises determining the reliability of said samples.

20. Method of extracting data from an input serial data stream according to any of the claims 1 to 19, whereby said evaluating said established samples comprises determining the probability of said samples to reliably represent the value of the corresponding bits.

21. Method of extracting data from an input serial data stream according to any of the claims 1 to 20, whereby said probability of the value reliability for a sample is determined on the basis of at least one previous sample by means of sample value comparison.

22. Method of extracting data from an input serial data stream according to any of the claims 1 to 21, whereby said probability of the value reliability for a sample is determined on the basis of the previous sample by means of sample value comparison.

23. Method of extracting data from an input serial data stream according to any of the claims 1 to 22, whereby said probability of the value reliability for a sample is determined on historical information of previous samples.

24. Method of extracting data from an input serial data stream according to any of the claims 1 to 23, whereby said historical information comprises a distribution of number of value changes over different sample offset numbers.

25. Method of extracting data from an input serial data stream according to any of the claims 1 to 24, whereby said over-sampling comprises over-sampling by approximately a pre-determined multiple of the time window rate of said input serial data stream, evaluating said established samples comprises counting the samples with a counter that wraps for each said pre-determined multiple, storing a sample offset number of said time window representing sample in a register, each time the value of said counter equals said sample offset number of said register providing the current sample to said output serial data stream.

26. Method of extracting data from an input serial data stream according to any of the claims 1 to 25, whereby said evaluating said established samples comprises counting the samples with a counter that wraps for each said pre-determined multiple, storing a sample offset number of said time window representing sample in a register, each time the value of said counter equals said sample offset number of said register comparing the current sample with the previous sample and if a sample value change is detected increment the sample offset number of said register.

27. Method of extracting data from an input serial data stream according to any of the claims 1 to 26, whereby said evaluation is performed on a run-time basis.

28. Method of sampling data, comprising the steps of

establishing samples by measuring said data frequently, establishing an output stream of data-representing samples by evaluating said samples according to a quality scale.

29. Method of sampling data according to claim 28, whereby said evaluating said samples is performed on a one-by-one basis.

30. Method of sampling data according to claim 28 or 29, whereby said measuring of said data frequently comprises measuring the level of said data by an over-sampling method.

31. Method of sampling data according to any of the claims 28 to 30, whereby said method comprises a method of extracting data from an input serial data stream according to any of the claims 1 to 27.

32. Method of reconstructing an input serial data stream, said method comprising receiving said input serial data stream by at least two different serial data stream receivers simultaneously and evaluating quality information provided by said serial data stream receivers to determine one of said different serial data stream receivers to provide an output data stream by reconstructing said input serial data stream.

33. Method of reconstructing an input serial data stream according to claim 32, whereby the difference of said at least two different serial data stream receivers comprises differently implemented cable equalizers.

34. Method of reconstructing an input serial data stream according to claim 32 or 33, whereby the difference of said at least two different serial data stream receivers comprises differently implemented data extraction methods.

35. Method of reconstructing an input serial data stream according to any of the claims 32 to 34, whereby said quality information represents the estimated ability to reconstruct said input serial data stream.

36. Method of reconstructing an input serial data stream according to any of the claims 32 to 35, whereby said quality information is based on estimated reliability of individual samples established by an over-sampling method within each of said receivers.

37. Method of reconstructing an input serial data stream according to any of the claims 32 to 36, whereby said receivers implements a method of extracting data from an input serial data stream according to any of the claims 1 to 27.

38. Method of reconstructing an input serial data stream according to any of the claims 32 to 37, whereby said receivers implements a method of sampling data according to any of the claims 28 to 31.

39. Method of establishing a clock that is phase-locked to an incoming stream, comprising establishing a stream of samples by over-sampling said incoming stream, evaluating said stream of samples to determine phase information of said incoming stream, selecting a part of said samples according to said determined phase information, and establishing said clock by providing said selected samples.

40. Method of establishing a clock that is phase-locked to an incoming stream according to claim 39, whereby said evaluation comprises run-time evaluation.

41. Method of establishing a clock that is phase-locked to an incoming stream according to claim 39 or 40, whereby said method is adaptive.

42. Method of establishing a clock that is phase-locked to an incoming stream according to any of the claims 39 to 41, whereby said over-sampling is based on an over-sampling clock which is frequency locked to said incoming stream.

43. Method of establishing a clock that is phase-locked to an incoming stream according to any of the claims 39 to 42, whereby said over-sampling is based on a fixed over-sampling clock.

44. Method of establishing a clock that is phase-locked to an incoming stream according to any of the claims 39 to 43, whereby said method comprises a method of extracting data from an input serial data stream according to any of the claims 1 to 27.

45. Method of establishing a clock that is phase-locked to an incoming stream according to any of the claims 39 to 44, whereby said method comprises a method of sampling data according to any of the claims 28 to 31.

46. Method of establishing a clock that is phase-locked to an incoming stream according to any of the claims 39 to 45, whereby said method comprises a method of reconstructing an input serial data stream according to any of the claims 32 to 38.

47. Serial data stream receiver (R; Rl, R2, Rn) comprising a sample means (SM; SMl, SM2, SMn) for sampling a serial data stream (IS; ISl, IS2, ISn) according to an over-sample clock (OSC) and providing a sampled stream (SSl, SS2, SSn), and a bit extractor (BEl, BE2, BEn) for selecting samples from said sampled stream to provide as an output stream (OS; OSl, OS2, OSn).

48. Serial data stream receiver according to claim 47, wherein said over-sample clock is established by means of a frame sync means (FMS).

49. Serial data stream receiver according to claim 47 or 48, wherein said frame sync means establishes said over-sample clock in the basis of said serial data stream.

50. Serial data stream receiver according to any of the claims 47 to 49, wherein said over-sample clock is frequency locked to said serial data stream.

51. Serial data stream receiver according to any of the claims 47 to 50, wherein said bit-extractor comprises an edge detector (ED), a counter (CNT) and a register (REG).

52. Serial data stream receiver according to any of the claims 47 to 51, wherein said output stream comprises a bit rate corresponding to said serial data stream.

53. Serial data stream receiver according to any of the claims 47 to 52, wherein said over-sample clock comprises a clock rate corresponding to at least twice the bit rate of said serial data stream, preferably four times said bit rate.

54. Serial data stream receiver according to any of the claims 47 to 53, wherein said bit extractor comprises memory.

55. Serial data stream receiver according to any of the claims 47 to 54, wherein said bit extractor comprises means for selecting samples according to statistical methods.

56. Serial data stream receiver according to any of the claims 47 to 55, wherein said serial data stream comprises physically encoded data representations.

57. Serial data stream receiver according to any of the claims 47 to 56, wherein said serial data stream comprises time discrete data representing symbols.

58. Serial data stream receiver according to any of the claims 47 to 57, wherein said serial data stream comprises audio representing data.

59. Serial data stream receiver according to any of the claims 47 to 58, wherein said serial data stream comprises an ADAT stream.

60. Serial data stream receiver according to any of the claims 47 to 59, wherein said serial data stream is transmitted at least partly by an optical interface.

61. Serial data stream receiver according to any of the claims 47 to 60, wherein said serial data stream receiver comprises processing means.

62. Serial data stream receiver according to any of the claims 47 to 61, wherein said serial data stream receiver comprises a digital signal processor.

63. Serial data stream receiver according to any of the claims 47 to 62, wherein said over-sample clock is a substantially jitter- free clock.

64. Serial data stream receiver according to any of the claims 47 to 63, wherein said over-sample clock is an audio clock.

65. Serial data stream receiver according to any of the claims 47 to 64, wherein said over-sample clock is established by means of a phase locked loop.

66. Serial data stream receiver according to any of the claims 47 to 65, wherein said sampling according to said over-sample clock establishes at least four samples per time window of said serial data stream.

67. Serial data stream receiver according to any of the claims 47 to 66, wherein said time-window of said serial data stream corresponds to a bit period of said serial data stream.

68. Serial data stream receiver according to any of the claims 47 to 67, wherein the values of said selected samples correspond to the values intentionally represented by said time windows.

69. Serial data stream receiver according to any of the claims 47 to 68, wherein said output stream comprises a reconstruction of said serial data stream.

70. Serial data stream receiver according to any of the claims 47 to 69, wherein said bit-extractor stores a sample offset number.

71. Serial data stream receiver according to any of the claims 47 to 70, wherein said sample offset number is used to select samples to be provided as part of said output stream.

72. Serial data stream receiver according to any of the claims 47 to 71, wherein said bit extractor comprises means for determining the reliability of the samples of said sampled stream.

73. Serial data stream receiver according to any of the claims 47 to 72, wherein said bit extractor comprises means for determining the probability of the samples of said sampled stream to reliably represent the value of the corresponding bits.

74. Serial data stream receiver according to any of the claims 47 to 73, wherein said probability of the value reliability for a sample is determined on the basis of at least one previous sample by means of sample value comparison.

75. Serial data stream receiver according to any of the claims 47 to 74, wherein said probability of the value reliability for a sample is determined on the basis of the previous sample by means of sample value comparison.

76. Serial data stream receiver according to any of the claims 47 to 75, wherein said probability of the value reliability for a sample is determined on historical information of previous samples.

77. Serial data stream receiver according to any of the claims 47 to 76, wherein said historical information comprises a distribution of number of value changes over different sample offset numbers.

78. Serial data stream receiver according to any of the claims 47 to 77, wherein said serial data stream receiver comprises means for carrying out a method of extracting data from an input serial data stream according to any of the claims 1 to 27.

79. Serial data stream receiver according to any of the claims 47 to 78, wherein said serial data stream receiver comprises means for carrying out a method of sampling data according to any of the claims 28 to 31.

80. Serial data stream receiver according to any of the claims 47 to 79, wherein said serial data stream receiver comprises means for carrying out a method of reconstructing an input serial data stream according to any of the claims 32 to 38.

81. Serial data stream receiver according to any of the claims 47 to 80, wherein said serial data stream receiver comprises means for carrying out a method of establishing a clock that is phase-locked to an incoming stream according to any of the claims 39 to 46.

82. Data sampling device comprising a sampling means, an evaluation means and an output means, wherein said sampling means establishes samples of said data and said evaluation means comprises means for determining a quality scale and selecting according to said quality scale a part of said samples and providing them to said output means.

83. Data sampling device according to claim 82, wherein said data sampling device comprises a serial data stream receiver according to any of the claims 47 to 81.

84. Data sampling device according to claim 82 or 83, wherein said data sampling device comprises means for carrying out a method of extracting data from an input serial data stream according to any of the claims 1 to 27.

85. Data sampling device according to any of the claims 82 to 84, wherein said data sampling device comprises means for carrying out a method of sampling data according to any of the claims 28 to 31.

86. Data sampling device according to any of the claims 82 to 85, wherein said data sampling device comprises means for carrying out a method of reconstructing an input serial data stream according to any of the claims 32 to 38.

87. Data sampling device according to any of the claims 82 to 86, wherein said data sampling device comprises means for carrying out a method of establishing a clock that is phase-locked to an incoming stream according to any of the claims 39 to 46.

88. Serial data stream receiver comprising at least two differently implemented receivers comprising means for determining a quality information regarding their performance, an evaluation means comprising means for evaluating said receivers on the basis of said quality information and determining one of said receivers to provide a reconstruction of said serial data stream to an output means.

89. Serial data stream receiver according to claim 88, wherein the difference of said at least two differently implemented receivers comprises differently implemented cable equalizers.

90. Serial data stream receiver according to claim 88 or 89, wherein the difference of said at least two differently implemented receivers comprises differently implemented data extraction methods.

91. Serial data stream receiver according to any of the claims 88 to 90, wherein said quality information represents the estimated ability to reconstruct said input serial data stream.

92. Serial data stream receiver according to any of the claims 88 to 91, wherein said quality information is based on estimated reliability of individual samples established by an over-sampling method within each of said receivers.

93. Serial data stream receiver according to any of the claims 88 to 92, wherein at least one of said differently implemented receivers comprises a serial data stream receiver according to any of the claims 47 to 81.

94. Serial data stream receiver according to any of the claims 88 to 93, wherein at least one of said differently implemented receivers comprises a data sampling device according to any of the claims 82 to 87.

95. Serial data stream receiver according to any of the claims 88 to 94, wherein at least one of said differently implemented receivers comprises means for carrying out a method of extracting data from an input serial data stream according to any of the claims 1 to 27.

96. Serial data stream receiver according to any of the claims 88 to 95, wherein at least one of said differently implemented receivers comprises means for carrying out a method of sampling data according to any of the claims 28 to 31.

97. Serial data stream receiver according to any of the claims 88 to 96, wherein at least one of said differently implemented receivers comprises means for carrying out a method of reconstructing an input serial data stream according to any of the claims 32 to 38.

98. Serial data stream receiver according to any of the claims 88 to 97, wherein at least one of said differently implemented receivers comprises means for carrying out a method of establishing a clock that is phase-locked to an incoming stream according to any of the claims 39 to 46.

99. Processing means for carrying out a method of extracting data from an input serial data stream according to any of the claims 1 to 27.

100. Processing means for carrying out a method of sampling data according to any of the claims 28 to 31.

101. Processing means for carrying out a method of reconstructing an input serial data stream according to any of the claims 32 to 38.

102. Processing means for carrying out a method of establishing a clock that is phase-locked to an incoming stream according to any of the claims 39 to 46.

103. Processing means according to any of the claims 99 to 102, wherein said processing means comprises a microchip.

104. Processing means according to any of the claims 99 to 103, wherein said processing means comprises a digital signal processor.

105. Data carrier storing instructions that cause a method according to any of the claims 1 to 46 to be carried out when performed by a processing means.