WO2008076444B1 - Refined optical system - Google Patents
Refined optical systemInfo
- Publication number
- WO2008076444B1 WO2008076444B1 PCT/US2007/025912 US2007025912W WO2008076444B1 WO 2008076444 B1 WO2008076444 B1 WO 2008076444B1 US 2007025912 W US2007025912 W US 2007025912W WO 2008076444 B1 WO2008076444 B1 WO 2008076444B1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- memory
- nvs
- physical addresses
- addresses
- logical addresses
- Prior art date
Links
- 230000003287 optical effect Effects 0.000 title abstract 2
- 230000015654 memory Effects 0.000 claims 77
- 238000013507 mapping Methods 0.000 claims 20
- 238000000034 method Methods 0.000 claims 18
- 239000007787 solid Substances 0.000 claims 18
- 230000015556 catabolic process Effects 0.000 claims 5
- 238000006731 degradation reaction Methods 0.000 claims 5
- 238000012544 monitoring process Methods 0.000 claims 4
- 239000004065 semiconductor Substances 0.000 claims 3
- 150000004767 nitrides Chemical class 0.000 claims 2
- 238000003384 imaging method Methods 0.000 abstract 4
- 230000005855 radiation Effects 0.000 abstract 2
- 238000005259 measurement Methods 0.000 abstract 1
Classifications
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B26/00—Optical devices or arrangements for the control of light using movable or deformable optical elements
- G02B26/08—Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light
- G02B26/0816—Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light by means of one or more reflecting elements
- G02B26/0833—Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light by means of one or more reflecting elements the reflecting element being a micromechanical device, e.g. a MEMS mirror, DMD
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/45—Cameras or camera modules comprising electronic image sensors; Control thereof for generating image signals from two or more image sensors being of different type or operating in different modes, e.g. with a CMOS sensor for moving images in combination with a charge-coupled device [CCD] for still images
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/58—Means for changing the camera field of view without moving the camera body, e.g. nutating or panning of optics or image sensors
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J3/00—Spectrometry; Spectrophotometry; Monochromators; Measuring colours
- G01J3/02—Details
- G01J3/0205—Optical elements not provided otherwise, e.g. optical manifolds, diffusers, windows
- G01J3/021—Optical elements not provided otherwise, e.g. optical manifolds, diffusers, windows using plane or convex mirrors, parallel phase plates, or particular reflectors
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J3/00—Spectrometry; Spectrophotometry; Monochromators; Measuring colours
- G01J3/02—Details
- G01J3/0256—Compact construction
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J3/00—Spectrometry; Spectrophotometry; Monochromators; Measuring colours
- G01J3/02—Details
- G01J3/0289—Field-of-view determination; Aiming or pointing of a spectrometer; Adjusting alignment; Encoding angular position; Size of measurement area; Position tracking
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
- G01S7/497—Means for monitoring or calibrating
- G01S7/4972—Alignment of sensor
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/30—Transforming light or analogous information into electric information
- H04N5/33—Transforming infrared radiation
Abstract
Selected scene regions are imaged. IMAGING CHANNEL: mirrors (preferably MEMS) address an imaging sensor to regions. CALIBRATION CHANNEL: the mirrors direct radiation from a source to a calibration sensor, along an imaging -channel segment. Beam splitter (s) let the channels share optical path at the mirrors. To minimize imaging- channel diffractive blur, the calibration channel modifies wave front angle and smoothness at the mirrors - measuring (and setting mirrors to optimize) PSF sharpness, then applying these measurements (and settings) to optimize imaging-channel settings by iterative multidi-mensional gradient search. An afocal lens receives scene radiation, magnifying deflection at the scene. An FOR is imaged on the imaging sensor; the mirrors address the sensor to a narrow FOV within the FOR; the lens enlarges deflections to cover the FOR. Plural diffraction- grating orders communicate between calibration source and sensor when the selected region is in plural scene portions, regardless which FOV is addressed.
Claims
AMENDED CLAIMS
[received by the International Bureau on
08 July 2008 (08.07.08) - 7 pages] second NVS memory, wherein said first logical addresses are accessed less frequently than said second logical addresses.
41. A solid state memory system comprising: a first nonvolatile semiconductor (NVS) memory having a first access time and a first capacity; a second nonvolatile semiconductor (NVS) memory having a second access time that is less than said first access time and a second capacity that is different than said first capacity; a mapping module that maps logical addresses to physical addresses of one of said first and second NVS memories based on at least one of said first access time, said second access time, said first capacity, and said second capacity; and a wear leveling module that monitors first and second wear levels of said first and second NVS memories, respectively, wherein said first and second NVS memories have first and second write cycle lifetimes, respectively.
42. The solid state memory system of claim 41 wherein said mapping module caches data to said second NVS memory.
43. (Cancelled)
44. The solid state memory system of claim 41 wherein said first wear level is substantially based on a ratio of a first number of write operations performed on said first NVS memory to said first write cycle lifetime, and wherein said second wear level Is substantially based on a ratio of a second number of write operations performed on said second NVS memory to said second write cycle lifetime.
45. The solid state memory system of claim 41 wherein said wear leveling module maps said logical addresses to said physical addresses of said second memory when said second wear level is less than said first wear level.
46. The solid state memory system of claim 41 wherein said mapping modulθ receives first and second frequencies for writing data to first and second of said logical addresses, wherein said wear leveling modulθ biases mapping of said first of said logical addresses to said physical addresses of said second NVS memory when said first frequency is greater than said second frequency and said second wear level is less than said first wear level.
47. The solid state memory system of claim 46 wherein said wear leveling module biases mapping of said second of said logical addresses to said physical addresses of said first NVS memory.
48. The solid state memory system of claim 46 further comprising a write monitoring module that monitors subsequent frequencies of writing data to said first and second of said logical addresses and that updates said first and second frequencies based on said subsequent frequencies.
49. The solid state memory system of claim 41 further comprising a write monitoring module that measures first and second frequencies of writing data to first and second of said logical addresses, wherein said wear leveling module biases mapping of said first of said logical addresses to said physical addresses of said second NVS memory when said first frequency is greater than said second frequency and said second wear level is less than said first wear level.
50. The solid state memory system of claim 49 wherein said wear leveling module biases mapping of said second of said logical addresses to said physical addresses of said first NVS memory.
51. The solid state memory system of claim 41 further comprising a degradation testing modulθ that: writes data at a first predetermined time to one of said physical addresses;
generates a first stored data by reading data from said one of said physical addresses; writes data to said one of said physical addresses at a second predetermined time; generates a second stored data by reading data from said one of said physical addresses; and generates a degradation value for said one of said physical addresses based on said first and second stored data.
52. The solid state memory system of claim 51 wherein said wear leveling module maps one of said logical addresses to said one of said physical addresses based on said degradation value.
53. The solid state memory system of claim 41 wherein : said wear leveling module maps said logical addresses to said physical addresses of said first NVS memory when said second wear level is greater than or equal to a predetermined threshold; and said wear leveling module maps said logical addresses to said physical addresses of said second NVS memory when said first wear level is greater than or equal to a predetermined threshold.
54. The solid state memory system of claim 41 wherein when write operations performed on a first block of said physical addresses of said first NVS memory during a predetermined period are greater than or equal to a predetermined threshold, said wear leveling module biases mapping of corresponding ones of said logical addresses from said first block to a second block of said physical addresses of said second NVS memory.
55. The solid state memory system of claim 41 wherein said wear leveling module identifies a first block of said physical addresses of said second NVS memory as a least used block (LUB).
56. The solid state memory system of claim 55 wherein said wear leveling module biases mapping of corresponding ones of said logical addresses from said first block to a second block of said physical addresses of said first NVS memory when available memory in said second NVS memory is less than or equal to a predetermined threshold.
57. The solid state memory system of claim 41 wherein said first NVS memory comprises a flash device and said second NVS memory comprises a phase-change memory device.
58. The solid state memory system of claim 57 wherein said first NVS memory comprises an Nitride Read-Only Memory (NROM) flash device.
59. A method comprising: receiving access commands including logical addresses; and mapping said logical addresses to physical addresses of one of first and second nonvolatile semiconductor (NVS) memories based on at least one of a first access time, a second access time, a first capacity, and a second capacity, wherein said first NVS memory has said first access time and said first capacity and said NVS memory has said second access time, which is less than said first access time, and said second capacity, which is less than said first capacity; and monitoring first and second wear levels of said first and second
NVS memories, respectively, wherein said first and second NVS memories have first and second write cycle lifetimes, respectively.
60. The method of claim 59 further comprising caching data to said second NVS memory.
61. (Cancelled)
62. The method of claim 59 wherein said first wear level is substantially based on a ratio of a first number of write operations performed on said first NVS memory to said first write cycle lifetime, and wherein said second wear level is substantially based on a ratio of a second number of write operations performed on said second NVS memory to said second write cycle lifetime.
63. The method of claim 59 further comprising mapping said logical addresses to said physical addresses of said second memory when said second wear level is less than said first wear level.
64. The method of claim 59 further comprising: receiving first and second frequencies for writing data to first and second of said logical addresses; and biasing mapping of said first of said logical addresses to said physical addresses of said second NVS memory when said first frequency is greater than said second frequency and said second wear level fs less than said first wear level.
65. The method of claim 64 further comprising biasing mapping of said second of said logical addresses to said physical addresses of said first NVS memory.
66. The method of claim 64 further comprising: monitoring subsequent frequencies of writing data to said first and second of said logical addresses; and updating said first and second frequencies based on said subsequent frequencies.
67. The method of claim 59 further comprising: measuring first and second frequencies of writing data to first and second of said logical addresses; and
biasing mapping of said first of said logical addresses to said physical addresses of said second NVS memory when said first frequency is greater than said second frequency and said second wear level is less than said first wear level.
68. The method of claim 67 further comprising biasing mapping of said second of said logical addresses to said physical addresses of said first NVS memory.
69. The method of claim 59 further comprising: writing data at a first predetermined time to one of said physical addresses; generating a first stored data by reading data from said one of said physical addresses; writing data to said one of said physical addresses at a second predetermined time; generating a second stored data by reading data from said one of said physical addresses; and generating a degradation value for said one of said physical addresses based on said first and second stored data.
70. The method of claim 69 further comprising mapping one of said logical addresses to said one of said physical addresses based on said degradation value.
71. The method of claim 59 further comprising: mapping said logical addresses to said physical addresses of said first NVS memory when said second wear level is greater than or equal to a predetermined threshold; and mapping said logical addresses to said physical addresses of said second NVS memory when said first wear level is greater than or equal to a predetermined threshold.
72. The method of claim 59 wherein when write operations performed on a first block of said physical addresses of said first NVS memory during a predetermined period are greater than or equal to a predetermined threshold, biasing mapping of corresponding ones of said logical addresses from said first block to a second block of said physical addresses of said second NVS memory.
73. The method of claim 59 further comprising identifying a first block of said physical addresses of said second NVS memory as a least used block (LUB).
74. The method of claim 73 further comprising biasing mapping of corresponding ones of said logical addresses from said first block to a second block of said physical addresses of said first NVS memory when available memory in said second NVS memory is less than or equal to a predetermined threshold.
75. The method of claim 59 wherein said first NVS memory comprises a flash device and said second NVS memory comprises a phase-change memory device.
76. The method of claim 75 wherein said first NVS memory comprises a Nitride Read-Only Memory (NROM) flash device.
77. The solid state memory system of claim 41 wherein said second NVS memory includes single-level cell (SLC) flash memory and said first NVS memory include multi-level cell (MLC) flash memory.
78. The method of claim 59 wherein said second NVS memory includes single-level cell (SLC) flash memory and said first NVS memory include multi-level cell (MLC) flash memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/456,504 US8624177B2 (en) | 2006-12-16 | 2009-06-16 | Refined optical system |
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US87510306P | 2006-12-16 | 2006-12-16 | |
| US60/875,103 | 2006-12-16 | ||
| US92023007P | 2007-03-27 | 2007-03-27 | |
| US60/920,230 | 2007-03-27 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US12/456,504 Continuation US8624177B2 (en) | 2006-12-16 | 2009-06-16 | Refined optical system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| WO2008076444A1 WO2008076444A1 (en) | 2008-06-26 |
| WO2008076444B1 true WO2008076444B1 (en) | 2008-08-21 |
Family
ID=39332964
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US2007/025912 WO2008076444A1 (en) | 2006-12-16 | 2007-12-17 | Refined optical system |
Country Status (1)
| Country | Link |
|---|---|
| WO (1) | WO2008076444A1 (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2333603A1 (en) * | 2009-12-08 | 2011-06-15 | Alcatel Lucent | An optical beam scanner |
| TWI514000B (en) | 2010-08-31 | 2015-12-21 | Corning Inc | Mems based surveillance system and a method for using same |
| US9071742B2 (en) * | 2011-07-17 | 2015-06-30 | Ziva Corporation | Optical imaging with foveation |
| US9921396B2 (en) | 2011-07-17 | 2018-03-20 | Ziva Corp. | Optical imaging and communications |
| DE102013019560B4 (en) * | 2013-11-22 | 2022-03-03 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Imaging radiation sensor |
| CN107589428B (en) * | 2017-11-03 | 2023-10-31 | 长春理工大学 | Multi-area array APD array-based composite mode laser radar imaging system |
| US20220229161A1 (en) * | 2019-06-05 | 2022-07-21 | Innoviz Technologies | Electro-optical systems for scanning illumination onto a field of view and methods |
| CN111928960B (en) * | 2020-08-19 | 2022-09-16 | 深圳元戎启行科技有限公司 | Wavefront detection device and imaging system based on wavefront detection |
| CN115144373A (en) * | 2022-06-29 | 2022-10-04 | 华中科技大学 | Reflective laminated diffraction imaging method, device and system based on angle self-calibration |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004083795A2 (en) * | 2002-12-13 | 2004-09-30 | Arete Associates | Optical system |
| US7297934B2 (en) * | 2003-12-12 | 2007-11-20 | ARETé ASSOCIATES | Optical system |
| WO2006076474A1 (en) * | 2005-01-13 | 2006-07-20 | Arete Associates | Optical system with wavefront sensor |
-
2007
- 2007-12-17 WO PCT/US2007/025912 patent/WO2008076444A1/en active Application Filing
Also Published As
| Publication number | Publication date |
|---|---|
| WO2008076444A1 (en) | 2008-06-26 |
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