WO2008075125A1

WO2008075125A1 - Method and decoder for tail-biting decoding

Info

Publication number: WO2008075125A1
Application number: PCT/IB2006/003719
Authority: WO
Inventors: Jean-François BERGEVIN; Gwenael Poitau
Original assignee: Wavesat Inc.; Sk Telecom Cl., Ltd.
Priority date: 2006-12-20
Filing date: 2006-12-20
Publication date: 2008-06-26

Abstract

The present invention relates to a method and a decoder for decoding a convolutionally encoded sequence of bits. The method and decoder of the present invention decode the convolutionally encoded sequence of bits, and re-decode a first portion thereof. Then, the method and decode proceeds with outputting the decoded sequence of bits, wherein the first portion of the decoded sequence of bits corresponds to re-decoded first portion of the sequence of bits.

Description

TITLE: METHOD AND DECODER FOR TAIL-BITING DECODING

FIELD OF THE INVENTION The present invention relates to Viterbi decoding, and more particularly to a method and an apparatus for performing decoding of tail-biting convolutionally encoded sequence of bits.

BACKGROUND OF THE INVENTION

In the last decades, the interest toward wireless communications has greatly increased. Such an interest has pushed the development and refinement of wireless protocols and technologies. All types of wireless communications have one thing in common: they allow data transmission over the air. However, transmitting data over the air introduces issues such as interference and distortion of data signal. To overcome such issues, encoding of data is being used.

There are various types of encoding mechanisms, each having their advantages and drawbacks. Amongst the most popular are the convolutional encoding techniques. Convolutional encoding consists in multiplying all the bits of a sequence with a generator matrix so as to create codewords. The generator matrix can be subdivided in three specific types: zero-tail matrix, a direct truncation matrix and a tail-biting matrix. The zero-tail matrix requires that last eight bits of the bits of sequence to be encoded be zeroes. This type of generator matrix advantageously allows having a known end state of zeroes when decoding encoded data. However, this requirement introduces a throughput reduction on an encoder. The direct truncation matrix proceeds with direct encoding, without knowing a prior state of the encoder or decoder. The direct truncation matrix is thus the weakest of the three types of generator matrix, as it does not provide any initializing. The tail-biting matrix uses the last bits of the codewords to initialize its encoding pattern. This subcategory of generator matrix introduces decoding difficulties such as an unknown initial and ending states, while allowing maximal throughput. Institute of Electrical and Electronics Engineers (IEEE) defines in IEEE 802.16-2004 and IEEE 802.16e-2005 specifics for the generator matrix of the zero tail-biting and tail- biting types for modulation techniques such as Orthogonal Frequency Division Multiplexing (OFDM) and Orthogonal Frequency Division Multiplexing Access (OFDMA). Encoding however means that decoding is required to recover the original bits of the sequence. Andrew J. Viterbi developed a technique known as the Viterbi Decoder Algorithm in the late 1960s,. The Viterbi Decoder Algorithm uses a trellis representation to decode codewords relying on a maximum likelihood analysis. The trellis representation is a redundant description of a state diagram of an encoder. As an encoder can only go from one state to two further states upon receipt of an input bit, Viterbi provides a simple way for recovering the original bits of a sequence from codewords. However, when errors happen in a transmission of the codewords, as often is the case because of interference or poor transmission or reception of wireless data communications, some additional efforts must be made to recover the original bits of the sequence.

For doing so, Viterbi further describes a method for calculating a number of erroneous bits for each path on the trellis, and thus evaluating a most likely number of errors based on the number of calculated erroneous bits. Other improvements have been made to the Viterbi Decoder Algorithm, to address cases where an initial state of an encoder is known and when it is not known. Those improvements are referred to as zero tailing and tail-biting. The zero tailing improvement of the Viterbi Decoder Algorithm requires a start and end states of a decoder to be forced to zero values. This improvement of the Viterbi Decoder Algorithm results in a reduction of the throughput. The tail- biting of the Viterbi Decoder Algorithm is used when the start and end states of the encoder are unknown. As not knowing the start and end states of the decoder greatly increases the possible paths taken along the trellis, analysis of each path is required, resulting in an important processing power, and latency when decoding the codewords. To overcome that added difficulty efficiently, last bits of the codewords are used to initialize the decoder, thus recreating an identical start and end states and thereby reducing the number of paths to be analyzed on the trellis.

Various tail-biting alternatives have been proposed in the past. One of the most referenced alternative has been proposed by Howard H. Ma and Jack K. Wolf, and was described in an article titled "On Tail-Biting Convolutional Codes", published at IEEE Transactions on Communications, Volume COM- 34, No. 2, pp.104-111 , February 1986. That paper proposes two algorithms for solving latency issues with tail-biting convolutional decoding. The first algorithm consists of identifying, through trial and error, which starting state returns the same ending state. However, this algorithm is suboptimal because it does not compensate for codewords including many errors, which can result in start and end state that are the same, even though they are not the right ones. The second algorithm consists of using algebraic structure of the convolution code to obtain the starting state, thus reducing a number of iterations. However, both these algorithms require that the whole codewords be processed iteratively to reach an optimal bit error rate, thus resulting in important latency.

Another reference of interest has been published by Qian Wang and Vijay K. Bhargava, and is titled "An efficient maximum likelihood decoding algorithm for generalized tail-biting convolutional codes including quasi-cyclic codes", IEEE Transactions on Communications, Volume 37, No. 8, pp.875-879, in August 1989. That paper describes two other algorithms based on the Viterbi Decoding Algorithm. More particularly, the first algorithm consists of storing the path with the largest metric together with its metrics for each start and end states, and eliminate all other paths. The second algorithm re-uses results from the first algorithm, and selects the path with the largest metrics' end state, and uses a start state equivalent to the end state and reuses those end state and start state for all other stored paths. However, these algorithms are not appropriate for real time tail-biting as they rely on iterations, which are too time consuming for being implemented for real time data transmissions. United States Patent No. 5,355,376 filed on October 11^th, 1994 by AT&T Bell Laboratories also describes a "Circular Viterbi Algorithm". In this algorithm, received codewords are appended in such a way that the Viterbi decoders continuously decode repeated codewords until one of four conditions is reached, i.e. when the metrics have converged, when the paths of trace back length becomes equivalent to a previous one, when the previous two conditions are attained, or when a fixed number of iterations has been reached. However, it can appreciated to those skilled in the art that the algorithm proposed by AT&T Bell Laboratories still causes an important latency, as the same codeword has to be decoded multiple times.

United States Patent No. 5,721 ,746 filed on February 24^th, 1998 and assigned to General Electric Company also describes another possible algorithm for decoding codewords. That algorithm relies on a particular encoding technique described by L.R. Bahl and al. in an articled titled "Optimal Decoding of Linear Codes for Minimizing Symbol Error Rate" published by IEEE Transactions on Information Theory, Volume IT-20, pp.284-287 on March 1974. This encoding technique relies more particularly on a generator matrix that performs forward recursion and backward recursion. However, this method is mathematically very intensive and requires iterative decoding, which increases latency and is not suitable for many wireless data transmissions.

Another algorithm of interest has been presented by Rose Y. Shao, Shu Lin and Marc P.C. Fossorier in a presentation titled "An Iterative Bidirectional Decoding Algorithm for tail-biting codes", made at 1999 IEEE ITW, in Kruger National Park in South Africa on June 20-25, 1999. Previous algorithms used unidirectional tail-biting decoding algorithms, which means that the decoding is performed from the first to the last bit of the received codeword. However, this algorithm proposes performing a backward decoding of the received codewords. Unfortunately, this algorithm requires dual high processing and is complex, and is still an iterative tail-biting decoding method, which is not applicable to real time applications. There is therefore a need for a decoding method and a decoder that is more appropriate for real time application by requiring less processing capability and having a lower latency, and more particularly a non-iterative decoding method and decoder. SUMMARY OF THE INVENTION

The present invention provides a decoding method and a decoder requiring less processing capability than decoders described in the prior art, while being capable of a lower latency and being appropriate for real-time applications and applications such as wireless data transfers and mobile applications, by being non-iterative.

For doing so, the method of the present invention includes a step of decoding the convolutionally encoded sequence of bits using a Viterbi decoder. The method then proceeds with re-decoding a first portion of the convolutionally encoded sequence of bits. The method then outputs the decoded sequence of bits, wherein an outputted decoded first portion of the convolutionally encoded sequence of bits corresponds to re-decoded first portion of the convolutionally encoded sequence of bits.

In another aspect, the present invention is directed to a decoder for decoding a convolutionally encoded sequence of bits. The decoded includes an an input port for receiving the convolutionally encoded sequence of bits. The decoder also includes a Viterbi decoder for decoding the convolutionally encoded sequence of bits and re-decoding a first portion of the convolutionally encoded sequence of bits. Finally, the decoder also includes an output port for outputting the decoded convolutionally encoded sequence of bits, wherein the first portion of the decoded convolutionally encoded sequence of bits corresponds to re-decoded first portion of the convolutionally encoded sequence of bits.

BRIEF DESCRIPTION OF THE DRAWINGS

In the following description, the following drawings are used to describe and exemplify the present invention: Figure 1a and b are flowcharts of methods in accordance with aspects of the present invention;

Figures 2a and 2b are schematic representations of examples of post fixing in accordance with two aspects of the present invention; Figure 3 is a schematic view of a decoder in accordance with an aspect of the present invention;

Figure 4 is a schematic view of a decoder in accordance with an aspect of the present invention in use in a modem; and

Figure 5 is a graph depicting bit error rate performances of a decoder in accordance with aspects of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to a method and a decoder for decoding tail- biting convolutionally encoded sequence of bits. More particularly, the method and decoder of the present invention decodes a convolutionally encoded sequence of bits, and re-decodes a first portion of the convolutionally encoded sequence of bits. The method and decoder then outputs a decoded sequence of bits wherein the first portion of the decoded sequence of bits corresponds to the re-decoded first portion.

The present invention is characterized by many advantages over prior art solutions. First and foremost, the present invention describes a tail-biting

Viterbi decoder that is non-iterative. By removing the usual iterative approach, the present invention results in a simpler and lower cost solution by allowing use of a zero-tail decoder, also known as a standard state "00"

Viterbi decoder. Finally, the present invention, because of its simplicity, can be implemented in an on-chip system, rendering it implementable in wireless communications systems for data transfers.

It should also be appreciated that in normal usage of IEEE 802.16e-2005 standard, also known as the Wireless Broadband profile, Convolutional Turbo

Code is mandatory and will be used in normal mode as its performances are recognized as being better that those obtained with regular convolutional encoding. Such a requirement is an additional justification for a simple and efficient tail-biting decoder, as the tail-biting mode will most likely be restrained for messages known as Frame Control Header (FCH) messages.

Reference is now made to Figures 1a and 1b, which depict flowcharts of two aspects of a method 10 for decoding a tail-biting convolutionally encoded sequence of bits, in accordance with the present invention. The method of Figure 1a starts by receiving a sequence of bits at step 11. The method continues with a step 14 of decoding the received sequence of bits. More particularly in that aspect of the invention, the decoding of step 14 further includes re-decoding a first portion of the received bits. To optimize the performances of the present invention, both in throughput and quality of the decoded sequence of bits, the first portion has a length equal to a number of bits required to initialize a decoder performing the decoding step. Then, the method completes with a step of outputting 19 the decoded sequence of bits. The decoded sequence of bits outputted in step 19 is preferably composed of the first portion and a remaining portion of the decoded sequence of bits. The first portion corresponds to the re-decoded sequence of bits, while the remaining portion corresponds to the remaining portion of the decoded sequence of bits. In the other aspect of the method, shown on Figure 1b, the method further includes a step copying and appending (step 12) a first portion of the convolutionally encoded sequence of bits at an end of the convolutionally encoded sequence of bits. Such copying and appending of the first portion of the convolutionally encoded sequence of bits is one possible way of facilitating the later re-decoding of the first portion of the encoded sequence of bits. This operation can also be named post fixing.

Reference is now been made concurrently to Figure 1b and Figures 2a and 2b, which are schematic representations of examples of post fixing in accordance with two other aspects of the present invention. Preferably, the first portion of bits has a length equal to a number of bits required to initialize a Viterbi decoder. As shown on Figure 2a, the first portion of bits may have a length equal to (2* a number of bits required to initialize the Viterbi decoder), i.e. x bits. In Figure 2b, the first portion of bits has a length equal to x bits, i.e. equal to a number of bits required to initialize the Viterbi decoder.

Returning now to Figure 1b, that aspect of the method 10 continues with decoding, at step 14, the convolutionally encoded sequence of bits and the appended first portion. As the first portion of the encoded sequence of bits has been post fixed to the sequence of bits to be decoded, the step of re- decoding is thus automatically performed when the decoding is performed. The method pursues at step 16 with replacing a part of the first portion of the sequence of bits after decoding with corresponding bits of the first portion appended at the end of the sequence of bits. Preferably, as first bits of the sequence are used to initialize the Viterbi decoder, it is the first bits of the first portion of the sequence of bits that are replaced. Then, in step 18, the appended first portion of bits is removed. The method then completes as on Figure 1 a with the step of outputting the decoded sequence of bits.

The decoding step 14 of Figures 1a and 1b is preferably performed using a Viterbi decoder. In an aspect of the invention, the Viterbi decoder can be a tail-biting decoder, while in another aspect of the invention, the decoder may consists more particularly of a zero-tailing tail-biting Viterbi decoder. Reference is now made concurrently to Figures 1a and 3, wherein Figure 3 represents a schematic block diagram of a decoder 30 in accordance with a first aspect of the present invention. Typically, the decoder 30 includes an input module 32 and an output module 34. The input module 32 and output module 34 can additionally be combined into an input/output port if desired. The input module 32 receives the convolutionally encoded sequence of bits 31 , and forwards it to a Viterbi decoder 36. The Viterbi decoder 36 is adapted to decode the encoded sequence of bits 31. In a first aspect of the present invention, the Viterbi decoder is a normal state "00" Viterbi decoder. The decoder 36 decodes the encoded sequence of bits 31 and re-decodes a first portion thereof. Then, the Viterbi decoder 36 sends the decoded sequence of bits 37 to a replacing module 38. The replacing module 38 is adapted to removing a part of the first portion of the sequence of bits after decoding and replace it with corresponding bits of the first portion which have been re- decoded. The decoded sequence of bits is then provided to the output module 34, which outputs the decoded sequence of bits, wherein the first portion of the decoded sequence of bits corresponds to re-decoded first portion of the sequence of bits.

Reference is now made concurrently to Figures 1b and 3, wherein Figure 3 represents a schematic block diagram of a decoder 30 in accordance with another aspect of the present invention. Typically, the decoder 30 includes an input module 32 and an output module 34. The input module 32 receives the convolutionally encoded sequence of bits 31 , and forwards it to an affixing module 35. The affixing module 35 is adapted to copy and append a first portion of the convolutionally encoded sequence of bits at an end of the convolutionally encoded sequence of bits. When that task is completed, the affixing module 35 forwards the resulting sequence of bits 33 to a Viterbi decoder 36. The Viterbi decoder 36 is adapted to decode the resulting sequence of bits 33, which corresponds to the convolutionally encoded sequence of bits with the appended first portion. Then, the Viterbi decoder 36 sends the decoded sequence of bits 37 to a replacing module 38. The replacing module 38 is adapted to removing a part of the first portion of the sequence of bits after decoding and replace it with corresponding bits of the first portion appended at the end of the sequence of bits which have also been decoded. The replacing module 38 may further be adapted to remove the first portion of the convolutionally encoded sequence of bits appended at the end of the convolutionally encoded sequence of bits. However, a deleting module 39, if preferred may also perform the removing of the appended first portion.

Reference is now made to Figure 4, which depicts a decoder in accordance with an aspect of the invention, in use in a modem. Typically, decoders such as the one of the present invention are used to communicate between computers. Computers communicate with one another either through a Local Area Network, through an Ethernet Network, through an Internet Protocol (IP) Network all of which being wired or wireless. As shown on Figure 4, a computer 40 is used to communicate with at least one other computer or server, through an IP network 42. For sake of clarity, the computer communicates with the IP network 42 wirelessly. The computer uses a modem 44 to connect and exchange data with the IP network 42. Modems, such as the modem 44 depicted in Figure 4, are composed of many different components, two of which are a decoder 46 and a buffer 48. Other components of the modem 44 will not be discussed herein, but those skilled in the art know the various possible components generally used in modems. Because of its simplicity and good accuracy, the decoder of the present invention is particularly interesting for use in the modem 40, and more particularly for the modem 40 being used with standards such as Wireless Broadband, OFDMA, etc. Since the decoder 46 of the present invention is a non-iterative decoder, it requires less processing capability and allows using a much smaller buffer 48 than in previous modem for tail-biting decoding. Reduction of the buffer and reduction of the required processing capability are important advantages for a successful decoder on the market.

Reference is now made to Figure 5, which exemplifies bit error rate results for a decoder in accordance with an aspect of the present invention. More particularly, the graph represents bit error rate curves computed through simulations for a Wireless Broadband OFDMA system. The graph shows results obtained for four different sets of modulation parameters. A first set of modulation parameters depicted is the Quadrature Phase-Shift Keying (QPSK) Vz tail-biting modulation, which is shown at reference 50. The second set of modulation parameters is the QPSK ^ΛA zero-tailing modulation, represented using reference 52. As can be appreciated, the QPSK ^ΛA tail- biting and QPSK ^ΛA zero-tailing show similar performances. A third set of modulation parameters depicted is the 64 Quadrature Amplitude Modulation (QAM) VA tail-biting modulation parameters, referenced 54. Finally, the fourth set of modulation parameters represented is the 64 QAM ³A zero-tailing modulation parameters, represented by reference 56. From this graph, it can o _{3 7} ,

- 11 -

be appreciated that the performances of the most robust modulation technique, i.e. QPSK, can sustain much more noise prior to being greatly affected by error. However, such robustness came at a price, as the throughput for QPSK was much lower than the 64QAM: 3.45 Mbps compared with 16 Mbps. Also, it is interesting to note in the graph that the bit error rate results obtained for each modulation techniques were rather similar between the tail-biting and the zero-tailing, proving the great advantage of the present invention with respect to simplicity and low costs, without sacrificing on performances. It is also of interest to note that as Frame Control Header of Wireless Broadband OFDMA messages are encoded using the QPSK ^ΛA tail- biting modulation, the bit error rate is good of the latter is considerably low as shown on the graph.

The present invention has been described by way of preferred embodiment. It should be clear to those skilled in the art that the described preferred embodiments are for exemplary purposes only, and should not be interpreted to limit the scope of the present invention. The method and decoder as described in the description of preferred embodiments can be modified without departing from the scope of the present invention. The scope of the present invention should be defined by reference to the appended claims, which clearly delimit the protection sought.

Claims

CLAIMS:

1. Method for decoding a convolutionally encoded sequence of bits, the method comprising steps of:

decoding the convolutionally encoded sequence of bits using a Viterbi decoder;

re-decoding a first portion of the convolutionally encoded sequence of bits, and

outputting the decoded sequence of bits, wherein outputted decoded first portion of the convolutionally encoded sequence of bits corresponds to re-decoded first portion of the convolutionally encoded sequence of bits.

2. The method of claim 1 , further comprising a prior step of:

copying and appending the first portion of the convolutionally encoded sequence of bits at an end of the convolutionally encoded sequence of bits.

3. The method of claim 2, wherein the outputting step comprises:

replacing a part of the first portion of the decoded sequence of bits with corresponding bits of the first portion appended at the end of the sequence of bits; and

removing the first portion of the convolutionally encoded sequence of bits appended at the end of the convolutionally encoded sequence of bits.

4. The method of claim 1 , wherein the Viterbi decoder is a zero-biting decoder.

5. The method of claim 1 , wherein the first portion of the convolutionally encoded sequence of bits has a length equal to a number of bits required to initialize the Viterbi decoder.

6. The method of claim 1 , wherein the first portion of the convolutionally encoded sequence of bits has a length equal to (2* a number of bits required to initialize the Viterbi decoder).

7. The method of claim 4, wherein the Viterbi decoder is a normal state "00" Viterbi decoder.

8. A decoder for decoding a convolutionally encoded sequence of bits, the decoder comprising:

an input port for receiving the convolutionally encoded sequence of bits;

a Viterbi decoder for decoding the convolutionally encoded sequence of bits and re-decoding a first portion of the convolutionally encoded sequence of bits; and

an output port for outputting the decoded convolutionally encoded sequence of bits, wherein the first portion of the decoded convolutionally encoded sequence of bits corresponds to re-decoded first portion of the convolutionally encoded sequence of bits.

9. The decoder of claim 8, further comprising:

an affixing module for copying and appending the first portion of the convolutionally encoded sequence of bits at an end of the convolutionally encoded sequence of bits; and

a replacing module for removing a part of the first portion of the sequence of bits after decoding and replacing with corresponding bits of the first portion appended at the end of the sequence of bits and removing the first portion of the convolutionally encoded sequence of bits appended at the end of the convolutionally encoded sequence of bits.

10. The decoder of claim 8, wherein the Viterbi decoder is normal state "00" Viterbi decoder.

11. The decoder of claim 8, wherein the first portion of the convolutionally encoded sequence of bits has a length equal to a number of bits required to initialize the Viterbi decoder.

12. The decoder of claim 8, wherein the first portion of the convolutionally encoded sequence of bits has a length equal to (2* a number of bits required to initialize the Viterbi decoder.

13. The decoder of claim 8, wherein the decoder is used in a Wireless Broadband capable modem.