WO2008069388A3 - Inverse mixcolumn block device and method of performing multiplication calculation using the same - Google Patents

Inverse mixcolumn block device and method of performing multiplication calculation using the same Download PDF

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Publication number
WO2008069388A3
WO2008069388A3 PCT/KR2007/003054 KR2007003054W WO2008069388A3 WO 2008069388 A3 WO2008069388 A3 WO 2008069388A3 KR 2007003054 W KR2007003054 W KR 2007003054W WO 2008069388 A3 WO2008069388 A3 WO 2008069388A3
Authority
WO
WIPO (PCT)
Prior art keywords
unit
block device
multiplication
outputs
inverse mixcolumn
Prior art date
Application number
PCT/KR2007/003054
Other languages
French (fr)
Other versions
WO2008069388A2 (en
Inventor
Jung-Hoon Oh
Yong-Su Lee
Young-Il Kim
Original Assignee
Korea Electronics Telecomm
Samsung Electronics Co Ltd
Jung-Hoon Oh
Yong-Su Lee
Young-Il Kim
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Korea Electronics Telecomm, Samsung Electronics Co Ltd, Jung-Hoon Oh, Yong-Su Lee, Young-Il Kim filed Critical Korea Electronics Telecomm
Publication of WO2008069388A2 publication Critical patent/WO2008069388A2/en
Publication of WO2008069388A3 publication Critical patent/WO2008069388A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
    • H04L9/0631—Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/12—Details relating to cryptographic hardware or logic circuitry

Abstract

The present invention relates to an Inverse MixColumn block device and a method of performing a multiplication operation using the same. According to an exemplary embodiment of the present invention, an Inverse MixColumn block device includes a storage unit that stores input data of a bit unit as a byte unit and outputs stored input bytes, a first multiplication operation block unit that performs and outputs multiplication operations of {01 }, {02}, {04}, and {08} as hexadecimal values for the input bytes that are received from the storage unit, a second multiplication operation block unit that performs and outputs multiplication operations of {09}, {0b}, {0d}, and {0e} as hexadecimal values by using the {01 }, {02}, {04}, and {08} multi¬ plication operation results received from the first multiplication operation block unit, and an exclusive logical sum operation unit that performs an exclusive logical sum operation on the {09}, {0b}, {0d}, and {0e} multiplication operation results received from the second multi¬ plication operation block unit and outputs output bytes for the input bytes. As such, if the Inverse MixColumn block device composed of a multiplier is implemented by simple hardware modules, encryption performance can be improved, and the Inverse MixColumn block device can be easily used in a portable apparatus that has a small size and low power consumption.
PCT/KR2007/003054 2006-12-06 2007-06-25 Inverse mixcolumn block device and method of performing multiplication calculation using the same WO2008069388A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2006-0122860 2006-12-06
KR1020060122860A KR100840944B1 (en) 2006-12-06 2006-12-06 MixColum block device and method of multiplication calculation thereof

Publications (2)

Publication Number Publication Date
WO2008069388A2 WO2008069388A2 (en) 2008-06-12
WO2008069388A3 true WO2008069388A3 (en) 2009-07-30

Family

ID=39492740

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2007/003054 WO2008069388A2 (en) 2006-12-06 2007-06-25 Inverse mixcolumn block device and method of performing multiplication calculation using the same

Country Status (2)

Country Link
KR (1) KR100840944B1 (en)
WO (1) WO2008069388A2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030099352A1 (en) * 2001-10-04 2003-05-29 Chih-Chung Lu Apparatus for encryption and decryption, capable of use in encryption and decryption of advanced encryption standard
US20060198524A1 (en) * 2003-05-14 2006-09-07 Sexton Bonnie C Hardware implementation of the mixcolumn/invmiscolumn functions

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030099352A1 (en) * 2001-10-04 2003-05-29 Chih-Chung Lu Apparatus for encryption and decryption, capable of use in encryption and decryption of advanced encryption standard
US20060198524A1 (en) * 2003-05-14 2006-09-07 Sexton Bonnie C Hardware implementation of the mixcolumn/invmiscolumn functions

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
"Proceedings of the IEEE International Conference on Application- Specific Systems, 17-19 July 2002", article CHIH-CHUNG LU ET AL.: "Integrated Design of AES (Advanced Encryption Standard) Encrypter and Decrypter", pages: 277 - 285 *

Also Published As

Publication number Publication date
KR20080051537A (en) 2008-06-11
WO2008069388A2 (en) 2008-06-12
KR100840944B1 (en) 2008-06-24

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