WO2008067066A2

WO2008067066A2 - Wireless communication unit and method for detecting a synchronisation signal

Info

Publication number: WO2008067066A2
Application number: PCT/US2007/081814
Authority: WO
Inventors: Alexander Radus
Original assignee: Motorola, Inc.
Priority date: 2006-11-29
Filing date: 2007-10-18
Publication date: 2008-06-05
Also published as: WO2008067066A3; WO2008067066B1; GB2444303B; GB2444303A; GB0623824D0

Abstract

A wireless communication unit (100) comprises a receiver operably coupled to a signal processor comprising logic (205) to perform a fast Fourier transform on a received signal from a second wireless communication unit. The logic (205) is operably coupled to signal determination logic (210) arranged to compare a fast Fourier transform signal to a number of stored fast Fourier transform signals. In response thereto the signal determination logic (210) determines whether to further process the received signal to acquire synchronisation with a transmission of the second wireless communication unit. A method of detecting a synchronisation signal is also provided.

Description

WIRELESS COMMUNICATION UNIT AND METHOD FOR DETECTING A

SYNCHRONISATION SIGNAL

TECHNICAL FIELD This invention relates to a wireless communication unit and a method for detecting a synchronisation signal. In particular, the invention is applicable to, but is not limited to, detecting a synchronisation signal of a wireless communication unit operating in a wireless communication system, such as a private mobile radio TETRA system and/or a cellular system such as a GSM communication system.

BACKGROUND Wireless communication systems, for example cellular telephony or private mobile radio (PMR) communication systems, typically provide for radio telecommunication links to be arranged between a number of mobile wireless communication units, often referred to as ^λmobile stations' (MSs) . In wireless communication systems, a method of communicating between the MSs typically involves use of one or more intermediary stations to forward a received communication from a first MS to a second MS, as provided in ^λtrunked mode' communication or repeater-based direct mode (DM) communication in a PMR communication system or in a mobile cellular telephone communication system.

In a wireless private mobile radio (PMR) communication system timing mechanisms are typically used. For example, where the wireless PMR communication system operates in accordance with the TErrestrial Trunked RAdio (TETRA) standard defined by the European Telecommunications Standards Institute (ETSI), the TETRA timing structure uses a time division multiple access (TDMA) protocol. Symbol Timing Recovery (STR) is employed and is a procedure by which the receiving MS adjusts its clock timing to match the transmitting MS's timing scheme. Receiving, processing and possibly adapting a clock timing, is performed at least once every multi-frame (eighteen frames) according to the TETRA standard.

Within these transmission patterns the TETRA standard specifies a surveillance and synchronisation

(sync) acquisition method. A surveillance pattern is a sequence of radio frequency (RF) signal reception intervals (i.e. a periodicity of sampling a RF channel) where a radio unit attempts to determine the state of the RF channel. Notably, the TETRA standard specifies a surveillance and sync, acquisition method that is based upon a MS scanning a range of frequencies and detecting any generic radio communication emission from a serving base transceiver station (BTS) . For each frequency channel the MS measures the received signal power, which may therefore include any random RF noise or interfering signal .

If the received signal strength of the signal on the channel exceeds a threshold, the MS tries to scan the channel for several frames and to decode system information transmitted by the infrastructure. In order to determine a state of a TETRA RF channel, a TETRA radio samples the RF channel once every 56.7/5 milliseconds (i.e. five times a frame, for approx. two milliseconds each sample) . By sampling the RF channel at this periodicity, the detection of any available radio energy, within a selected frequency range and between prescribed signal strength thresholds, is essentially assured, in that a TETRA transmission burst from an operational TETRA radio unit will be sampled twice. Upon detection of a desired BTS emission, the proposed and standardised method then dictates a transition of the detecting TETRA radio unit into a synchronisation acquisition mode of operation .

In the current known technique the MS attempts to find in the received signal a well known pattern (training sequence) by simple calculation of a cross correlation function. The MS performs this operation for each incoming sample. As the scanning of each channel usually takes several frames (up to 0.5 seconds in TETRA) , and as there are a large number of frequency channels, the whole procedure of finding of a valid infrastructure signal may take a long time. Nonetheless, as a result of this scanning, the MSs may sample and detect RF channels that do not contain a valid BTS signal, where the RF channel exhibits a high level of electromagnetic power that may exceed the threshold due to, say, a presence of an unknown source of electromagnetic radiation, for example a welder.

In addition, within the TETRA standard there is an operational mode termed "idle dual watch". In idle dual watch mode an MS that is already synchronized with the infrastructure is required to simultaneously scan both the trunked mode channel and a DMO (direct mode operation) channel, so that it is able to transfer to a direct mode call if one becomes available. In an idle dual watch mode of operation the same problem as above occurs. However, the impact in the idle dual watch mode may be much worse on some functional aspects of the MS. For example, if the MS encounters a high signal level on the DMO channel, it begins to scan the DMO channel in order to decode a downlink synchronization burst of the transmitting MS. This may take several frames, during which time the MS is not listening to the infrastructure (serving BTS) and thus may not receive useful signalling data that is being sent to the MS. If there is a constant strong ^λnon-TETRA' signal on the DMO channel, the MS will transition into this ^λscanning' mode often, which will increase the probability of going out of synchronisation with the infrastructure. Thus, the current known synchronisation acquisition methods may be summarised as:

(i) Energy wise wasteful, for most of the channel monitoring time, as the MS may perform scanning and detecting and synchronisation acquisition routines on emissions that were not related to a transmitting BTS (or other MS) ; and

(ii) Wasteful of processing time, e.g. central processing unit (CPU) cycles, for most of the channel surveillance time, for the same reasons as given above, which decreases valuable battery life time of the MS.

Thus, there exists a need to provide a wireless communication unit and an improved method of detecting a synchronisation signal wherein the aforementioned disadvantages may be alleviated.

SUMN[ARY OF THE INVENTION

According to the present invention in a first aspect there is provided a wireless communication unit as defined in claim 1 of the accompanying claims. According to the present invention in a second aspect there is provided a method of detecting a synchronisation signal, the method of detecting a synchronisation signal being as defined in claim 8 of the accompanying claims.

According to the present invention in a third aspect there is provided a storage medium as defined in claim 14 of the accompanying claims.

Further features of the invention are as defined in the accompanying dependent claims and are disclosed in the embodiments of the invention to be described.

Embodiments of the present invention will now be described by way of example with reference to the accompanying drawings, in which:

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying figures, where like reference numerals refer to identical or functionally similar elements throughout the separate views and which together with the detailed description below are incorporated in and form part of the specification, serve to further illustrate various embodiments and to explain various principles and advantages all in accordance with the present invention.

FIG. 1 illustrates a wireless communication unit adapted in accordance with embodiments of the invention. FIG. 2 illustrates a receiver architecture of a wireless communication unit adapted in accordance with embodiments of the invention.

FIG. 3 illustrates an impulse response of a cosine roll off filter employed by a signal processor in accordance with embodiments of the invention. FIG. 4 illustrates an amplitude of a base band TETRA signal, for a bit sequence 0000101000, as processed by a signal processor in accordance with embodiments of the invention . FIG. 5 illustrates a baseband signal, for a bit sequence 0000101000, as processed by a signal processor in accordance with embodiments of the invention.

FIG. 6 illustrates an amplitude of the base band signal for the bit sequence 0000101000 in a frequency domain as processed by a signal processor in accordance with embodiments of the invention.

FIG. 7 illustrates an amplitude of the base band signal, for the sequence 01010101010000000000, as processed by a signal processor in accordance with embodiments of the invention.

FIG. 8 illustrates a real version of a base band signal for the sequence 01010101010000000000, as processed by a signal processor in accordance with embodiments of the invention.

DESCRIPTION OF EMBODIMENTS OF THE INVENTION

Before describing in detail embodiments that are in accordance with the present invention, it should be observed that the embodiments reside primarily in combinations of method steps and apparatus components related to a method and apparatus for detecting a synchronisation signal. Accordingly, the apparatus components and method steps have been represented where appropriate by conventional symbols in the drawings, showing only those specific details that are pertinent to understanding the embodiments of the present invention so as not to obscure the disclosure with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein. Thus, it will be appreciated that for simplicity and clarity of illustration, common and well-understood elements that are useful or necessary in a commercially feasible embodiment may not be depicted in order to facilitate a less obstructed view of these various embodiments.

It will be appreciated that embodiments of the invention described herein may be comprised of one or more generic or specialized processors (or "signal processors") such as microprocessors, digital signal processors, customized processors and field programmable gate arrays (FPGAs) and unique stored program instructions (including both software and firmware) that control the one or more processors to implement, in conjunction with certain non-processor circuits, some, most, or all of the functions of the method and apparatus for detecting a synchronisation signal described herein. The non-processor circuits may include, but are not limited to, a radio receiver, a radio transmitter and user input devices. As such, these functions may be interpreted as steps of a method to perform the detecting of a synchronisation signal described herein. Alternatively, some or all functions could be implemented by a state machine that has no stored program instructions, or in one or more application specific integrated circuits (ASICs) , in which each function or some combinations of certain of the functions are implemented as custom logic. Of course, a combination of the two approaches could be used. Both the state machine and ASIC are considered herein as a "signal processor" for purposes of the foregoing discussion and claim language .

Moreover, an embodiment of the present invention can be implemented as a computer-readable storage element or medium having computer readable code (e.g., processor- implementable instructions) stored thereon for programming a computer (e.g., comprising a signal processor) to perform a method as described and claimed herein. Examples of such computer-readable storage elements include, but are not limited to, a hard disk, a CD-ROM, an optical storage device and a magnetic storage device. Further, it is expected that one of ordinary skill, notwithstanding possibly significant effort and many design choices motivated by, for example, available time, current technology, and economic considerations, when guided by the concepts and principles disclosed herein will be readily capable of generating such software instructions and programs and ICs with minimal experimentation .

Generally speaking, the various embodiments provide a wireless communication unit and improved method of detecting a synchronisation signal that uses the validation of a received electromagnetic signal during a signal level measurement phase, which occurs before entering a scanning phase. Embodiments of the invention are illustrated with reference to a TETRA communication system. As the described TETRA signal strength measurement takes only a few milliseconds, the improved synchronisation signal detecting method is much more efficient and effective than known techniques.

Although embodiments of the invention are described with reference to a wireless TETRA subscriber unit, it is within the contemplation of the invention that the inventive concept can be applied equally to other wireless communication units, such as cellular phones compliant with the Global System for Mobile communications (GSM) cellular communication standard, as well as other units, communication standards and associated timing structures. Referring now to FIG. 1, there is shown a block diagram of a wireless TETRA subscriber communication unit 100 adapted to support the inventive concept of the embodiments of the invention. The wireless subscriber unit 100 includes an antenna 102 that in this embodiment is coupled to a duplex filter or antenna switch 104 that provides isolation between a receiver chain 110 and a transmitter chain 120 within the wireless subscriber unit 100. As is known in the art, the receiver chain 110 typically includes receiver front-end circuitry 106 (effectively providing reception, filtering and intermediate or base-band frequency conversion) . The front-end circuit is serially coupled to signal processing logic (typically implemented as a digital signal processor) 108. An output from the signal processing logic 108 is provided to a user-interface 130, which may comprise a display, loudspeaker, etc.

The receiver chain 110 also includes received signal strength indicator (RSSI) circuitry 112 (shown coupled to the receiver front-end 106, although the RSSI circuitry 112 could be located elsewhere within the receiver chain 110) . The RSSI circuitry is further coupled to the signal processing function 108. Also included within the receiver chain 110 is a controller 114. The controller 114 is arranged to perform overall functional control of the wireless TETRA subscriber communication unit 100. The controller 114 is coupled to the receiver front-end circuitry 106, the signal processing function 108 and also to a memory device 116 in the receiver chain 110. The memory device 116 stores operating regimes, such as decoding/encoding functions and the like. A timer 118 is coupled to the controller 114 to control the timing of operations (transmission or reception of time-dependent signals) within the wireless subscriber unit 100.

As regards the transmit chain 120, this essentially includes a user-interface 130 comprising elements such as a microphone, keypad, etc. coupled in series to a transmitter/ modulation circuit 122. Thereafter, any transmit signal is passed through a RF power amplifier 124 to be radiated from the antenna 102. The transmitter/ modulation circuitry 122 and the power amplifier 124 are operationally responsive to the controller 114, with an output from the power amplifier 124 coupled to the duplex filter or antenna switch 104. The transmitter/ modulation circuitry 122 and receiver front-end circuitry 106 comprise frequency up-conversion and frequency down-conversion functions (not shown) .

In accordance with embodiments of the invention, the signal processing logic 108 has been adapted to detect and acquire synchronisation with significantly less processing than used to detect a synchronisation signal in known detect and acquire synchronisation methods.

Notably the receiver front-end circuitry 106 receives a radio frequency signal and down converts the signal to a baseband signal. The signal processor function 108 then processes the baseband signal and is able to determine, without demodulating and decoding the received signal, that it is a TETRA (or in alternative embodiments a GSM) signal.

Referring now to FIG. 2, a block diagram of receiver signal processing logic 108 of a wireless communication unit is shown that is adapted in accordance with the inventive concept of the invention. The receiver signal processing circuit 108 comprises a series of RF receiver circuits grouped and shown as receiver RF block 250, receiving an RF input signal that has been transmitted from, and the transmit baseband signal filtered by, a sender side. The receiver RF block 250 in this embodiment includes RF amplification, RF down-mixing, appropriate filtering to filter out unwanted adjacent- channel signals and an analog-digital (A/D) converter for conversion of the analogue signal to a digital equivalent .

Notably, in accordance with embodiments of the invention, FFT logic 205 is introduced into the receive path at an early stage. In this regard, a fast Fourier transform (FFT) is performed on the digital signal output from the RF block 250, in FFT logic 205. FFT logic 205 outputs a signal to a symbol timing recovery block 252. Thus, and advantageously, in accordance with embodiments of the invention, an additional step of analyzing the spectra characteristics of the received signal is performed, using FFT logic 205, to determine whether any further processing of the signal is worthwhile.

In accordance with one embodiment of the invention, FFT logic 205 is operably coupled to signal determination logic 210. In particular, the signal determination logic 210 analyses a behaviour of the respective amplitude of the received baseband signal in a frequency domain

(provided by FFT logic 205), as illustrated in FIG. 4, in order to identify different bit sequences. Notably, the signal determination logic 210 determines whether there is minimal amplitude change in the baseband signal. For example, if the signal determination logic 210 identifies that there is only a small variation in amplitude; the signal determination logic 210 interprets this as a small phase transition in the received signal. Thus, in this manner, the signal determination logic 210 is able to identify whether the received signal is a desired signal (e.g. one that may exhibit a supported training sequence) and decide whether further processing of the received signal is to be performed.

If further processing of the signal is deemed to be worthwhile, for example in response to identifying that the FFT of the received signal exhibits a particular desired profile, the following known operations are performed. Symbol timing recovery function is performed, which is important to the receiving process in that it samples the received data at optimal times and thereby prevents inter-symbol interference (ISI) between bits in the received data stream. A cross-correlation function 251 is connected to the symbol timing recovery block 252 to perform timing recovery. In known synchronisation acquisition techniques the cross-correlation function 251 is configured to compare two received training/ synchronisation sequences at the beginning and middle of a received slot to pre-stored training/ synchronisation sequences. In the classical approach the cross- correlation function 251 searches for a so called training sequence in the received base band signal. A training sequence is a well known bit pattern (as indicated in the TETRA standard) .

Once the correct symbol timing and frequency error estimation has been determined from the cross-correlation logic 251, the received data block is input to a demodulator 254. The demodulator 254 demodulates the received TETRA signal, in this case a TETRA pi/4 differential quadrature phase shift keyed (DQPSK) signal. In the demodulator 254, impulse response curves of the received signal are generated.

The impulse response curves are weighted by complex coefficients, according to a quadrature phase shift keyed (QPSK) table, as detailed in Table 1 below, and passed through a baseband filter (not shown) . At the output of the baseband filter a sum of complex weighted impulse responses is obtained, with the feature that at times kT the k-th symbols are not interfered by adjacent symbols, as shown in FIG. 3.

The output of the demodulator 254 then provides a signal to an automatic frequency control 256 (AFC) circuit to estimate, and compensate for, a frequency shift between the received signal and the receiver' s local oscillator. A similar output may be provided to an automatic gain control (AGC) circuit, not shown, to ensure that the received signal levels are at an optimal amplitude level so that the received signal is maintained in the linear regions of the receiver's RF circuits. The demodulator 254 also outputs a series of demodulated symbols that are input to differential decoder 258 for conversion into a series of demodulated bits. The output of the differential decoder 258, in the form of modulation bits, is fed into a burst builder 260 to restore the transmitted bursts of data into a series of multiplexed bits which is, in turn, input to a logical channel (LCH) de-multiplexer 262 to generate a series of scrambled bits. The series of scrambled bits output from the LCH de-multiplexer 262 is input to de-scrambler 264 to provide a series of received bits that are still interleaved. Up to this point, the receiving functions have all been carried out at the physical channel level of the well-known OSI model. The remaining steps/circuits of the receiver process are carried out within the medium access control (MAC) 266 layer.

The output from the de-scrambler 264 is input to a de-interleaver 268 in the MAC layer 266 for de- interleaving the blocks of bits. The de-interleaving process operates on one time division multiplexing (TDM) slot of received sub-channel symbols. These bits are reordered in a re-ordering block 270 to provide encoded bits ready for decoding in a decoder 272. The decoder function may involve a number of decoding operations such as cyclic redundancy checking (CRC) , Viterbi decoding, forward error correction (FEC) decoding, etc.

Finally, if the received signal was encrypted for security purposes, the information bits output from the decoder 272 are input to a decryption block 274. If the received signal was a speech signal, the output of the decryption block is input to a speech decoder (not shown) to provide the user with an audible signal.

In prior art receivers, a majority, if not all, of the above operations 250-274 were necessary in order for the receiver' s processor to determine whether the received message is intended for the respective user. The above operations were also carried out irrespective of whether the information received contained any new worthwhile information, for example information that the receiver has not previously received.

However, following the introduction of FFT logic 205, the above receiver operations are no longer required to identify whether a received signal is valid, as the FFT logic 205 followed by a comparison of the FFT of the received signal with known FFT profiles, pre-empts such processing. In summary, the TETRA baseband signal may be depicted as follows:

B(t)=∑a_kg(t-kT)

Where :

^represents the k-th symbol comprising two bits of

information to be transferred. a_k=a_k__ιeχ^ [2] φ is equal to the phase shift between two adjacent symbols calculated according to the scheme illustrated in

Table 1.

Table 1 : QPSK phase increment according to recovered bits:

and g(t-kT) is the impulse response of the cosine roll- off filter on the k-th symbol, where the period T is 1/18000 msec, according to the TETRA symbol rate.

A base band filter of the transmit side, which may be implemented as a cosine roll-off filter, is illustrated by a graph 300 shown in FIG. 3. The impulse response of a current symbol 305 is illustrated, with a previous symbol located at 310 and a subsequent symbol located at 315. The previous symbol and subsequent symbol do not have a zero amplitude value. At the times kT the adjacent symbols are not affected by each other as their impulse responses converge to zero (Nyquist criteria) .

Notably, the signal determination logic 210 may determine whether there is minimal amplitude change in the baseband signal. For example, if the signal determination logic 210 identifies that there is only a small variation in amplitude; the signal determination logic 210 may interpret this as a small phase transition in the received signal. In recovering the QPSK signal, as detailed above in Table 1, such an interpretation may be understood as equating to a +/-Pi/4 transition between symbols, as would be found, for example, in the bit sequence 00 00 10 10 00. It is envisaged that the inventive concept of the invention may be applied to any constant amplitude modulation scheme where the symbols are located on a unit circle, as would be appreciated by a skilled artisan.

FIG. 4 illustrates a graph 400 of the aforementioned bit sequence (00 00 10 10 00) of a received QPSK baseband signal, as processed by the signal determination logic 210 in accordance with embodiments of the invention. Thus, the signal determination logic 210 is able to interpret the type of signal, in this case that it is a QPSK signal, by interpreting the amplitude values of the aforementioned bit sequence, e.g. symbol ^λ00' (amplitude 405), followed by symbol ^λ00' (amplitude 410), followed by symbol ^λ10' (amplitude 415), followed by symbol ^λ10' (amplitude 420), and followed by symbol ^λ00' (amplitude 425) .

Referring now to FIG. 5, a graph 500 illustrates the aforementioned baseband signal (shown as 505) being represented in the frequency domain. Here, it is clear that the energy of the amplitude signal, with +/-Pi/4 phase transitions, is concentrated at the centre frequency ^λ0' .

In accordance with embodiments of the invention, and based on this FFT profiling of the amplitude signal of the base band signal, the signal determination logic is able to compare an FFT of the received signal to a number of stored FFT signals (for example FFT profiles stored in memory device 116 of FIG. 1) . Thus, the following method is introduced to distinguish whether a received signal is a valid or an invalid received signal.

In accordance with embodiments of the invention, the wireless communication unit is arranged to measure signal strength of a received signal. This measurement may be performed for, say, several milliseconds. If the strength of the signal is below a pre-determined threshold, then it is proposed that the wireless communication unit does not perform any further signal processing on the received signal. If the strength of the signal is above a predetermined threshold, then FFT logic (205) performs a fast Fourier transform of the amplitude of the baseband signal for the portion of signal received in the previous step . Signal determination logic, operably coupled to the FFT logic then determines whether the FFT signal demonstrates an expected profile in the frequency domain by comparing the FFT signal with one or more other FFT signals stored in the communication unit. If it does, then the signal determination logic arranges for the wireless communication unit to enter a channel scanning mode of operation, by commencing to look for a valid downlink burst. For example, FIG. 6 illustrates a graph 600 of an amplitude of the baseband signal for a bit sequence 01 01 11 11 01 in a frequency domain, as processed by a signal processor in accordance with embodiments of the invention. Here, the energy of the signal is concentrated at the frequencies of 0 kHz 605 and +/-18 kHz 610, 615, thereby indicating phase transitions of +/-3*Pi/4.

If the wireless communication unit receives a signal above the threshold, and the FFT signal does not match an expected FFT profile stored in, say, the memory device, the signal determination logic wireless communication unit immediately assumes that the received signal is a non-TETRA signal, and prevents further signal processing on the received signal, i.e. it prevents the signal being passed to the symbol timing recovery logic 252 and subsequent receiver logic illustrated in FIG. 2.

Following the signal determination logic matching the FFT of the received signal to a stored profile, the signal determination logic analyzes a behaviour of the amplitude of the base band signal in the frequency domain to identify different bit sequences. Thus, the signal determination logic is able to identify how the amplitude of the baseband signal changes. For example, if the signal determination logic determines that the baseband signal only changes slightly, the signal determination logic may assume that the phase transitions equate to +/- Pi/4, as for example for the bit sequence 00 00 10 10 00.

FIG. 7 illustrates a graph of an amplitude of a baseband signal 700, for an alternative sequence 01010101010000000000, which may be processed by the signal determination logic in accordance with embodiments of the invention. The equivalent bit sequence 01010101010000000000, as processed by the signal processor, is illustrated in the graph 800 of FIG. 8. Thus, a skilled person will appreciate that a number of different FFT profiles may be used by the signal determination logic to try to identify a bit sequence of a desired received signal, with any number of bits in the bit sequence being used in the profile comparison.

Thus, in accordance with one embodiment of the invention, the wireless communication unit 100 is able to activate its receiver for a short period of time, in order to identify whether a received signal is a desired synchronisation signal, and, in response thereto, align its real time clock to the actual BTS sync burst boundaries in order to synchronise to a transmission of the second wireless communication unit. The alignment of a real-time clock to identified timing points or boundaries indicated in the BTS transmission may be implemented by any known clock adjustment method.

It is envisaged that the various adapted components within the TETRA wireless communication unit may be realised in discrete or integrated component form. More generally, the functionality associated with detecting a TETRA BTS transmission type, may be implemented in a respective wireless communication unit in any suitable manner. For example, new apparatus may be added to a conventional communication unit, or alternatively existing parts of a conventional communication unit may be adapted, for example by reprogramming one or more processors 108 therein. As such, the required adaptation may be implemented in the form of processor-implementable instructions stored on a storage medium, such as a floppy disk, hard disk, programmable read-only memory (PROM) , random access memory (RAM) or any combination of these or other storage media. It is within the contemplation of the invention that the inventive concepts described herein can be applied in both TETRA and GSM radios, where an improvement in detecting a desired signal may be gained by the wireless communication unit, by performing a signal validity test, followed by a frequency domain FFT analysis to identify whether the FFT analysis matches a stored FFT profile.

It will be understood that the wireless communication unit and method of performing synchronisation acquisition therein, as described above, may provide one or more of the following exemplary advantages :

(i) By employing the inventive concept herein described it is possible for a wireless communication unit to significantly reduce a time needed to synchronize itself with associated infrastructure.

(ii) Employing synchronisation signal detection using the inventive concept herein described requires much lower power consumption. (iϋ) Employing synchronisation signal detection using the inventive concept herein described saves battery life of the wireless communication unit.

It will be appreciated that references to specific functional devices or elements are only to be seen as references to suitable means for providing the described functionality, rather than indicative of a strict logical or physical structure or organization of components.

Aspects of the invention may be implemented in any suitable form. The signal determining logic, for example, may be located in any portion of the receiver chain and may be physically, functionally and/or logically implemented in any suitable manner. In the foregoing specification, specific embodiments of the present invention have been described. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention. The benefits, advantages, solutions to problems, and any element (s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential features or elements of any or all the claims. The invention is defined solely by the appended claims including any amendments made during the pendency of this application and all equivalents of those claims as issued.

Moreover in this document, relational terms such as first and second, top and bottom, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms "comprises," "comprising," "has", "having," "includes", "including," "contains", "containing" or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises, has, includes, contains a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises ...a", "has ...a", "includes ...a", "contains ...a" does not, without more constraints, preclude the existence of additional identical elements in the process, method, article, or apparatus that comprises, has, includes, contains the element. The terms "a" and "an" are defined as one or more unless explicitly stated otherwise herein. The terms "substantially", "essentially", "approximately", "about" or any other version thereof, are defined as being close to as understood by one of ordinary skill in the art, and in one non-limiting embodiment the term is defined to be within 10%, in another embodiment within 5%, in another embodiment within 1% and in another embodiment within 0.5%. The term "coupled" as used herein is defined as connected, although not necessarily directly and not necessarily mechanically. A device or structure that is "configured" in a certain way is configured in at least that way, but may also be configured in ways that are not listed.

Claims

1. A wireless communication unit (100) comprises a receiver operably coupled to a signal processor (108) for processing a received radio frequency (RF) signal from a second wireless communication unit, wherein the wireless communication unit (100) is characterised in that the signal processor (108) comprises logic (205) to perform a fast Fourier transform where the logic (205) is operably coupled to signal determination logic (210) arranged to compare the fast Fourier transform signal to a number of stored fast Fourier transform signals and in response thereto determines whether to further process the received RF signal to synchronise to a transmission of the second wireless communication unit.

2. The wireless communication unit (100) of Claim 1 wherein the signal determination logic (210) is arranged to generate a sequence of impulse response curves of the fast Fourier transform signal and in response thereto analyse a behaviour of the received signal in a frequency domain .

3. The wireless communication unit (100) of Claim 2 wherein the signal determination logic (210) analyses the behaviour of the received signal in order to identify a bit sequence of the received signal.

4. The wireless communication unit (100) of any preceding claim wherein the signal determination logic (210) distinguishes between a valid received RF signal and an invalid received RF signal by comparing the fast Fourier transform signal to a plurality of stored fast Fourier transform signals.

5. The wireless communication unit (100) of any preceding claim wherein the wireless communication unit (100) is capable of communicating in accordance with the TErrestrial Trunked RAdio (TETRA) standard.

6. The wireless communication unit (100) of any of preceding Claims 1 to 4, wherein the wireless communication unit (100) is capable of communicating in accordance with the Global System for Mobile communications (GSM) standard.

7. The wireless communication unit (100) of any preceding claim where the wireless communication unit (100) is a mobile station.

8. A method (200) of detecting a synchronisation signal comprising: receiving a radio frequency (RF) signal at a first wireless communication unit; and processing the received radio frequency (RF) ; and wherein the method is characterised by: performing (205) a fast Fourier transform on the received RF signal; comparing (210) the fast Fourier transform signal to a number of stored fast Fourier transform signals, and in response thereto determining (210) whether to further process the received RF signal to synchronise to a transmission of a second wireless communication unit.

9. The method (200) of Claim 8 further comprising generating a sequence of impulse response curves of the fast Fourier transform signal and in response thereto analysing a behaviour of the received signal in a frequency domain.

10. The method (200) of Claim 9 further comprising analysing the behaviour of the received signal in order to identify a bit sequence of the received signal.

11. The method (200) of any of preceding Claims 8 to 10 further comprising distinguishing between a valid received RF signal and an invalid received RF signal in response to comparing the fast Fourier transform signal to a number of stored fast Fourier transform signals.

12. The method (200) of any of preceding Claims 8 to 11 wherein the first wireless communication unit (100) is capable of communicating in accordance with the TErrestrial Trunked RAdio (TETRA) standard.

13. The method (200) of any of preceding Claims 8 to 12 wherein the wireless communication unit (100) is capable of communicating in accordance with the Global System for Mobile communications (GSM) standard.

14 A storage medium storing processor-implementable instructions for controlling a signal processor to carry out the method of any of Claims 8 to 13.