WO2008061314A1

WO2008061314A1 - Addressing apparatus and methods

Info

Publication number: WO2008061314A1
Application number: PCT/AU2007/001800
Authority: WO
Inventors: Ronald Barry Zmood
Original assignee: Mems-Id Pty Ltd
Priority date: 2006-11-24
Filing date: 2007-11-23
Publication date: 2008-05-29

Abstract

A programmable memory device (10) including an array of memory elements (12), and a plurality of address elements (16) for addressing said memory elements, wherein said address elements are activated by a programming signal and are frequency-sensitive, such that said memory elements can be selectively addressed to change their states by the application of one or more programming signals having one or more predetermined frequency components that selectively activate one or more of said address elements.

Description

ADDRESSING APPARATUS AND METHODS

The present invention relates to addressing apparatus and methods, e.g. for recording data on a memory device. It relates especially, although not exclusively, to apparatus and methods for encoding data on micromechanical arrays. Such arrays may for example be used in RFID tags.

WO 2004/084131 and WO 2004/083798, both to an inventor of the present application, describe memory devices and temperature sensing devices that utilise arrays of resonant members to represent data. These members may take the form of cantilever and bridge structures, and may have different resonant frequencies from one another so that the presence or absence of a vibratable resonant member of a particular frequency may be equated to a logical "1 " or "0", and may represent binary code, a status flag or the like. A determination of the presence or absence of a member may be made by applying an excitation signal to the array and by analysing a response to determine if it is indicative of a particular member's frequency.

Data may be encoded into these arrays in a number of ways, e.g. by fabricating members only of particular frequencies, by making members with a full range of frequencies and by then destroying particular members, or by enabling or disabling the ability of particular members to vibrate, e.g. by using a removable tether.

Resonant members are also disclosed in US 5481102, US 5552778, US 5563583, US 5565847 and US 6819246, and the contents of these documents, and of WO 2004/084131 and WO 2004/083798, are incorporated herein in their entirety by reference.

The present invention relates to addressing apparatus and methods, and may provide apparatus and methods for encoding data. The apparatus and methods may for example be used with the above-mentioned resonant members, but may also have broader applications. Viewed from one aspect, the present invention provides a programmable memory device including an array of memory elements, and a plurality of address elements for addressing said memory elements, wherein said address elements are activated by a programming signal and are frequency-sensitive, such that said memory elements can be selectively addressed to change their states by the application of one or more programming signals having one or more predetermined frequency components that selectively activate one or more of said address elements.

The present invention allows for example an array of resonant members, e.g. as disclosed in WO 2004/084131 , to be programmed by applying a programming signal of appropriate frequencies to the device, such that a select number of the address elements are activated to pass a current to tethers of associated resonant members. The current will then fuse the tethers and release the selected resonant members, so that they can respond to interrogation signals, thereby encoding the array.

Each memory element may have a dedicated address element associated with it. Alternatively, the memory elements may be activated by a 2D array of address lines, e.g. in columns and rows or bit lines and word lines, with each address element associated with a particular address line, such that the appropriate activation of address elements will address a particular memory element, e.g. by passing an appropriate fusing current through a tether of the memory element.

The programming signal may be applied as an electrical input to external programming connection terminals of the memory device. The programming signal may also be applied in a contactless manner, e.g. as an electromagnetic signal, e.g. an RF signal, or as an acoustic signal.

The programming signal may be applied directly to the address elements, e.g. if the resonant members are activated magnetically or acoustically, or may be applied to an antenna circuit, e.g. to induce an electrical current in the antenna circuit that may then be input to the address elements.

Each address element could have a dedicated set of contacts for an electrical current input signal or could have a dedicated antenna circuit. Preferably, address elements are associated with a common conductor for receiving an electrical current from a common pair of electrical contacts or from a common antenna circuit. Address elements may therefore be associated with a common input conductor on which a programming signal may be placed, e.g. as derived from an antenna circuit or as input by a direct electrical contact. All of the address elements may be associated with a common input conductor, or groups of address elements may be associated with their own respective input conductor, e.g. one input conductor for row address elements and one for column address elements.

An advantage of using frequency-sensitive address elements is that they allow memory devices to be programmed after they have been fully fabricated. Also, they allow memory devices to be programmed in a contactless manner, or, when electrical contacts are used, allow the number of contacts to be reduced, e.g. to two for a single common input conductor.

The present invention facilitates the encoding of memory devices in the field, and is especially advantageous in the field of RFID tags, as it allows tags to be encoded with data after they have been fabricated and packaged.

An address element may include a mechanical resonant member, such as used as data elements in WO 2004/084131 , the resonant member acting as a frequency selection device. Thus, the resonant member may resonate in accordance with the frequency components of an input signal so as to provide an output signal to a memory element when a frequency of the input signal matches a resonant frequency of the member. An advantage of this is that the resonant members of the address elements may be fabricated at the same time as resonant members used to provide the memory elements.

The resonant member may be made to vibrate in any suitable manner. Various types of resonant member and methods of vibration are for example disclosed in WO 2004/084131. The resonant members may for example be piezoelectric, capacitive, Lorentz force or magnetic. In one preferred form, resonant members are vibrated under the Lorentz force, i.e. by the application of ac current to an input conductor of the resonant member whilst in a magnetic field. The magnetic field may be supplied by an internal or external source.

The outputs from the frequency selective address elements may also be generated in any suitable manner, and for example an output current of an address element may be generated by an output conductor on a resonant member vibrating in a magnetic field, e.g. the same magnetic field as used to vibrate the resonant member under the Lorentz force. The address element may be in effect an electrical generator, and the combination of the input and output signals over a resonant member may be considered to be a frequency- selective transformer. Preferably, an address element includes a resonant member having an input conductor and an output conductor thereon, such that the application of ac current of a predetermined frequency on said input conductor causes said resonant member to vibrate and to generate ac current in the output conductor. Both the vibration and the current generation could be the result of the same excitation process, e.g. both could be caused by a Lorentz force interaction.

The methods used to vibrate the resonant member and generate the output current need not be the same, and, for example, a resonant member could be vibrated under a Lorentz force and generate a current using a piezoelectric element or vice versa.

The address elements need not include a mechanical resonant member, and could be solid-state, e.g. in the form of a tuned circuit of electronic components, e.g. an LC circuit.

The address element may itself generate an output signal from an input signal, and the output signal may then be applied to an address line of a memory element. Alternatively, the address element may include a switch and may provide an output signal by switching to a separate signal source into or out of circuit with an address line. For example, an address element may open or close a switch on an address line to connect the address line to an electrical output, e.g. a voltage source.

In one form, the address element may include a heater circuit, e.g. including a resistive heating element, e.g. a coil, for heating a bimetal switch when a signal of selected frequency is applied to it. Alternatively, the address element may actuate an electromagnet element to close a switch, e.g. using an inductive coil, e.g. in the manner of a relay device.

In one embodiment, the address element provides a dc output, and each column address line includes a capacitor that is chargeable by a column address member. To address a selected memory element, the capacitor address elements are activated to charge each capacitor apart from the one on the address line of the selected memory element. An address element then outputs a current on the row address line associated with the selected memory element. This current passes through the specified memory element to charge the uncharged capacitor on the associated column line. This current can change the state of the memory element, e.g. by fusing a tether of a resonant member so that it is freed to vibrate. None of the other memory elements are affected, as no charge will flow through them due to the charged capacitors on their address lines.

To ensure that these blocking capacitors remain charged, the column address elements of the charged capacitors may continue to be activated during the time that current is applied to the row address elements. Alternatively, the RC time constant of the capacitors and associated discharge resistors may be sufficiently high that the capacitors retain sufficient charge to sufficiently block current during the activation period of the row address elements, without requiring the continued activation of their associated column address elements.

In order to address a further memory element, the column capacitors must be allowed to discharge, e.g. through an associated resistor.

The dc current may be a rectified form of an ac signal generated by the address elements, e.g. a half or full wave rectification that may for example be provided by a diode circuit, or may be provided by switching a separate source onto the address line. The separate source may again be a rectified form of an ac signal or the discharge of a capacitor.

In another embodiment, the address elements may provide ac outputs. These ac outputs may be of different frequencies, and in order to address a memory element a pair of the address elements may be activated to provide ac outputs on associated row and column address lines, such that the combination of outputs causes the memory element to change state. For example, a diode pair may be associated with each memory element, such that whilst only a single voltage signal is applied to the pair, only a small current is developed across them, whereas when the voltages of two combined ac outputs are provided across them, a large voltage is produced and a large current is developed across them e.g. so as to fuse an associated tether. In this regard, the two outputs are of different but similar frequencies, and they will tend to cancel one another out most of the time. However, for a short time the outputs are in an appropriate phase relation, e.g. about 180° out of phase, and so produce a high combined voltage signal. The non-linearity of the diode pair may provide a positive activation threshold, as a small change in voltage can provide a large change in current over certain voltage ranges. The outputs of the address elements may be clamped, e.g. by a diode circuit, to ensure that their outputs are not sufficient, individually, to change the state of a memory device, e.g. to fuse a tether.

Viewed from another aspect, the present invention provides a method of programming a memory device having an array of memory elements, including the steps of: providing a plurality of address elements for addressing said memory elements, wherein said address elements are frequency-sensitive; and applying a programming signal to said address elements, the programming signal having one or more predetermined frequency components that selectively activate one or more of said address elements for addressing one or more of said memory elements.

The present invention also extends to programming devices for programming a memory device, e.g. as discussed above, the programming device outputting a programming signal including frequency components corresponding to activation frequencies of selected ones of said address elements. The programming device may for example include an antenna and

RF generator for generating suitable frequency signals, and/or may include a current generator for generating a current to be applied to external contacts of a memory device. It may also include a power supply signal for supplying power to the memory device that may then be switched through to the memory elements by the address elements.

The present invention also extends to a system of data recordal including both a programmable memory device as discussed and a programming device. The present invention may therefore provide a data recordal system including: a programmable memory device including an array of memory elements, and a plurality of address elements for addressing said memory elements, wherein said address elements are activated by a programming signal and are frequency-sensitive, such that said memory elements can be selectively addressed to change their states by the application of a programming signal having one or more predetermined frequency components that selectively activate one or more of said address elements; and a programming device for applying a programming signal to said memory device, said programming signal having required frequency components therein for addressing required ones of said memory elements.

The present invention is particular useful in relation to the activation of resonant members, and, viewed from another aspect, the present invention provides a programmable memory device including an array of tethered resonant members, and a plurality of activation elements for activating said resonant members by fusing tethers of said resonant members, wherein said activation elements are activated by a programming signal and are frequency- sensitive, such that selected ones of said resonant members can be activated by the application of a programming signal having one or more predetermined frequency components that selectively activate one or more of said activation elements.

The present invention also extends to a programmable memory device including an array of memory elements that each include a resonant member requiring activation, and a plurality of activation elements for addressing said memory elements to activate said resonant members, wherein each said activation element includes a resonant member that is free to vibrate and that is of a different resonant frequency to the resonant members of the other activation elements, and wherein a resonant member of a memory element can be activated by application of a programming signal to said memory device, said programming signal having one or more predetermined frequency components that selectively resonate one or more of said resonant members of said addressing elements. The use of resonant members in the address elements is itself particularly useful, and, viewed from a further aspect, the present invention provides a programmable memory device including an array of memory elements, and a plurality of address elements for addressing said memory elements, wherein each said address element includes a resonant member of a different resonant frequency to the resonant members of the other activation elements, and wherein a resonant member can be activated by application of a programming signal to said memory device, said programming signal having one or more predetermined frequency components that selectively resonate one or more of said resonant members. Although of particular use in relation to memory devices, the concepts of the present invention are not limited to such applications, and may be used in any suitable system that includes array elements that require selective addressing. Thus, viewed from a further aspect, the present invention provides an addressable array including a plurality of addressable array elements, and a plurality of addressing elements for addressing said array elements, wherein said addressing elements are activated by a programming signal and are frequency-sensitive, such that said array elements can be selectively addressed by the application of a programming signal having one or more predetermined frequency components that selectively activate one or more of said addressing elements. The addressing elements preferably include resonant members that resonate in accordance with an applied programming signal.

The addressable array elements could be for example an array of switches that could be activated or deactivated, and could relate to an array of switches that could be released by removing tethers on the switches. The invention may allow for the addressing of a large array without needing a large number of address lines.

The present inventive concepts are particularly applicable to devices formed using MEMS technology, but may be applied to devices formed in other manners and of other sizes.

It should be noted that any one of the aspects mentioned above may include any of the features of any of the other aspects mentioned above and may include any of the features of any of the embodiments described below, as appropriate.

Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings. It is to be understood that the particularity of the drawings does not supersede the generality of the preceding description of the invention. In the drawings:

Figure 1 is a schematic diagram of a first type of memory device that has an address element for each memory element; Figure 2 is a schematic diagram of a second type of memory device, similar to the first type, but with the address elements associated with a common antenna;

Figure 3 is a schematic diagram of a 2D addressable array of memory elements and address elements;

Figure 4 is a schematic diagram of a frequency selective circuit utilising a mechanical resonant member that may be used in an address element;

Figure 5 is a schematic diagram of a solid-state frequency selective circuit that may be used as an address element; Figure 6 is a schematic diagram of a further address element that includes a switch;

Figure 7 is a schematic diagram of a 2D addressable array of memory elements that use address elements having dc output;

Figure 8 is a timing diagram for explaining the addressing of a memory element in Fig. 7;

Figure 9 is a schematic diagram of a 2D addressable array of memory elements that use address elements having ac output; and

Figure 10 is a graph of voltage-current characteristics for a diode pair of the memory elements of Fig. 9 for explaining the addressing of a memory element in Fig. 9.

Referring to Fig.1 , a programmable memory device or data carrier 10 includes a set of memory elements 12 addressed by activation signals 14 from a set of frequency sensitive address elements 16. The address elements 16 are activated by a programming signal 18, e.g. from an encoding/activation device 20. The programming signal 18 is used to address the memory device 10 and to change the state of the memory elements 12, thereby to encode data in the device 10 or to otherwise activate the memory elements 12.

For example, the memory elements 12 may take the form of tethered resonant members, e.g. as disclosed in WO 2004/084131 or WO 2004/083798, and the change of state of the memory elements 12 may be the removal of their tethers, so that the resonant members are free to vibrate and so represent data or, in the case of a thermal sensing device, are activated to start sensing, so that they can later enter a vibratable state once a temperature threshold has been reached. The address elements 16 are each sensitive to a different frequency or frequency range, e.g. F1 to F4, and selected ones of the memory elements 12_Mi to 12_M4 can be addressed by the application of a programming signal 18 that includes frequency components corresponding to the frequencies F1 -F4 of the associated address elements 16_Fi to 16_F4. The address elements 16 may include frequency selective circuits tuned to their own particular frequency or frequency range, and these may include solid-state circuits, e.g. LC circuits or the like, and/or mechanical resonant members, e.g. as discussed in WO 2004/084131. Various possible configurations for the address elements are discussed below in more detail.

The activation signals 14 applied by the address elements 16 to the memory elements 12 may take a number of forms, and may include the application of electric current to the associated memory element 12. An applied current may for example be used to fuse a restraining tether of a resonant member of the memory device 12. An applied current could however also be used in other ways to change the state of a memory element, e.g. it could be used to heat a memory element or to provide a magnetic force using a coil.

The address element programming signal 18 may be applied simultaneously to all of the address elements 16 and may include one or more than one frequency component, so as to activate address elements 16 simultaneously or individually. The programming signal 18 for example may be an RF frequency signal, but could take other forms, e.g. ac current supplied via sets of electrical contacts between the programming device 20 and the memory device 10. It could also for example be an acoustic signal. The programming signal 18 may be applied directly to each of the address elements 16. For example acoustic signals could directly vibrate resonant members in the address elements 16, or a RF signal could directly vibrate a magnetic resonant member or could interact with a separate antenna for each of the address element 16. The programming signal 18 may also be applied to the address elements

16 via a common circuit. An example of this is shown in Fig. 2, in which the address elements 16 of a memory device 10 are all connected on a common input line 22 that receives current from an antenna 24. Thus, by applying an RF programming signal 18 to the antenna 24, ac current is induced in the input line 22, and the frequency components of the ac current can be used to activate the address elements 16.

The same antenna 24 may also be used when interrogating the memory elements 12, e.g. as discussed in WO 2004/084131. For example, a swept frequency RF signal or the like may be applied to the antenna 24 and the response signal may be analysed to check for characteristics caused by a resonant member of a memory element 12 vibrating on a line 26 also connected to the antenna 24.

The address elements 16 may themselves generate the address/activation signal 14, e.g. a fusing current, to apply to the memory elements 12, e.g. using a frequency-selective mechanical transformer as discussed below. Alternatively, the address elements 16 may include a switch that switches in a signal, e.g. current, to the memory elements 12, as again discussed below. This switched-in signal may for example also be generated by the antenna 24 and supplied to the address elements 16 over a common supply line 28. The current may be for example an induced ac current directly from the antenna 24 or may come from a power supply circuit 30 that for example may use current from the antenna 24 to charge a capacitor or the like to provide a dc supply. Separate antennae could alternatively be used for addressing and power purposes. In another embodiment, current could be supplied directly from an external power source over an external electrical connection.

The use of frequency-sensitive address elements 16 has a number of advantages. It allows the encoding of the memory device 10 to be carried out after their fabrication, and so allows the memory devices 10 to be mass produced in a standard process and then tailored to individual needs in a separate process. It also removes or reduces the need for external address connections on the device 10, e.g. an RF signal activated device would need no external contacts, whilst a device activated via an electrical connection would need only a pair of contacts to address a number of memory elements 12 provided on the same input line.

The frequency-sensitive address elements 16 also allow memory elements 12 to be addressed simultaneously or individually. Where the system is used with RFID tags and memory devices as discussed in WO 2004/084131 , the system has the advantage that the same antenna that is used to read the memory devices may be used to program the memory devices, and that the address elements can be fabricated in a similar manner and at the same time as the memory elements.

Fig. 3 shows a further arrangement of memory elements 12 and address elements 16, in which the memory elements 12 are arranged in a 2D array along address lines 32 and 34, and in which each address line has an address element 16 thereon. The address lines 32 and 34 may for example be referred to as row and column lines or bit lines and word lines, although it will be realised that it is the topological connections of the elements that is referred to by this wording, rather than any actual physical arrangement of the memory elements that might be used in practice to give effect to the array.

In this example, the activation of combinations of address elements 16 will address selected ones of the memory devices 12. This may require the use of more complex programming signal combinations, but has the advantage of requiring fewer address elements 16 than the use of a dedicated address element 16 for each memory element 12 as used in the devices of Figs. 1 and 2. Again, the address elements 16 may receive input signals along a common input line 22, e.g. from an antenna or through an external electrical connection. In accordance with the frequencies on the line 22, the address elements 16 may generate or switch in a current to an address line 32 or 34. For example, if an input current on line 22 includes both an F₁ component and an F₄ component, then the address elements 16i and 16₄ would both be activated, and would address memory element M1. They might do this for example by closing switches to place the row address line 32! and the column address line 34_! into circuit with a power supply, or by generating currents that are supplied along the two lines. Various other regimes are also possible, and two specific systems are discussed in more detail below.

Fig. 4 shows a possible address element 16 for use in any of the above devices and arrays. The address element 16 includes a resonant member 40, in the form of a bridge structure, across which are provided an input conductor 42 and an output conductor 44. The input conductor 42 receives an input signal from for example an antenna or external electrical contact as the programming signal, and the resonant member 40 is mounted in a magnetic field perpendicular to the direction of the electrical conductor 42 across the resonant member 40, e.g. across or into the page. The magnetic field can be generated by magnetic elements inside of the memory device 10 or by an external magnetic field applied at the same time as the programming signal 18.

When the input signal corresponds to the resonant frequency of the resonant member 40, the resonant member 40 vibrates due to a Lorentz force acting on the conductor 42. This in turn induces a current on the output conductor 44 through the movement of the conductor 44 in the magnetic field, and this current can be output to the associated memory device 12 e.g. via address line 32 or 34. The resonant member 40 and input and output conductors 42, 44 therefore provide a tuned circuit, which may be considered as a type of transformer or generator arrangement. As well as the shown Lorentz force type arrangement, other arrangements using resonant members would also be possible. For example, the resonant members could interact with a programming signal, e.g. an input ac current or an RF signal, through a magnetic, capacitive or piezoelectric arrangement, e.g. as discussed in WO 2004/084131. Also the input and output currents may be generated using different forces. For example the resonant member 40 could be vibrated under the Lorentz force, but could provide an output current using a piezoelectric component. The resonant member 40 could also take other forms including e.g. a cantilever structure.

Fig. 5 shows schematically an address element 16 formed without a resonant member and which uses solid-state electronic components, e.g. inductors 50, capacitors 52 and resistors 54, to form a tuned circuit 56 that passes only a set frequency or frequency band. The output of the tuned circuit 56 could be used directly to activate a memory element 12 or could be applied via a transformer circuit 58. Fig. 6 shows a further embodiment of an address element 16, in which a tuned circuit 60 is used to activate a switch 62. The tuned circuit 60 could for example take the form of the tuned circuit of Fig. 4 or 5, and the output current could be used to heat a coil 64 to move a bimetallic strip 66. This could then place an address line 32,34 into circuit with a current source on a line 68. The line 68 could for example be direct from an antenna for generating ac current, or could be from a supply circuit that e.g. charges a capacitor from an antenna current or could be direct from an external power source, the current being applied via an external electrical contact. Fig. 7 shows a memory element array in which memory elements are addressed using dc current. In this example, the address elements 16 may for example take the form shown in Fig. 4, and receive an input current 70 on input line 42 that may be derived from an antenna circuit or other source, as discussed above. The output on conductor 44 is applied to the address lines 32, 34 via a diode 72, so as to provide a half-wave rectified dc current (although full wave rectification could also be provided).

The memory elements are represented by fusible tethers 74 which will be fused by current on the lines 32,34, so as to release associated resonant members. The releasing of the resonant members may provide encoding by having for example released resonant members represent a "1 " and unreleased resonant members representing a "0" or vice versa.

A diode 76 is provided with each fusible tether 74 so as to prevent unwanted current flows, and a capacitor 78 is provided at the end of each column line 34 together with a discharge resistor 80. In use, if it is desired to release tether 74₂i, the column address element

16_F7 is activated by applying a current with frequency F7 on the input line 42, so that the capacitor 78_F7 is charged up. Next, a current with both frequency components F7 and F2 is applied to the input line 42 so as to keep capacitor 78_F7 charged, and so as to provide dc current on address line 32_F2- This causes a current to flow through tether 74₂i to charge capacitor 78_F6, whilst no current flows through tether 74₂₂, as capacitor 78_F7 is already fully charged. The current through tether 74₂i fuses the tether, at which point the current is stopped and the capacitor 78_F6 discharges through resistor 80. No programming signal is then applied for a set time, so as to allow the capacitor 78_F7 to also discharge through its own resistor 80.

Thus, as shown in the Fig. 8 timing chart, the address process includes a first charging stage of time t_c for charging capacitor 78_F7, during which time the applied programming signal has only the frequency component F7, a second addressing stage of time t_a for providing current J_A to fuse the addressed tether, during which time the programming signal has frequency components F7 and F2, and a third dwell stage for time td in which no programming signal is provided, to allow the capacitor 78_F7 to discharge.

This system can of course be extended to arrays having any number of rows and columns. Thus, in a first programming step, all column capacitors are charged, except on the column line of the memory element to be addressed. The charged capacitors are then kept charged by their column address elements whilst a row address element associated with the memory element to be addressed is also activated so as to charge the uncharged capacitor through the desired memory element tethers and fuse the tethers with this current. Finally, all of the address elements are left unactivated so as to allow the capacitors to drain.

Fig. 9 shows a memory element array in which memory elements are addressed using ac current. In this example, the address elements 16 may again take the form shown in Fig. 4, and again tethers 74 are shown as being used. In this embodiment, however column capacitors are not used. Instead, diode pairs 90 are used to clamp the output signals to a first voltage V₁ that cannot fuse the tethers 74, and diode pairs 92 are provided in series with the tethers 74 so as to allow fusing currents to pass only is specific circumstances. In this case, in order to fuse tether 74₁₂, a programming signal is applied to input line 42 that has both an F2 frequency component and an F6 frequency component. This will result in ac voltage being developed at the output of address elements 16_F2 and 16_Fe, but at none of the other address element outputs. Accordingly, ac current will flow across tether 74₁₂ that will be based on a superposition of the two voltages from address elements 16_F2 and 16_F6- The two voltage signals will generally cancel one another out to a greater or lesser extent, but as they will be of different but similar frequencies, at some point, e.g. after a set number of voltage cycles, the two voltages will be generally out of phase with one another, and so will provide a voltage of about 2V₁ for a short time period, which will be sufficient to fuse the tether 74₁₂. This can be see in Fig. 10 which provides the V-I characteristics of the diode pairs 92. Thus, a single address element output of V₁ can only provide a low non- fusing current i_nt, whilst the combined output of two address elements can provide a voltage of 2V₁, and so a much larger fusing current of if. The non- linearity of the diode pair 92 enables a small change in voltage to provide a large change in current, and so provides a positive threshold trigger above which fusing can take place.

It will be noted also that the diode pair of tether 74₂2 will only have voltage V₁ developed across it, and so will not pass a sufficiently high current to fuse the tether 74₂2-

Accordingly, any tether 74 may be fused by the activation of an associated pair of row and column address elements, and any address element may be activated by applying a programming signal at its assigned frequency. Turning to the programming device 20, this may be configured in any suitable form so as to provide the frequency signals required for the desired addressing and encoding. For example, the programming device 20 may include an input for receiving data from a user, from a storage device or any other source, and may include software or the like to determine the output signals needed to encode a memory device 10 with the data. The programming device may include a suitable antenna for communicating with an antenna 24 on the memory device or for communicating directly with the address elements, and/or may include electrical connections for connecting with external electrical connections on the memory device. The electrical connections may pass the programming signals and also possibly power signals.

As the programming device may be arranged quite close to the memory device for programming, it may be more powerful and so provide greater coupling and larger currents in the memory device than might for example an interrogation device for applying an interrogation signal. Accordingly, the addressing circuitry, tethers and the like may be designed for one power regime, whilst addressing circuitry and the like associated with reading circuitry may be designed for another power regime, in which input signals may be of less strength.

The devices, arrays, memory elements, address elements and resonant members may be fabricated using MEMS technology (microelectromechanical systems technology), which is also known as MST (Micro System Technology) and micromachining. MEMS technology includes fabrication technologies for integrated circuits, and technologies specifically developed for micromachining. It generally relates to the fabrication of components with dimensions in the range of micrometers to millimeters. MEMS techniques may include for example masking, deposition and etching steps, amongst other well-known lithographic and micromachining processes. It may include for example photolithography and thin film deposition or growth. Typically, the process results in a laminate structure. A number of structural layers can be formed on a substrate, and required components can be formed by selective etching of the substrate and/or sacrificial materials and component materials deposited thereon. The resulting micromachined components may be combined with electronics that are fabricated using standard integrated circuit processes. The addressing concepts are however scalable, and may be applied to any type of resonant member, including larger structures.

Although ac output signals from the address elements are generally discussed above in relation to the same frequency as the input signal, this need not necessarily be the case and the address elements may output signals of different frequencies from the input signals, including dc signals.

The addressing concepts are especially suited to providing RFID tags and the like, although are broadly applicable to any other suitable application.

For example, the use of frequency-sensitive address members and the described addressing systems are applicable to any appropriate type of memory device that has memory elements that need to be selectively addressed. These memory elements may for example not use resonant members, and/or may not use tethers. The address element could for example be used with any type of memory that incorporates a fusing connection or indeed any type of memory that can be addressed and made to change state by the application of a current or other signal from an address element. These concepts would for example be applicable to the programming of electronic programmable read only memory.

The addressing concepts may also be extended to non-memory devices e.g. to any array elements that may be addressed by a set of frequency- sensitive addressing elements, as discussed herein, either with a dedicated address element for each array element or with an address element provided in relation to each address line of the array, e.g. row and column lines. Especially useful are address elements formed using resonant members, which may be used to activate or change the state of any suitable array items. For example, the address elements may be used to control an array of switches, e.g. in a telecom system, e.g. as part of the subscriber access network for connecting subscribers to trunk cables. Generally, the address elements can provide a two terminal method of addressing a large matrix array without the need for active electronics. This concept is applicable in a wide range of circumstances.

The frequencies used to activate the frequency-selective address elements may be basic resonant frequencies or may be higher order resonant frequencies.

It is to be understood that various alterations, additions and/or modifications may be made to the parts previously described without departing from the ambit of the present invention, and that, in the light of the above teachings, the present invention may be implemented in a variety of manners as would be understood by the skilled person.

The present application may be used as a basis for priority in respect of one or more future applications, and the claims of any such future application may be directed to any one feature or combination of features that are described in the present application. Any such future application may include one or more of the following claims, which are given by way of example and are non-limiting with regard to what may be claimed in any future application.

Claims

CLAIMS:

1. A programmable memory device including an array of memory elements, and a plurality of address elements for addressing said memory elements, wherein said address elements are activated by a programming signal and are frequency-sensitive, such that said memory elements can be selectively addressed to change their states by the application of a programming signal having one or more predetermined frequency components that selectively activate one or more of said address elements.

2. The memory device of claim 1 , wherein a memory element is associated with a dedicated address element.

3. The memory device of claim 1 , wherein said memory elements are addressable by row and column address lines, an address element being associated with each said address line.

4. The memory device of claim 1 , 2 or 3, wherein said programming signal is applied as an ac electrical signal, and wherein said device includes an electrical connection for receiving said electrical signal.

5. The memory device of any of claims 1 to 3, wherein said programming signal is an electromagnetic signal applied to an antenna circuit associated with said address elements.

6. The memory device of any preceding claim, wherein address elements are associated with a common input conductor on which a programming signal is placed.

7. The memory device of any preceding claim, wherein a said address element includes a tuned circuit of electronic components.

8. The memory device of any preceding claim, wherein a said address element includes a mechanical resonant member.

9. The memory device of any preceding claim, wherein a said address element includes a resonant bridge member or a resonant cantilever member.

10. The memory device of any preceding claim, wherein a said address element includes a mechanical resonant member that has an input conductor thereon, said resonant member vibrating in response to a current on said input conductor having a frequency corresponding to a resonant frequency of said resonant member.

11. The memory device of any preceding claim, wherein a said address element includes a mechanical resonant member that resonates under the Lorentz force.

12. The memory device of any preceding claim, wherein a said address element includes circuitry for generating an output signal for addressing said memory elements.

13. The memory device of any preceding claim, wherein a said address element includes a mechanical resonant member having an output conductor thereon, such that when said resonant member vibrates an output signal is developed on said output conductor.

14. The memory device of any preceding claim, wherein a said address element includes a switch associated with an address line of a memory element, said address line applying a signal to a memory element based on the state of said switch.

15. The memory device of any preceding claim, wherein said address elements include a switch for switching an address signal into a memory element, said address signal being provided by a circuit deriving power from said programming signal or from a separate power signal.

16. The memory device of any preceding claim, wherein a said address element includes a tuned circuit and a coil for activating a switch on an address line of a memory element.

17. The memory device of any preceding claim, wherein a said address element includes a bimetallic switch on an address line of a memory element.

18. The memory device of any preceding claim, wherein a said address element outputs a dc signal to said memory elements.

19. The memory device of any of claims 1 to 17, wherein a said address element outputs an ac signal to said memory elements.

20 The memory device of any preceding claim, wherein said memory elements are resonant members held by restraining devices which are disabled by said address elements.

21. The memory device of any preceding claim, wherein said memory elements are resonant members held by fusible tethers, and wherein an address element addresses a memory element by applying a current to said memory element sufficient to fuse a tether associated with said memory element to release the resonant member.

22. The memory device of any preceding claim, wherein said memory elements are arranged in a 2D array and are associated with row and column address lines on each of which is provided an address element for outputting dc current, wherein each column address line includes a capacitor chargeable by a corresponding column address element, such that to address a selected memory element all capacitors apart from the capacitor on the column address line of the selected memory element are charged, an address element applies dc current to the row address line of said selected memory element to charge the uncharged capacitor on the selected memory element's column address line, and said capacitors are allowed to discharge.

23. The memory device of any of claims 1 to 21 , wherein said memory elements are arranged in a 2D array and are associated with row and column address lines on each of which is provided an address element for outputting ac current, such that to address a selected memory element the address element on the corresponding row address line applies an ac signal of a first frequency and the address element on the corresponding column address line applies an ac signal of a second frequency, such that waveforms of said two signals combine to provide a current across said memory element above a threshold value sufficient to alter a state of said memory element.

24. The memory device of claim 23, wherein each memory element includes a diode pair across which said threshold value current is developed.

25. The memory device of claim 23 or 24, wherein said address lines are clamped to a maximum voltage less than that able to supply said threshold value of current.

26. A method of programming a memory device having an array of memory elements, including the steps of: providing a plurality of address elements for addressing said memory elements, wherein said address elements are frequency-sensitive; and applying a programming signal to said address elements, said programming signal having one or more predetermined frequency components that selectively activate one or more of said address elements for addressing one or more of said memory elements.

27. A programming device for a memory device of any of claims 1 to 26, said programming device outputting a programming signal including frequency components corresponding to activation frequencies of selected ones of said address elements.

28. A memory recordal system including: a programmable memory device including an array of memory elements, and a plurality of address elements for addressing said memory elements, wherein said address elements are activated by a programming signal and are frequency-sensitive, such that said memory elements can be selectively addressed to change their states by the application of a programming signal having one or more predetermined frequency components that selectively activate one or more of said address elements; and a programming device for applying a programming signal to said memory device, said programming device having required frequency components therein for addressing required ones of said memory elements.

29. A programmable memory device including an array of tethered resonant members, and a plurality of activation elements for activating said resonant members by fusing tethers of said resonant members, wherein said activation elements are activated by a programming signal and are frequency-sensitive, such that selected ones of said resonant members can be activated by the application of a programming signal having one or more predetermined frequency components that selectively activate one or more of said activation elements.

30. A programmable memory device including an array of memory elements that each include a resonant member requiring activation, and a plurality of activation elements for addressing said memory elements to activate said resonant members, wherein each said activation element includes a resonant member therein that is free to vibrate and that is of a different resonant frequency to the resonant members of the other activation elements, and wherein a resonant member of a memory element can be activated by application of a programming signal to said memory device, said programming signal having one or more predetermined frequency components that selectively resonate one or more of said resonant members of said addressing elements.

31. A programmable memory device including an array of memory elements, and a plurality of address elements for addressing said memory elements, wherein each said address element includes a resonant member of a different resonant frequency to the resonant members of the other activation elements, and wherein a resonant member can be activated by application of a programming signal to said memory device, said programming signal having one or more predetermined frequency components that selectively resonate one or more of said resonant members.

32. An addressable array including a plurality of addressable array elements, and a plurality of addressing elements for addressing said array elements, wherein said addressing elements are activated by a programming signal and are frequency-sensitive, such that said array elements can be selectively addressed by the application of a programming signal having one or more predetermined frequency components that selectively activate one or more of said addressing elements.

33. The addressable array of claim 32, wherein said addressing elements include resonant members that resonate in accordance with an applied programming signal.