WO2008061161A3 - Execution of legacy code on hybrid computing platform - Google Patents

Execution of legacy code on hybrid computing platform Download PDF

Info

Publication number
WO2008061161A3
WO2008061161A3 PCT/US2007/084722 US2007084722W WO2008061161A3 WO 2008061161 A3 WO2008061161 A3 WO 2008061161A3 US 2007084722 W US2007084722 W US 2007084722W WO 2008061161 A3 WO2008061161 A3 WO 2008061161A3
Authority
WO
WIPO (PCT)
Prior art keywords
code
processing
fpga
execution
computing platform
Prior art date
Application number
PCT/US2007/084722
Other languages
French (fr)
Other versions
WO2008061161A2 (en
Inventor
Kent L Gilson
James V Yardley
Original Assignee
Star Bridge Systems Inc
Kent L Gilson
James V Yardley
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Star Bridge Systems Inc, Kent L Gilson, James V Yardley filed Critical Star Bridge Systems Inc
Publication of WO2008061161A2 publication Critical patent/WO2008061161A2/en
Publication of WO2008061161A3 publication Critical patent/WO2008061161A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061—Partitioning or combining of resources
    • G06F9/5066—Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061—Partitioning or combining of resources
    • G06F9/5077—Logical partitioning of resources; Management or configuration of virtualized resources

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Logic Circuits (AREA)
  • Stored Programmes (AREA)

Abstract

A system includes an operating system tied to an FPGA with at least one embedded microprocessor to execute computer readable code. A process in the system includes running a profile of a targeted software program to determine processing- intensive portions of code. The processing-intensive portions of code are identified in the software program. One of the processing-intensive portions of the code is selected. FPGA code for the selected processing-intensive portion is created. A portion of the embedded microprocessor is partitioned to allocate to the FPGA code. The FPGA code is programmed in the embedded microprocessor.
PCT/US2007/084722 2006-11-14 2007-11-14 Execution of legacy code on hybrid computing platform WO2008061161A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US86580706P 2006-11-14 2006-11-14
US60/865,807 2006-11-14

Publications (2)

Publication Number Publication Date
WO2008061161A2 WO2008061161A2 (en) 2008-05-22
WO2008061161A3 true WO2008061161A3 (en) 2008-07-10

Family

ID=39402465

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/084722 WO2008061161A2 (en) 2006-11-14 2007-11-14 Execution of legacy code on hybrid computing platform

Country Status (1)

Country Link
WO (1) WO2008061161A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10229470B2 (en) * 2016-08-05 2019-03-12 Intel IP Corporation Mechanism to accelerate graphics workloads in a multi-core computing architecture

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994014123A1 (en) * 1992-12-11 1994-06-23 National Technology, Inc. Integrated circuit computing device comprising dynamically configurable gate array having a reconfigurable execution means
US6385668B1 (en) * 1999-04-08 2002-05-07 Lucent Technologies Inc. Method and apparatus for compound hardware configuration control
US6571381B1 (en) * 1998-02-25 2003-05-27 Pact Xpp Technologies Ag Method for deadlock-free configuration of dataflow processors and modules with a two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)
US6871341B1 (en) * 2000-03-24 2005-03-22 Intel Corporation Adaptive scheduling of function cells in dynamic reconfigurable logic

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994014123A1 (en) * 1992-12-11 1994-06-23 National Technology, Inc. Integrated circuit computing device comprising dynamically configurable gate array having a reconfigurable execution means
US6571381B1 (en) * 1998-02-25 2003-05-27 Pact Xpp Technologies Ag Method for deadlock-free configuration of dataflow processors and modules with a two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)
US6385668B1 (en) * 1999-04-08 2002-05-07 Lucent Technologies Inc. Method and apparatus for compound hardware configuration control
US6871341B1 (en) * 2000-03-24 2005-03-22 Intel Corporation Adaptive scheduling of function cells in dynamic reconfigurable logic

Also Published As

Publication number Publication date
WO2008061161A2 (en) 2008-05-22

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