WO2008059560A1

WO2008059560A1 - Direct conversion receiver

Info

Publication number: WO2008059560A1
Application number: PCT/JP2006/322613
Authority: WO
Inventors: Hiroshi Miyagi
Original assignee: Neuro Solution Corp.
Priority date: 2006-11-14
Filing date: 2006-11-14
Publication date: 2008-05-22

Abstract

A direct conversion receiver wherein even when signals are successively received, the DC offset voltage can be removed. The direct conversion receiver comprises a local oscillator (16) that generates a local oscillation signal having the same frequency as a desired signal to be received; a mixer (14) that mixes a broadcast wave signal received via an antenna (12) with the local oscillation signal to generate a baseband signal; PLL circuits (20,30) that receive the baseband signal outputted by the mixer (14); and analog-to-digital converters (28,38) and a signal processing part (40) that sever as a demodulating circuit for demodulating signals outputted by the PLL circuits (20,30). The PLL circuits (20,30) generate the signals that are synchronized with the baseband signal and that have no correlation to the DC offset voltage included in the baseband signal.

Description

Specification

Direct conversion receiver

Technical field

The present invention relates to a direct conversion receiver that converts a received signal into a baseband signal and performs demodulation processing and the like. Background art

A direct conversion receiver generates a baseband signal by mixing a local oscillation signal having the same frequency as the high frequency signal with a mixer with respect to the received high frequency signal. In this mixer, the local oscillation signal wraps around the input terminal side of the high-frequency signal, so that the output signal includes a DC offset voltage, and the reception sensitivity deteriorates. For this reason, a receiver that removes a DC offset voltage using a guard interval is conventionally known (see, for example, Patent Document 1).

Patent Document 1: Japanese Patent Laid-Open No. 2001-245006 (Page 5-11, Fig. 1-10)

Disclosure of the invention

Problems to be solved by the invention

[0003] By the way, since the removal of the DC offset voltage disclosed in Patent Document 1 described above is performed using a guard interval, when receiving signals continuously like an FM receiver, There was a problem that it could not be applied and the DC offset voltage could not be removed.

[0004] The present invention was created in view of the above points, and an object of the present invention is to provide a direct converter capable of removing a DC offset voltage even when signals are continuously received. To provide a version receiver.

Means for solving the problem

In order to solve the above-described problem, a direct conversion receiver according to the present invention includes a local oscillator that generates a local oscillation signal having the same frequency as a signal desired to be received, and a broadcast received through an antenna. A mixer that generates a baseband signal by mixing the wave signal and the local oscillation signal, and a PLL circuit that receives the baseband signal output from the mixer force And a demodulation processing circuit for performing demodulation processing on the signal output from the PLL circuit. Specifically, the PLL circuit described above includes a phase comparator in which a baseband signal is input to one input terminal, a low-pass filter that smoothes the output of the phase comparator, and a frequency according to the output voltage of the low-pass filter. A voltage-controlled oscillator that oscillates at a frequency divider, and a frequency divider that divides the output of the voltage-controlled oscillator and inputs it to the other input terminal of the phase comparator. The output of the voltage-controlled oscillator is demodulated. It is input to the circuit. The PLL circuit can generate a signal that is synchronized with the baseband signal and uncorrelated with the DC offset voltage included in the baseband signal, and removes the DC offset voltage even when the signal is continuously received. be able to.

[0006] Further, the above-described demodulation processing circuit includes an analog / digital converter for converting a signal output from the PLL circuit into digital data, and a signal for performing demodulation processing on the digital data output from the analog / digital conversion. It is desirable to have a processing unit. This makes it possible to perform complex demodulation processing by digital processing.

[0007] The PLL circuit described above includes first and second PLL circuits that generate an I signal as an in-phase component and a Q signal as a quadrature component, and the demodulation processing circuit includes the I signal and the Q signal. It is desirable to perform demodulation processing based on this. This makes it possible to demodulate using I and Q signals.

[0008] Each of the first and second PLL circuits described above includes a phase comparator in which a baseband signal is input to one input terminal, a low-pass filter for smoothing the output of the phase comparator, and a low-pass filter. A voltage-controlled oscillator that oscillates at a frequency corresponding to the output voltage of the output and a frequency divider with a frequency division ratio of 2 in the final stage to divide the output of the voltage-controlled oscillator and input the other of the phase comparator The final frequency divider included in the first PLL circuit performs frequency division operation in synchronization with the rise of the previous frequency divider. The final-stage frequency divider included in the second PLL circuit performs frequency division in synchronization with the falling edge of the previous frequency divider, and outputs the voltage-controlled oscillator included in the first PLL circuit. Is input to the demodulation processing circuit as an I signal and the output of the voltage controlled oscillator included in the second PLL circuit It is desirable to be input to the demodulation processing circuit as Q signal. This enables demodulation processing using the I and Q signals generated by the two PLL circuits. [0009] In addition, it is desirable that the PLL circuit described above generates an I signal as an in-phase component and a Q signal as a quadrature component with a common circuit configuration. It is possible to generate the I and Q signals necessary for demodulation processing with a simple circuit configuration.

[0010] In addition, the PLL circuit described above includes a phase comparator in which a baseband signal is input to one input terminal, a low-pass filter that smoothes the output of the phase comparator, and a frequency according to the output voltage of the low-pass filter. Including the voltage-controlled oscillator that oscillates at the first stage and the first divider with a division ratio of 2 at the final stage, the output of the voltage-controlled oscillator is divided and input to the other input terminal of the phase comparator Multiple dividers and the first divider perform the dividing operation in synchronization with the rising Z falling of the previous divider, while the falling of the same previous divider Z has a second divider with a division ratio of 2 that is different from the multiple dividers that divide in synchronization with the rising edge, and the output of the first divider is demodulated as an I signal. It is desirable that the second divider output is input to the demodulation processing circuit as a Q signal. This makes it possible to generate I and Q signals using a single PLL circuit.

[0011] Further, the above-mentioned local oscillator includes a crystal resonator, and a local oscillator excluding the crystal resonator, a mixer, a PLL circuit, and a demodulation circuit are combined into one using a MOS process or a CMOS process. It is desirable to form on a semiconductor substrate. This makes it possible to reduce the circuit configuration and facilitate manufacture.

Brief Description of Drawings

FIG. 1 is a diagram showing a basic configuration of a direct conversion receiver according to a first embodiment.

FIG. 2 is a diagram showing a basic configuration of a direct conversion receiver according to a second embodiment. Explanation of symbols

[0013] 10 Low noise amplifier (LNA)

12 Antenna

14 Mixer

16 Local oscillator (LO)

18 Amplifier

20, 20A, 30 PLL circuit

21, 31 Phase comparator 22, 32 Low-pass filter (LPF)

23, 33 Voltage controlled oscillator (VCO)

24, 25, 26, 27, 34, 35, 36 divider

28, 38 Analog-to-digital converter (ADC)

40 Signal processor

42 Digital—Analog Transformation (DAC)

44 Speaker

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, a direct conversion receiver according to an embodiment to which the present invention is applied will be described in detail.

[First Embodiment]

FIG. 1 is a diagram illustrating a basic configuration of a direct conversion receiver according to the first embodiment. As shown in Fig. 1, the direct conversion receiver of this embodiment includes a low-noise amplifier (LNA) 10, an antenna 12, a mixer 14, a local oscillator (LO) 16, an amplifier 18, a PLL circuit 20, 30, and an analog digital Converters (ADC) 28 and 38, a signal processing unit 40, a digital analog conversion (DAC) 42, and a speaker 44 are provided. This direct conversion receiver receives continuously distributed FM broadcast waves, but the present invention can also be applied to a direct conversion receiver that performs intermittent reception. In this direct conversion receiver, most of the components except the antenna 12, the speaker 44, and a few other components are formed on a single semiconductor substrate using a MOS process or a CMOS process. For example, when the local oscillator 16 is configured with a PLL circuit and a crystal oscillator including a crystal oscillator is used to generate the reference frequency signal, the local oscillator 16 excluding the mixer 14 and the crystal oscillator is used. Amplifier 18, PLL circuit 20, 30, Analogue digital converter (ADC) 28, 38, Signal processing unit 40, Digital analog converter (DAC) 42 Overall power of one semiconductor using MOS process or CMOS process It is formed on a substrate. As a result, the circuit configuration can be reduced in size and manufacturing is facilitated.

The low noise amplifier 10 amplifies the reception signal input from the antenna 12. This low noise Between the amplifier 10 and the antenna 12, impedance matching between them is performed, and an input circuit (not shown) configured to include a tuning circuit or a band-pass filter for selecting a broadcast wave desired to be received. ) Is inserted. The mixer 14 mixes the reception signal amplified by the low noise amplifier 10 and the local oscillation signal from which the local oscillator 16 is also output, and outputs a baseband signal. The local oscillator 16 outputs a local oscillation signal having the same frequency as the broadcast wave desired to be received. The amplifier 18 amplifies the baseband signal output from the mixer 14 and inputs the amplified signal to two subsequent PLL (phase-locked loop) circuits 20 and 30.

[0017] The two PLL circuits 20 and 30 perform orthogonal demodulation on the baseband signal output from the amplifier 18 to generate an in-phase component (I signal) and a quadrature component (Q signal) of the baseband signal. To do. One PLL circuit 20 outputs an I signal, and the other PLL circuit 30 outputs a Q signal. The analog-digital conversion 28 samples the I signal output from the one PLL circuit 20 at a predetermined frequency and converts it into digital data. The analog digital conversion 38 samples the Q signal output from the other PLL circuit 30 at a predetermined frequency and converts it into digital data. The signal processing unit 40 generates audio data by performing signal processing such as FM detection and FM stereo demodulation using the I signal and the Q signal converted into digital data. The signal processing unit 40 is configured by using, for example, a DSP (digital signal processing device). In the digital-analog conversion, the audio data output from the signal processing unit 40 is converted into an analog audio signal and output from the speaker 44. In the configuration shown in FIG. 1, one digital-analog converter 42 and one speaker 44 are shown, but two sets of these are provided for stereo reproduction.

Next, the detailed configuration of the two PLL circuits 20 and 30 and the operation for generating the I signal and the Q signal will be described. As shown in Figure 1, one PLL circuit (first PLL circuit) 20 includes a phase comparator 21, a low-pass filter (LPF) 22, a voltage-controlled oscillator (VCO) 23, and frequency dividers 24, 25, and 26. It has.

[0019] The phase comparator 21 has two input terminals, and is fed back through the baseband signal input from the amplifier 18 to one input terminal and the three frequency dividers 24, 25, and 26. Compare the phase of the signal. A signal with a duty ratio corresponding to the phase comparison result is output from the phase comparator 21. Is output. For example, if the frequency and phase of two signals input to two input terminals are the same, a signal with a duty ratio of 50% is output, and if they do not match, the duty ratio is less than 50% or The above signals are output. Alternatively, if the frequency and phase of the two signals input to the two input terminals are equal, a 0 V signal is output, and if they do not match, a positive or negative potential pulse is output according to the magnitude relationship. Is done.

The low-pass filter 22 smoothes the output signal of the phase comparator 21 and generates a control voltage to be applied to the voltage controlled oscillator 23. The voltage controlled oscillator 23 oscillates at a frequency corresponding to the applied control voltage. The output signal of the voltage controlled oscillator 23 is input to the analog digital converter and also input to the frequency divider 24. The frequency divider 24 divides the output signal of the voltage controlled oscillator 23 by the frequency division ratio Ν. In the subsequent stage of the frequency divider 24, frequency dividers 25 and 26 having a frequency division ratio of 2 are connected in cascade, and the output signal of the third frequency divider 26 is input to the phase comparator 21.

In the PLL circuit 20 described above, when a baseband signal having a frequency f is input from the amplifier 18, the voltage controlled oscillator 23 has a frequency of 4 Nf and is synchronized with the input baseband signal. Output signal (I signal).

[0022] The other PLL circuit 30 (second PLL circuit) includes a phase comparator 31, a low-pass filter (LPF) 32, a voltage-controlled oscillator (VCO) 33, and frequency dividers 34, 35, and 36. ing. The phase comparator 31 has two input terminals, and a baseband signal input from the amplifier 18 to one input terminal and a signal fed back through three frequency dividers 34, 35, and 36. Perform phase comparison. The phase comparator 31 outputs a signal with a duty ratio corresponding to the phase comparison result.

The low-pass filter 32 smoothes the output signal of the phase comparator 31 and generates a control voltage to be applied to the voltage controlled oscillator 33. The voltage controlled oscillator 33 oscillates at a frequency corresponding to the applied control voltage. The output signal of the voltage controlled oscillator 33 is input to the analog digital converter 38 and also to the frequency divider 34. The frequency divider 34 divides the output signal of the voltage controlled oscillator 33 by the frequency division ratio Ν. In the subsequent stage of the frequency divider 34, frequency dividers 35 and 36 having a frequency division ratio of 2 are connected in cascade, and the output signal of the third frequency divider 36 is connected. The signal is input to the phase comparator 31.

By the way, the third frequency divider 26 included in the PLL circuit 20 performs the frequency dividing operation in synchronization with the rising edge of the output signal of the second frequency divider 25. The third frequency divider 36 included performs a frequency dividing operation in synchronization with the fall of the output signal of the second frequency divider 35. Therefore, in the PLL circuit 30 described above, when the baseband signal having the frequency f is input from the amplifier 18, the voltage controlled oscillator 33 has a frequency of 4Nf and the phase of the input baseband signal and the phase. Outputs a signal (Q signal) with a 90 ° offset.

As described above, in the direct conversion receiver of this embodiment, the PLL circuits 20 and 30 generate a signal that is synchronized with the baseband signal and has no correlation with the DC offset voltage included in the baseband signal. The DC offset voltage can be removed even when broadcast wave signals are continuously received.

[0026] Further, by performing demodulation processing using the signal processing unit 40 after conversion into digital data, it is possible to perform complicated demodulation processing by digital processing. Also, demodulation processing using the I signal and Q signal generated by the two PLL circuits 20 and 30 becomes possible.

[Second Embodiment]

FIG. 2 is a diagram illustrating a basic configuration of a direct conversion receiver according to the second embodiment. As shown in FIG. 2, the direct conversion receiver of this embodiment includes a low noise amplifier (LNA) 10, an antenna 12, a mixer 14, a local oscillator (LO) 16, an amplifier 18, a PLL circuit 20A, and analog-digital conversion. Devices (ADC) 28 and 38, a signal processing unit 40, a digital-analog converter (DAC) 42, and a speaker 44. Similar to the direct conversion receiver of the first embodiment shown in FIG. 1, the direct conversion receiver of the present embodiment receives FM broadcast waves that are continuously distributed. The present invention can also be applied to a direct conversion receiver that performs the above. This direct conversion receiver has almost all components except the antenna 12, speaker 44, and a few other components integrated on a single semiconductor substrate using the MOS process or CMOS process! .

The direct conversion receiver shown in FIG. 2 is different from the configuration shown in FIG. 1 in that two PLL circuits 20 and 30 are replaced with one PLL circuit 20A. PLL circuit 20A Is equipped with a phase comparator 21, a low-pass filter (LPF) 22, a voltage controlled oscillator (VCO) 23, and frequency dividers 24, 25, 26, 27! A frequency divider 27 is added to the PLL circuit 20 shown in FIG. 1 until the PLL circuit 20 is completed, and other configurations are basically the same. The frequency divider 27 is connected to the subsequent stage of the frequency divider 25 and performs a frequency dividing operation in synchronization with the fall of the output signal of the frequency divider 25. As a result, when an I signal synchronized with the baseband signal is output from the frequency divider (first frequency divider) 26, the frequency divider (second frequency divider) 27 is orthogonal to the baseband signal. Yes Q signal can be extracted. These I and Q signals are separately converted into digital data by the analog / digital converters 28 and 38 and then input to the signal processing unit 40. As described above, in the direct comparison receiver of the present embodiment, the I signal and the Q signal can be generated using one PLL circuit 20, and the circuit configuration can be simplified.

[0029] It should be noted that the present invention is not limited to the above embodiment, and various modifications can be made within the scope of the gist of the present invention. For example, in each of the above-described embodiments, the analog digital processing 28 and 38 and the signal processing unit 40 may be used to perform a demodulation operation by a force analog processing that performs a demodulation operation by digital processing. .

In each of the above-described embodiments, the I signal and the Q signal are generated using two PLL circuits 20 and 30 or one PLL circuit 20 、. The signal generated by V may be digitally processed in the signal processing unit 40 in the subsequent stage to generate the I signal and the Q signal. For example, in the configuration shown in FIG. 2, the frequency divider 27 and the analog-digital conversion 38 may be omitted, and the demodulation processing may be performed after generating the I signal and the Q signal in the signal processing unit 40. Or, in this case, the output of divider 26 is input to analog-digital converter 28, but the voltage-controlled oscillator 23, dividers 24, 25 V, and either output is converted to analog-digital converter 28. You can enter it!

Industrial applicability

[0031] According to the present invention, the PLL circuit can generate a signal that is synchronized with the baseband signal and has no correlation with the DC offset voltage included in the baseband signal, and the signal is continuously received. Even so, the DC offset voltage can be removed.

Claims

The scope of the claims

[1] A local oscillator that generates a local oscillation signal having the same frequency as a signal desired to be received, and a mixer that generates a baseband signal by mixing a broadcast wave signal received via an antenna and the local oscillation signal When,

A direct conversion receiver comprising: a PLL circuit to which the mixer force output baseband signal is input; and a demodulation processing circuit that performs demodulation processing on the signal output from the PLL circuit.

[2] In claim 1,

The PLL circuit oscillates at a frequency corresponding to an output voltage of the low-pass filter, a low-pass filter that smoothes the output of the phase comparator, a phase comparator in which the baseband signal is input to one input terminal. A voltage controlled oscillator that divides the output of the voltage controlled oscillator and inputs it to the other input terminal of the phase comparator, and the output of the voltage controlled oscillator is the output of the voltage controlled oscillator. Direct conversion receiver that is input to the demodulation processing circuit.

[3] In claim 2,

The demodulation processing circuit includes an analog-to-digital converter that converts a signal output from the PLL circuit into digital data, and a signal processing unit that performs demodulation processing on the digital data output from the analog-to-digital conversion. Having direct conversion receiver.

[4] In claim 1,

The PLL circuit includes first and second PLL circuits that generate an I signal as an in-phase component and a Q signal as a quadrature component,

The demodulation processing circuit is a direct conversion receiver that performs demodulation processing based on the I signal and the Q signal.

[5] In claim 4,

Each of the first and second PLL circuits includes a phase comparator in which the baseband signal is input to one input terminal, and a low-pass filter that smoothes the output of the phase comparator. Including a filter, a voltage-controlled oscillator that oscillates at a frequency corresponding to the output voltage of the low-pass filter, and a frequency divider having a division ratio of 2 in the final stage to divide the output of the voltage-controlled oscillator. A plurality of frequency dividers that are input to the other input terminal of the phase comparator, and the final-stage frequency divider included in the first PLL circuit is a stand-up of the previous frequency divider. The frequency divider operates in synchronization with the upper force S, and the final-stage frequency divider included in the second PLL circuit performs frequency synchronization in synchronization with the fall of the previous frequency divider. ,

The output of the voltage controlled oscillator included in the first PLL circuit is input to the demodulation processing circuit as the I signal, and the output of the voltage controlled oscillator included in the second PLL circuit is the Q signal. A direct comparison receiver that is input as a signal to the demodulation processing circuit.

[6] In claim 1,

The PLL circuit is a direct conversion receiver that generates an I signal as an in-phase component and a Q signal as a quadrature component with a common circuit configuration.

[7] In claim 6,

The PLL circuit oscillates at a frequency corresponding to an output voltage of the low-pass filter, a low-pass filter that smoothes the output of the phase comparator, a phase comparator in which the baseband signal is input to one input terminal. A plurality of voltage controlled oscillators, and a first frequency divider having a frequency division ratio of 2 in the final stage, and dividing the output of the voltage controlled oscillator and inputting it to the other input terminal of the phase comparator The same frequency divider and the first frequency divider perform the frequency dividing operation in synchronization with the rising Z falling edge of the previous frequency divider, while the falling frequency of the previous frequency divider is the same. A second frequency divider having a frequency division ratio of 2 different from the plurality of frequency dividers that perform the frequency dividing operation in synchronization with Z rising;

The direct conversion receiver in which the output of the first divider is input to the demodulation processing circuit as the I signal and the output of the second divider is input to the demodulation processing circuit as the Q signal .

[8] In claim 1,

The local oscillator is configured to include a crystal resonator,

The local oscillator excluding the crystal resonator, the mixer, the PLL circuit, the demodulation circuit There is a MOS process! / ヽ is a direct conversion receiver that uses a CMOS process on a single semiconductor substrate.