WO2008059391A1 - Générateur de signaux, et procédé de génération de signaux pour des récepteurs radiofréquence - Google Patents

Générateur de signaux, et procédé de génération de signaux pour des récepteurs radiofréquence Download PDF

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Publication number
WO2008059391A1
WO2008059391A1 PCT/IB2007/054386 IB2007054386W WO2008059391A1 WO 2008059391 A1 WO2008059391 A1 WO 2008059391A1 IB 2007054386 W IB2007054386 W IB 2007054386W WO 2008059391 A1 WO2008059391 A1 WO 2008059391A1
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WIPO (PCT)
Prior art keywords
receiver
signal
clock signal
digital
periodic
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PCT/IB2007/054386
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English (en)
Inventor
Paulus T. M. Van Zeijl
Anthony Sayers
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Nxp B.V.
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Publication date
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Publication of WO2008059391A1 publication Critical patent/WO2008059391A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B17/00—Monitoring; Testing
    • H04B17/20—Monitoring; Testing of receivers
    • H04B17/21—Monitoring; Testing of receivers for calibration; for correcting measurements

Definitions

  • the present invention relates to a signal generator for calibration and a method for calibration of image rejection and second order intercept.
  • mixers translate a high input radio frequency (RF) to a lower intermediate frequency (IF). This is generally known as down conversion.
  • RF radio frequency
  • IF intermediate frequency
  • the mixer output signal, amplitude and phase are proportional to the input signal's amplitude and phase, and independent of the local oscillator (LO) signal characteristics.
  • LO local oscillator
  • non-linearities and unmatched path properties e.g. of the I-path and the Q-path produce undesired mixing products, such as spurious responses, which are caused by undesired signals reaching the mixer's RF input port and producing a response at the IF frequency.
  • IP2 second order intercept
  • IP2 For specifying the mixer's IP2, it is assumed that only the fundamental RF and LO frequencies are applied to the mixer's port and that the harmonic distortion is created in the mixer alone.
  • High level input signals create distortion or inter modulation products and can be quantified by calculating the intercept point either at the input or output of the device or system.
  • the input intercept point represents a hypothetical input amplitude at which the desired signal components and undesired components are equal in amplitude.
  • IP3 for the third order intercept
  • the order refers to how fast the amplitudes of the distortion products increase with a rise in input level.
  • the second order inter modulation products will increase in amplitude by 2 dB, when the input signal is raised by IdB. Accordingly, radio frequency applications require receivers, which provide a high image rejection and a high second-order intercept (IP2).
  • a transmitter may be used for generating a calibration signal for the receiver. If the transceiver uses the same frequency for receiving and transmitting, a single-sideband signal at the transmitter may have the frequency fLo + fiF, wherein fi ⁇ > is the frequency of the local oscillator (LO), and f ⁇ ? is the intermediate frequency.
  • LO local oscillator
  • a certain amount of feed-through from the LO will occur at the frequency fLo-
  • any unbalance in the LO or IF path will result in an image signal at fi ⁇ > + fiF- If the desired component is at fLo+fiF than the image is at fLo-fiF-
  • This image signal limits the achievable calibration accuracy of the receiver to the amount generated by the transmitter. Accordingly, an important characteristic of a receiver is the image rejection.
  • the ideal approach of calibrating the receiver consists in measuring the receiver with a good signal generator. Based on measurements on the basis of test signals, which are provided by the signal generator and which are injected in the receiver, the I and Q unbalance with regard to their amplitudes and phases, the IP2 effects, and the image rejection can be determined. In response to the measurement results, small changes in the I or Q path are applied to counteract the measured non-idealities.
  • a separate high performance signal generator providing high quality reference signals entails high costs for the equipment.
  • a method for calibrating a radio frequency receiver includes the following steps: providing a first digital clock signal, adapting the first digital clock signal such that a harmonic of the first digital clock signal is suitable to be used as a calibration signal for the receiver. Further, the method can include the step of supplying the digital clock signal to an input of the radio receiver in order to calibrate the receiver by use of the harmonic.
  • This aspect of the present invention is particularly advantageous, as digital clock signals are omni-present and easy to generate. Digital clock signals are composed of high order harmonics of the basic oscillating frequency of the digital signal. If the signal is assumed to have a predetermined waveform, the harmonics are predictable.
  • the high order harmonics have smaller amplitudes compared to the amplitudes of the digital clock signal.
  • the digital signal is adapted such that the first digital clock signal can be applied to specific inputs of the radio frequency receiver without overdriving the input.
  • the input may be an input of the low noise amplifier or any other entry point in the receiver processing chain dependent on the components, which are to be calibrated.
  • the digital clock signal might be filtered in order to suppress undesired frequency components.
  • the method comprises the step of attenuating the first periodic digital clock signal in order to avoid overloading the input of the receiver, i.e. input components of the receiver.
  • the whole digital input signal is attenuated in order to prevent that for example the LNA or other components are overdriven by the input signals.
  • the digital signal, so attenuated can be used without previous filtering and the entire digital calibration signal can be applied to the respective injection point of the receiver.
  • the method includes the step of combining the first periodic digital clock signal with a delayed version of the first periodic digital clock signal, thereby generating a periodic pulse signal to be used as calibration signal.
  • a signal having a short pulses might be more suitable for extracting harmonics, as for example a rectangular digital clock signal. Accordingly, a harmonic of an increased quality can be extracted from the short pulse signal than from signals having other waveforms.
  • the pulse signal can be generated by some digital circuitry, as logic gates and inverters.
  • the harmonic to be used for calibration is a harmonic of an order greater than 20.
  • This aspect of the invention takes account of the beneficial concept to use a basic digital clock signal of a rather low frequency compared to the radio frequency of the receiver.
  • harmonic 38 is suitable. If, for example, the basic clock signal has a frequency of 25 MHz, the 80 th harmonic of the clock signal is in the range of 2 GHz.
  • the harmonics having a respective high order provide still sufficiently large amplitudes for calibration.
  • the method comprises the step of using the rising slopes and falling slopes of the periodic pulse signals. Accordingly, the repetition rate of the test signal, i.e.
  • the digital clock signal is increased.
  • the ratio of the peak- value of the digital clock signal versus the rms-value (root mean square) of the desired harmonic can be decreased by increasing the repetition rate. Therefore, this aspect of the invention might be useful for some applications.
  • the method comprises the step of calibrating the amplitude and calibrating the phase of the receiver, wherein calibrating the amplitude is carried out before calibrating the phase.
  • calibrating the amplitude is carried out before calibrating the phase.
  • the amplitude and the phase error are the two possible errors which can be corrected in a receiver having a typical quadrature down converter. If the amplitude is corrected in a first step, the amplitude error can not affect the phase error during the second calibration step. Therefore, the above method steps, in the defined order, are useful for achieving high image rejection levels of 50 - 60 dB. If the phase is corrected first, the amplitude error influences the result and the over-all calibration result is inferior.
  • the method includes the step of calibrating the delay between two paths of the receiver by determining the amplitude error and the phase error for different oscillating frequency values of the local oscillator.
  • a delay will result in a frequency dependent phase-error.
  • the object of the present invention is also solved by an electronic device including digital circuitry for generating a first periodic digital clock signal, wherein the first periodic digital clock signal is adapted to be applied to an entry point of a receiver, such that the receiver can be calibrated by use of a harmonic of the first periodic digital clock signal.
  • the calibration signal can be considered to be the entire digital signal including the harmonic. It is also possible to filter the digital signal in order to suppress some of the undesired signal components.
  • the calibration signal can be injected at any possible input point at the receiver to be calibrated.
  • the calibration signal is coupled to an input of a low noise amplifier of the receiver.
  • the electronic device includes a integrated receiver, wherein the digital circuitry for generating the digital periodic clock signal, is integrated together with the receiver.
  • the digital circuitry for generating the digital periodic clock signal is integrated together with the receiver.
  • the circuitry for calibration is based on small digital circuitry this concepts supports easy manufacturing and a high quality of receivers. External calibration procedures are not needed anymore.
  • the receiver is enabled to carry out self-calibration by integrating the calibration circuits in the same device, the whole concept may be used in a beneficial manner for calibrating transmitters by use of calibrated receiver. Further, the concept can also be applied for transceivers.
  • the electronic device includes further digital circuitry for generating a second periodic digital clock signal, the second periodic digital clock signal being coupled with the first digital clock signal for generating a pulse signal.
  • the digital circuitry for providing the clock signal can be implemented based on a phase locked loop or a delay locked loop.
  • the method and circuitry is preferably used to for calibrating the image rejection, the second order intercept, the cut-off frequency of any filtering in the receiver, be it high-pass, low-pass or band-pass filtering.
  • Fig. 1 shows a simplified schematic of a circuitry to be used as a part of the test signal generator according to a first embodiment of the present invention
  • Fig. 2 shows a waveform diagram for the circuitry of Fig. 1
  • Fig. 3 shows the frequency domain signals of the upper waveform (pulse) shown in Fig. 2
  • Fig. 4 shows a simplified block diagram of a receiver and possible input points for a calibration signal according to an aspect of the present invention
  • Fig. 5 shows a simplified diagram illustrating a receiver architecture with a phase shift for Cartesian signals
  • Fig. 6 shows a simplified diagram illustrating the correction of amplitude and phase error for quadrature down-conversion according to an aspect of the invention
  • Fig. 7 shows a simplified block diagram relating to a time delay in one path.
  • the test signal generator includes three invertors INVl to INV3 and a single AND gate.
  • the input signal may be a digital 25 MHz clock signal, which is delayed and inverted by the inverters INVl to INV3.
  • the input signal is also applied to the AND gate by a direct path without further delay or inversion.
  • the AND gate receives a delayed and a non-delayed version of the input clock signal IN.
  • the AND gate produces an output signal OUT in form of a small pulse with a peak-to-peak value of approximately the supply voltage (e.g. 1 Vpp).
  • the repetition rate of the pulse signal corresponds to the period of the input clock signal IN.
  • the frequency of the input signal might be assumed to be 25 MHz. In this case, the repetition rate of the output signal OUT amounts also to 25 MHz.
  • Fig. 2 shows the waveforms of the input and output signals of the configuration shown in Fig. 1 in a simplified manner.
  • the digital signal S3 after propagating through the inverters INVl to INV3 of Fig. 1 is delayed and inverted with respect to the input signal S2 propagating through the direct path to the AND gate.
  • a short pulse Sl appears, which has a width being equivalent to the delay of the three inverters INVl to INV3.
  • Fig. 2 serves only to illustrate the principle.
  • the time scale and the proportions of the pulse width versus the period of the signals as indicate in Fig. 2 may deviate considerably from realistic proportions.
  • Fig. 3 shows the spectrum in the frequency domain of the pulse signal OUT of Fig. 1 and Fig.2. This gives a rough estimate of the signal power of each of the harmonics.
  • the harmonics Around 2 GHz, the harmonics have a peak value of -42 dBVp or an rms- value of -45 dBVrms or 5.6 mVrms. These considerations are particularly important for the applicability of the present invention.
  • the appropriate input locations for the calibration signals relate to the amplitudes and power levels of the calibration signals. If a signal is to be input at certain point of the receiver, care has to be taken not to overload the input. This aspect of the invention will be illustrated with respect to Fig. 4.
  • Fig. 4 shows a simplified diagram for a receiver including an antenna AN, a low noise amplifier LNA, and a front end filter FEF.
  • a calibration signal could be applied.
  • the amplitude levels will be in the range of the supply voltage of the circuitry. Applying such high voltage levels to the LNA will let the LNA overload. For example, if the voltage levels of the digital clock signal used to provide the harmonics (e.g. the amplitudes of the periodic short pulse signal produced by the circuitry shown in Fig. 1) amount to 1 Vpp, the signal will overdrive the complete front-end (e.g. the LNA) in the receiver. If an 1 dB compression level of -30 dBm (or 7 mVrms into 50 Ohm) is assumed, the calibration signal, i.e. the periodic short pulse signal produced by the circuit in Fig.
  • the calibration signal i.e. the periodic short pulse signal produced by the circuit in Fig.
  • a signal, which is attenuated as described above is still applicable for DCS 1800 applications.
  • the noise level of the receiver is specified to be around -116 dBm for a 200 kHz bandwidth.
  • the test signal i.e. the harmonic used for calibration
  • the test signal provides an SNR of 41 dB. If this SNR is not sufficient, integration over a certain time interval can improve the SNR up to any required value.
  • the front end filter may provide a filter characteristic for GSM applications in the range of 925 to 960 MHz.
  • a maximum transmission power level of -57 dBm during reception for the purpose of accurate reception is allowed.
  • the same level is relevant for calibration.
  • the test signal is an in-band signal, which will be directly radiated, if it is coupled to the antenna.
  • a test signal of -75 dBm provides a sufficient margin with respect to this requirement. This is due to regulatory requirements.
  • Fig. 5 shows a simplified diagram illustrating a receiver architecture for Cartesian radio signals, wherein a phase shift in the A-branch is present
  • RF- or IF-f ⁇ lter limit the frequency range of the input radio signals and attenuate the non-relevant frequency components. If a receiver should be calibrated at a frequency of 2 GHz, which is the 80 th harmonic of the 25 MHz test signal, the respective 80 th harmonic of the input signal is to be extracted from the digital clock signal. If the intermediate frequency is 200 kHz, the local oscillator is adjusted to 2000.2 MHz. This requires a fractional -n synthesizer.
  • the 2 GHz signals will be mixed down to 200 KHz in the I- and Q-path.
  • a corresponding error in phase and amplitude is present in the I- and Q-path, which can be detected by the digital part of the receiver. Further, the detected errors may be corrected in the analog or digital part of the receiver as described below. If a 25 MHz repetition rate test signal is used, a calibration at every 25 MHz can be performed over the whole frequency range of the receiver.
  • An important aspect of the present invention is the large amplitude of the test signal and the relatively low amplitude of the harmonics.
  • the large amplitude of the test signal can overload the receiver front end.
  • the ratio of the peak value of the signal versus the root means square (rms) value of the desired frequency component can be reduced by generating pulses with a higher repetition rate.
  • this higher repetition rate entails a reduced number of possible frequencies, which are available for calibration.
  • Calibration at multiple intermediate frequencies may be performed by changing the LO frequency.
  • An option to increase the repetition rate of the test signal consists in using both, the up-going and the down-going slopes of the 25 MHz clock signal. Accordingly, the circuit shown in Fig.
  • the outputs of the two end gates can be combined in a third end gate in order to create a pulse repetition rate of 50 MHz.
  • This approach relies basically on digital gates, which allows easy transfer from one technology to another.
  • the test signal generated as described above can be used for calibrating the image rejection, the second order intercept, and the cut off frequency of any filtering implemented in the receiver.
  • the filter might be a high pass, low pass, or a band pass filter.
  • circuit shown in Fig. 1 uses a couple of inverters for the delay of the input clock signal, it is also possible to use resistors, inductors, capacitors, or any other kind of slew rate limited inverters in order to realize the delay. Further, there are numerous techniques to increase the repetition rate of the test signal as for example by use of a delay locked loop (DLL) or a phase locked loop (PLL). DLLs and PLLs can be used to generate higher harmonics.
  • DLL delay locked loop
  • PLL phase locked loop
  • Another possibility to create a higher repetition rate is to use a long inverter- like delay line and combining multiple slopes of multiple inverter outputs. Due to unbalances in the delays, the amplitude distribution of the harmonics may not be equal, which can be solved by implementing a programmable attenuator, through which the test signal is coupled into the receiver.
  • transmitter applications can also benefit from the invention.
  • an un-calibrated transmitter signal can be connected to the receiver.
  • the received signal can be examined for any mis-alignment in order to calibrate the transmitter in response to any detected deficiencies.
  • the filtering in the analog or digital part of the receiver can be used to attenuate any undesired harmonic of the test signal. Accordingly, unwanted frequency components of the test signal are suppressed in order to prevent them from interfering in the calibration procedure.
  • Fig. 6 shows a simplified diagram illustrating the correction of amplitude and phase error for quadrature down-conversion.
  • the amplitude and phase errors can be assumed to correspond to the errors shown in Fig. 5.
  • Two possible errors are considered within the quadrature down-conversion unit. These are the phase error, which is represented by ⁇ , and an amplitude error, which is represented by ⁇ . These are the only possible errors that the system outlined above can detect on the basis of the two sinusoidal signals at the output.
  • the outputs are the signals at the right-hand side of the Figure: Asin(%) for the I-path and Acos((7) for the Q-path.
  • the image produced by this down-conversion unit is best for the smallest phase and amplitude error.
  • the phase and the amplitude error are measured as follows. In order to evaluate the amplitude error, the power in each of the I- and Q- paths is determined and the difference is calculated. This is carried out by squaring and integrating each signal over a suitable period of time. This can be done without any pre-knowledge of the phase error. In a second step, the phase difference between the two signals is determined. In particular, it is to be determined, how close the two signals are to ideal quadrature. This is usually done by multiplying the I- and Q-signals with each other. This results in the following expression:
  • ⁇ can be determined, since ⁇ and A are known from the previous amplitude measurements.
  • the amplitude error is determined before the phase error. Accordingly, the amplitude values to be used in the above equation can already be corrected, which reduces the error in the calculated value of ⁇ . This is particularly beneficial for image rejection values of about 50 to 60 dB. If the phase error and the amplitude error are determined, the receiver can be calibrated in order to compensate the measured deficiencies. The adjustment of the circuit is based on the trigonometric identity:
  • a cos (cost - ⁇ + ⁇ ) A cos (cost + ⁇ ) cos ⁇ + A sin (cost + ⁇ ) sin ⁇
  • Fig. 7 shows a simplified block diagram relating to a time delay in one path. Adding a small amount of the I-path signal to the Q-path signal causes a correction in phase, which is independent of the test frequency COs. Accordingly, it can be assumed that the phase error is independent of the frequency. If no additional measurements were taken at other frequencies, this is rough approximation of the real situation.
  • the delay in the I-path or the Q-path can be estimated.
  • One possibility consists in compensating the delay only during the IF processing as shown in Fig. 7.
  • an estimate of T can be obtained. In this case, the error is easily cancelled by implementing a specific delay in the respective other path. If the signals propagating in this part of the system are over-sampled, delay compensation can be improved.

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  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Monitoring And Testing Of Transmission In General (AREA)

Abstract

La présente invention concerne un procédé de calibration d'un récepteur radiofréquence, qui comprend les étapes suivantes : fournir un signal d'horloge numérique, de telle sorte qu'une composante harmonique du signal d'horloge numérique puisse être utilisée comme un signal de calibration pour le récepteur, et envoyer le signal d'horloge numérique vers une entrée du récepteur radio de façon à calibrer le récepteur en utilisant la composante harmonique.
PCT/IB2007/054386 2006-11-14 2007-10-29 Générateur de signaux, et procédé de génération de signaux pour des récepteurs radiofréquence WO2008059391A1 (fr)

Applications Claiming Priority (2)

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EP06124043 2006-11-14
EP06124043.8 2006-11-14

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WO2008059391A1 true WO2008059391A1 (fr) 2008-05-22

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Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB570636A (en) * 1943-10-22 1945-07-16 Marconi Wireless Telegraph Co Improvements in tuning arrangements for radio-receivers
US2393856A (en) * 1944-10-12 1946-01-29 Collins Radio Co Calibration system for radio receivers
US4169245A (en) * 1972-07-26 1979-09-25 E-Systems, Inc. Spectral correlation
US4331941A (en) * 1980-02-29 1982-05-25 Hewlett-Packard Company Digital phase domain amplitude modulation method and apparatus
EP0475705A2 (fr) * 1990-09-14 1992-03-18 Ford Motor Company Limited Alignement d'un filtre HF utilisant l'horloge d'un processeur numérique
US5826180A (en) * 1994-08-08 1998-10-20 Nice Systems Ltd. Near homodyne radio frequency receiver
EP1467507A2 (fr) * 2003-04-09 2004-10-13 Broadcom Corporation Procédé et dispositif de conservation de synchronisation dans un système de communication
US20050181754A1 (en) * 1999-10-21 2005-08-18 Stephen Wu Adaptive radio transceiver with calibration
US7088765B1 (en) * 2000-03-15 2006-08-08 Ndsu Research Foundation Vector calibration system

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB570636A (en) * 1943-10-22 1945-07-16 Marconi Wireless Telegraph Co Improvements in tuning arrangements for radio-receivers
US2393856A (en) * 1944-10-12 1946-01-29 Collins Radio Co Calibration system for radio receivers
US4169245A (en) * 1972-07-26 1979-09-25 E-Systems, Inc. Spectral correlation
US4331941A (en) * 1980-02-29 1982-05-25 Hewlett-Packard Company Digital phase domain amplitude modulation method and apparatus
EP0475705A2 (fr) * 1990-09-14 1992-03-18 Ford Motor Company Limited Alignement d'un filtre HF utilisant l'horloge d'un processeur numérique
US5826180A (en) * 1994-08-08 1998-10-20 Nice Systems Ltd. Near homodyne radio frequency receiver
US20050181754A1 (en) * 1999-10-21 2005-08-18 Stephen Wu Adaptive radio transceiver with calibration
US7088765B1 (en) * 2000-03-15 2006-08-08 Ndsu Research Foundation Vector calibration system
EP1467507A2 (fr) * 2003-04-09 2004-10-13 Broadcom Corporation Procédé et dispositif de conservation de synchronisation dans un système de communication

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