WO2008057829A3 - Mesochronous clock system and method to minimize latency and buffer requirements - Google Patents

Mesochronous clock system and method to minimize latency and buffer requirements Download PDF

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Publication number
WO2008057829A3
WO2008057829A3 PCT/US2007/082859 US2007082859W WO2008057829A3 WO 2008057829 A3 WO2008057829 A3 WO 2008057829A3 US 2007082859 W US2007082859 W US 2007082859W WO 2008057829 A3 WO2008057829 A3 WO 2008057829A3
Authority
WO
WIPO (PCT)
Prior art keywords
clock signal
clock
mesochronous
minimize latency
domain
Prior art date
Application number
PCT/US2007/082859
Other languages
French (fr)
Other versions
WO2008057829A2 (en
Inventor
Nitin Godiwala
Matthew H Reilly
Original Assignee
Sicortex Inc
Nitin Godiwala
Matthew H Reilly
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/594,442 external-priority patent/US7689856B2/en
Priority claimed from US11/594,441 external-priority patent/US20080109672A1/en
Application filed by Sicortex Inc, Nitin Godiwala, Matthew H Reilly filed Critical Sicortex Inc
Publication of WO2008057829A2 publication Critical patent/WO2008057829A2/en
Publication of WO2008057829A3 publication Critical patent/WO2008057829A3/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H04L7/0012—Synchronisation information channels, e.g. clock distribution lines by comparing receiver clock with transmitter clock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0091—Transmitter details
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0602—Systems characterised by the synchronising information used
    • H04J3/0605—Special codes used as synchronising signal
    • H04J3/0608—Detectors therefor, e.g. correlators, state machines

Abstract

A mesochronous clock system and method to minimize latency and buffer requirements for data transfer in a large multiprocessor computing system. A stream of data is transferred from a first clock domain with a first clock signal to a second clock domain with a second clock signal. The first and second clock signals have a mesochronous relationship. The first clock signal is sampled in the second clock domain. In response to the sampling of the first clock signal, a modified version of the first clock signal is formed having a known phase relationship to the second clock signal. A parallel form of the received data is formed under the control of modified version of the first clock signal. In response to the sampling of the first clock signal, a subset of contiguous bits of the parallel data is selected for use in the second clock domain.
PCT/US2007/082859 2006-11-08 2007-10-29 Mesochronous clock system and method to minimize latency and buffer requirements WO2008057829A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/594,442 US7689856B2 (en) 2006-11-08 2006-11-08 Mesochronous clock system and method to minimize latency and buffer requirements for data transfer in a large multi-processor computing system
US11/594,441 2006-11-08
US11/594,441 US20080109672A1 (en) 2006-11-08 2006-11-08 Large scale computing system with multi-lane mesochronous data transfers among computer nodes
US11/594,442 2006-11-08

Publications (2)

Publication Number Publication Date
WO2008057829A2 WO2008057829A2 (en) 2008-05-15
WO2008057829A3 true WO2008057829A3 (en) 2008-07-24

Family

ID=39365211

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/082859 WO2008057829A2 (en) 2006-11-08 2007-10-29 Mesochronous clock system and method to minimize latency and buffer requirements

Country Status (1)

Country Link
WO (1) WO2008057829A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160132072A1 (en) * 2014-11-10 2016-05-12 Intel Corporation Link layer signal synchronization

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5838749A (en) * 1995-06-05 1998-11-17 Broadband Communications Products, Inc. Method and apparatus for extracting an embedded clock from a digital data signal
US20050276322A1 (en) * 2004-06-14 2005-12-15 Rambus, Inc. Hybrid wired and wireless chip-to-chip communications
US6987823B1 (en) * 2000-02-07 2006-01-17 Rambus Inc. System and method for aligning internal transmit and receive clocks
US20060092969A1 (en) * 2000-09-13 2006-05-04 Susnow Dean S Multi-lane receiver de-skewing

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5838749A (en) * 1995-06-05 1998-11-17 Broadband Communications Products, Inc. Method and apparatus for extracting an embedded clock from a digital data signal
US6987823B1 (en) * 2000-02-07 2006-01-17 Rambus Inc. System and method for aligning internal transmit and receive clocks
US20060092969A1 (en) * 2000-09-13 2006-05-04 Susnow Dean S Multi-lane receiver de-skewing
US20050276322A1 (en) * 2004-06-14 2005-12-15 Rambus, Inc. Hybrid wired and wireless chip-to-chip communications

Also Published As

Publication number Publication date
WO2008057829A2 (en) 2008-05-15

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