WO2008050452A1

WO2008050452A1 - Plasma display panel and its driving method

Info

Publication number: WO2008050452A1
Application number: PCT/JP2006/321550
Authority: WO
Inventors: Takashi Sasaki; Akihiro Takagi
Original assignee: Hitachi Plasma Display Limited
Priority date: 2006-10-27
Filing date: 2006-10-27
Publication date: 2008-05-02

Abstract

A plasma display panel is provided with a first substrate on which a plurality of first and second electrodes are formed in parallel with each other, a plurality of third electrodes disposed in the substantially vertical direction with respect to the first and second electrodes, longitudinal partition walls for defining discharge spaces and a second substrate on which at least three kinds of coated fluorescent layers are formed in the defined discharge space, wherein the first substrate, the third electrodes, the partition wall and second substrate are sealed though the discharge space and the longitudinal partition walls disposed between specific two kinds of the fluorescent layers are made lower in height than the other longitudinal partition walls, so that delay at a cell of one of the fluorescent layers is eased by making use of a priming effect of a cell of the other of neighboring fluorescent layers and so that a driving margin of the plasma display panel can be enlarged.

Description

Specification

Plasma display panel and driving method thereof

Technical field

The present invention relates to a plasma display panel and a driving method thereof.

Background art

[0002] In a plasma display panel, a malfunction caused by an address discharge delay deteriorates the image quality. Therefore, it is necessary to improve the address discharge delay. As a method for improving the delay of the address discharge, a method of performing an address discharge in a region without performing a sustain discharge between cells has been proposed. For example, by providing a display discharge cell in which a sustain discharge is performed and an address discharge cell that is formed separately from the display discharge cell and communicates with the display discharge cell through a gap, an address discharge cell is provided. A plasma display panel having a stable characteristic has been proposed (for example, see Patent Document 1).

However, in the method of performing address discharge in a region where sustain discharge between cells is not performed, a discharge region different from the region where sustain discharge is performed must be provided, and discharge is performed between cells. It cannot be applied to a plasma display panel with a structure that does not have a large area.

[0004] Patent Document 1: Japanese Patent Application Laid-Open No. 2003-31131

Disclosure of the invention

[0005] An object of the present invention is to provide a plasma display panel capable of improving a delay in address discharge and expanding a drive margin, and a driving method thereof.

[0006] The plasma display panel of the present invention is arranged in a direction substantially perpendicular to the first substrate on which a plurality of first and second electrodes arranged in parallel are formed, and the first and second electrodes A plurality of third electrodes, vertical barrier ribs defining discharge spaces corresponding to the third electrodes, and at least three kinds of phosphor layers applied in the discharge spaces partitioned by the vertical barrier ribs are formed. 2 is sealed through a discharge space, and among the at least three types of phosphor layers, the height of the vertical barrier ribs disposed between the two specific phosphor layers is higher than the other vertical barrier ribs. Specially made low It is a sign.

The plasma display panel driving method of the present invention includes a first substrate on which a plurality of first and second electrodes arranged in parallel are formed, and a direction substantially perpendicular to the first and second electrodes. A plurality of arranged third electrodes, a medial wall defining a discharge space corresponding to the third electrode, and at least three types of phosphor layers applied in the discharge space defined by the vertical partition are formed. The height of the vertical barrier rib arranged between two specific phosphor layers out of at least three phosphor layers is sealed with the second substrate thus formed through the discharge space. When address discharge is performed in a cell of a phosphor layer having a high emission luminance among two specific types of phosphor layers in a plasma display panel formed lower than the vertical barrier rib, the two specific types of phosphor layers Of the phosphor layer with low emission brightness should be addressed. It is characterized by.

[0007] According to the present invention, the height of the vertical barrier rib arranged between two specific types of phosphor layers is made lower than the other vertical barrier ribs, so that the address of one phosphor layer in the cell It becomes possible to mitigate the discharge delay by utilizing the priming effect of the cell of the other phosphor layer adjacent to the discharge.

Brief Description of Drawings

[0008] FIG. 1 is a diagram showing a configuration example of a plasma display device according to an embodiment of the present invention.

FIG. 2 is an exploded perspective view showing a structural example of a plasma display panel in an embodiment of the present invention.

FIG. 3A is a plan view of a plasma display panel according to an embodiment of the present invention.

FIG. 3B is a cross-sectional view schematically showing between I and I shown in FIG. 3A.

FIG. 4 is a plan view of a plasma display panel according to another embodiment of the present invention.

FIG. 5 is a diagram schematically showing a cross section of a plasma display panel in another embodiment of the present invention.

FIG. 6 is a conceptual diagram showing a configuration example of each field in the embodiment of the present invention. FIG. 7 is a diagram showing an example of a driving waveform of the plasma display device in the embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram illustrating a configuration example of a plasma display device according to an embodiment of the present invention. The plasma display device in this embodiment includes a plasma display panel 1, a sustain drive circuit 2, a scan drive circuit 3, an address drive circuit 4, a control circuit 5, and a power supply circuit 6.

The sustain drive circuit 2 has a circuit force that repeats sustain discharge (sustain discharge), and supplies a predetermined voltage to a plurality of X electrodes (sustain electrodes) XI, X2,..., Xn. Hereinafter, each of the X electrodes XI, X2,..., Xn or their generic name is referred to as an X electrode Xi, and i means a subscript.

[0012] The scan driving circuit 3 includes a circuit that selects a row to be displayed by line-sequential scanning and a circuit that repeats sustain discharge, and includes a plurality of Y electrodes (scan electrodes) Yl, Υ2, ..., Υη Supply a predetermined voltage to Hereinafter, each of Υ electrode Yl, Υ2,..., Υη or their generic name is called Υ electrode Yi, and i means a subscript.

[0013] The address driving circuit 4 has a circuit power for selecting a column to be displayed, and supplies a predetermined voltage to the plurality of address electrodes A1, A2,. Hereinafter, each of the address electrodes Al, A2,... Or their generic name is referred to as an address electrode Aj, where j is a subscript.

The three drive circuits apply a predetermined voltage to each electrode during a reset period and a wall charge erasing period described later.

[0014] The control circuit 5 generates a control signal based on display data, a clock signal, a horizontal synchronization signal, a vertical synchronization signal, and the like input from the outside of the apparatus. The control circuit 5 supplies the generated control signal to the sustain drive circuit 2, the scan drive circuit 3, and the address drive circuit 4, and controls these drive circuits 2-4.

The power supply circuit 6 supplies a predetermined voltage to the sustain drive circuit 2, the scan drive circuit 3, the address drive circuit 4, and the control circuit 5. For example, the power supply circuit 6 supplies drive voltages to be applied to the electrodes Xi, Yi, and Aj to the sustain drive circuit 2, the scan drive circuit 3, and the address drive circuit 4. The

In the plasma display panel 1, the Y electrode Yi and the X electrode Xi form a row extending in parallel in the horizontal direction, and the address electrode Aj forms a column extending in the vertical direction. Y electrode Yi and X electrode Xi are alternately arranged in the vertical direction. That is, the Y electrode Yi and the X electrode Xi are arranged in parallel to each other, and the address electrode Aj is arranged in a direction substantially perpendicular to the Y electrode Yi and the X electrode Xi. Y electrode Yi and address electrode Aj form a two-dimensional matrix of i rows and j columns. Note that the electrodes may be arranged such that a set of electrodes Xi, Yi, X (i + 1), Y (i + 1) is repeatedly arranged in the vertical direction. There is also a structure in which the Y electrode Yi forms a row not only with the X electrode Xi but also with the X electrode X (i + 1).

The cell Cij is formed by the intersection of the Y electrode Yi and the address electrode Aj and the X electrode Xi adjacent thereto corresponding thereto. This cell Cij corresponds to, for example, red (R), green (G), and blue (B) sub-pixels, and one pixel is constituted by these three sub-pixels. Panel 1 displays an image by lighting a plurality of pixels arranged two-dimensionally. Line order in scan drive circuit 3 Determines which cell is lit by the next scan circuit and address drive circuit 4, and repeatedly discharges by sustain drive circuit 2 and the circuit that repeats sustain discharge in scan drive circuit 3 By performing the above, the display operation in the plasma display device is performed.

FIG. 2 is an exploded perspective view showing a structural example of the plasma display panel 1 in the present embodiment.

The X electrode 11 corresponds to the X electrode Xi shown in FIG. 1, and the Y electrode 12 corresponds to the Y electrode Yi shown in FIG. The X electrode 11 and the Y electrode 12 are formed on the front glass substrate 10 so as to be parallel to each other. A dielectric layer 13 for accumulating wall charges is deposited thereon. Further thereon, an MgO (acid magnesium) protective layer 14 is deposited.

Further, the address electrodes 15R, 15G, 15B correspond to the address electrode Aj shown in FIG. The address electrodes 15R, 15G, and 15B are formed on the rear glass substrate 19 disposed so as to face the front glass substrate 10 in a direction perpendicular to the X electrode 11 and the Y electrode 12 (so as to intersect). A dielectric layer 16 is deposited on the address electrodes 15R, 15G, 15B. Furthermore, red, green and blue phosphors 18R, 18G and 18B are deposited thereon. Also, vertical barrier ribs (vertical barriers) that divide the discharge space on both sides of the address electrodes 15R, 15G, and 15B. (Rib) 17 is formed, and phosphors 18 are arranged and applied in stripes for each color on the inner surface.

Note that there is a structure in which horizontal ribs are provided to form lattice-like ribs. In this case, the phosphor 18 is applied in the eyes of the lattice.

Specifically, as shown in FIG. 2, a red phosphor layer 18R is formed above the address electrode 15R, a green phosphor layer 18G is formed above the address electrode 15G, and the address electrode 1 A blue phosphor layer 18B is formed above 5B. Further, a vertical partition wall 17RG is disposed between a red phosphor layer 18R formed corresponding to the address electrode 15R and a green phosphor layer 18G formed corresponding to the address electrode 15G. Similarly, a vertical partition 17GB is disposed between the green phosphor layer 18G and the blue phosphor layer 18B formed corresponding to the address electrode 15B, and the blue phosphor layer 18B and the red phosphor layer 18R. A vertical partition 17 BR is disposed between the two.

[0021] The discharge between the X electrode 11 and the Y electrode 12 excites the phosphors 18R, 18G, and 18B to emit each color. The front glass substrate 10 and the back glass substrate 19 are sealed, and Ne + Xe pegging gas or the like is sealed in the inside (the discharge space between the front glass substrate 10 and the back glass substrate 19).

Here, the delay of the address discharge in the cells of the phosphor layer 18G is larger than the delay of the address discharge in the cells of the other phosphor layers 18R and 18B. In addition, the phosphor layers 18R and 18B adjacent to the phosphor layer 18G have lower emission luminance in the phosphor layer 18B. Therefore, in this embodiment, the vertical partition 17GB disposed between the phosphor layers 18G and 18B is disposed between the vertical partition 17RG and the phosphor layers 18B and 18R disposed between the phosphor layers 18R and 18G. The height of the partition wall is lower than the vertical partition wall 17 BR.

[0023] In this way, the priming effect by the address discharge performed in the phosphor layer 18B cell is utilized in the phosphor layer 18G cell by making the vertical partition wall 17GB lower than the vertical partition walls 17RG and 17BR. And delay of address discharge in the phosphor layer 18G cell can be mitigated. In the plasma display panel 1 according to the present embodiment, since the heights of the vertical partition walls 17RG, 17GB, and 17BR are different as described above, the heights of the applied phosphor layers 18R, 18G, and 18B are also different. [0024] As a method for making the vertical partition 17GB and the vertical partition 17RG, 17BR different in height, for example, the horizontal width of the vertical partition 17GB before firing the partition may be made wider than that of the vertical partition 17RG, 17BR. By forming the width of the vertical partition 17GB before firing the partition larger than that of the vertical partitions 17RG and 17BR, the vertical partition 17GB can be made lower than the vertical partition 17RG and 17BR by heat shrinkage after firing. Monkey.

FIG. 3A is a plan view of the plasma display panel 1 in the present embodiment. In FIG. 3A, the same components as those shown in FIG. 2 are denoted by the same reference numerals.

In FIG. 3A, 11a is a metal electrode (bus electrode) in the X electrode, and l ib is a transparent electrode in the X electrode. The metal electrode (bus electrode) 11a and the transparent electrode l ib constitute the X electrode 11 shown in FIG.

Similarly, 12a is a metal electrode (bus electrode) in the Y electrode and 12b is a transparent electrode in the Y electrode. The metal electrode (bus electrode) 12a and the transparent electrode 12b constitute the Y electrode 12 shown in FIG.

Here, in FIG. 3A, the T-shaped transparent electrode l ib and the transparent electrode 12b are shown as an example. The shape of the transparent electrode l ib and the transparent electrode 12b is not limited to this. Any conventionally known shape can be applied.

[0028] The metal electrode (bus electrode) 11a in the X electrode and the metal electrode (bus electrode) 12a in the Y electrode are arranged in parallel to each other, and the address electrodes 15R, 15G, and 15B are arranged so as to intersect with each other. Vertical partition walls 17RG, 17GB, and 17BR are arranged on both sides of the address electrodes 15R, 15G, and 15B. In FIG. 3A, the width of the vertical partition wall 17GB is widened, and the height of the vertical partition wall 17GB is lower than that of the vertical partition walls 17RG and 17BR.

FIG. 3B is a diagram schematically showing a cross section between I and I shown in FIG. 3A. In FIG. 3B, the same components as those shown in FIG. 2 are denoted by the same reference numerals. FIG. 3B shows only a cross section of the plasma display panel 1 on the rear glass substrate 19 side.

As described above, the back glass substrate 19 is provided with the address electrodes 15 R, 15 G, and 15 B and is covered with the dielectric layer 16. Vertical partition 17RG between address electrodes 15R and 15G The vertical barrier ribs 17GB are disposed between the address electrodes 15G and 15B, and the vertical barrier ribs 17BR are disposed between the address electrodes 15B and 15R. Phosphor layers 18R, 18G, and 18B are separately coated on the side surfaces of the dielectric layer 16 and the vertical barrier ribs 17RG, 17GB, and 17BR on the address electrodes 15R, 15G, and 15B.

[0031] The vertical partition wall 17GB is formed to be lower by D1 than the height HI of the vertical partition walls 17RG and 17BR. Normally, the height of the vertical partition walls is 130 to 160 / ζ πι. If the height HI of the vertical partition walls 17RG and 17BR is about 150 / zm, the height of the vertical partition walls 17GB and the height of the vertical partition walls 17RG and 17BR The difference D1 is 5 m or more so that the height of the partition walls is clearly different and 20 μm or less so as not to receive the sustain discharge crosstalk, and 5 / z πι to 10 / ζ m is desirable.

[0032] In order to realize the difference D1 between the height of the vertical partition 17GB and the height of the vertical partitions 17RG and 17BR, for example, the width W of the vertical partition 17RG and 17BR at the upper surface of the partition, so-called rib top,

RG

When W is about 50 / z m, the width W of the vertical partition 17GB is 30% larger than W and W.

BR GB RG BR

The comb is approximately 65 m.

[0033] Here, as shown in FIG. 3B, the widths W and W of the vertical partition walls 17RG and 17BR and the vertical partition wall 17GB

RG BR

Different from width W, but distance between adjacent vertical partition walls 17BR, 17RG, 17GB, 17BR

GB R

, L and L are substantially equal. Temporarily, only the width W of the vertical partition 17GB was increased.

G B GB

In this case, the cell of the green phosphor layer 18G and the cell of the blue phosphor layer 18B! The discharge space (light emitting part) becomes narrow and the aperture ratio (opening area) decreases and the color balance is lost. Shimatsu.

However, as in this embodiment, the distances L, L, and L between adjacent vertical partition walls are made substantially equal.

R G B

Even if the width W is larger than the widths W and W, the cells of the phosphor layers 18R, 18G, and 18B are connected.

GB RG BR

V, the discharge space (light emitting part) can be made substantially the same size and the aperture ratio (opening area) can be made uniform, and the color balance can be prevented from being lost.

[0035] In the present embodiment described above, the force that lowers the height of the vertical partition walls 17RG and 17BR over the entire length of the vertical partition walls 17GB, as shown in Fig. 4, is a partial height of the vertical partition walls 17GB. May be lowered.

FIG. 4 is a plan view of a plasma display panel 1 according to another embodiment of the present invention. In FIG. 4, the same components as those shown in FIG. Is attached. In FIG. 4, in order to reduce the delay of the address discharge using the priming effect of the adjacent cell, the height of the vicinity 41 of the Y electrodes 12a and 12b that perform address discharge with the address electrode is set to other heights. It is designed to be lower than the vertical partition.

[0037] In the plasma display panel 1 shown in FIG. 4, the horizontal width of the vertical partition 17GB is the same as the horizontal partition 17RG and 17BR except for a part 41. Accordingly, the height of the vertical partition walls 17 GB is substantially equal to the height of the vertical partition walls 17RG and 17BR except for the vicinity 41 of the Y electrodes 12a and 12b.

On the other hand, the width of the vertical partition 17GB in the vicinity 41 of the Y electrodes 12a and 12b is wider than the other medial walls, and the height of the vertical partition 17GB in the vicinity 41 is lower than the other vertical partitions. ing.

FIG. 5 is a view schematically showing a cross section of the plasma display panel 1 in another embodiment of the present invention. FIG. 5 shows only the cross section of the plasma display panel 1 on the side of the rear glass substrate 19 as in FIG. 3B, and the same components as those shown in FIG. 3B are denoted by the same reference numerals. ing.

[0039] In the plasma display panel shown in FIG.

GB

Bulkheads 17RG and 17BR, when the width W and W are larger than the vertical partition 17GB and adjacent to it

RG BR

Distance between adjacent vertical bulkheads 17RG, 17GB L, L, between other vertical bulkheads 17BR and 17RG

G B

The distance is larger than L.

R

[0040] By making the distances L and L larger than the distance L in this way, the cell of the green phosphor layer 18G

G B R

In addition, the light emission in the cell of the blue phosphor layer 18B can be increased to make the width of the vertical partition wall 17GB inconspicuous, and the deterioration of display quality can be suppressed. Note that the distance L between the vertical barrier ribs 17GB and 17RG corresponding to at least the green phosphor layer 18G with high brightness is the vertical barrier rib.

G

Distance between 17BR and 17RG should be larger than L, but between vertical partition walls 17GB and 17BR

R

The distance L is preferably larger than the distance L between the vertical partition walls 17BR and 17RG.

B R

Next, a method for driving the plasma display device in the embodiment of the present invention will be described.

FIG. 6 is a conceptual diagram showing a configuration example of each field according to the present embodiment. In the present embodiment, the image is formed in, for example, 60 fields Z seconds. One field, for example, 10 Subfields (first subfield 21, second subfield 22,..., Tenth subfield 30). Each subfield 21-30 includes a reset period Tr, an address period Ta, and a sustain (sustain discharge) period Ts. The sustain period T s may include a wall charge erasing period Te for reducing wall charges.

In the reset period Tr, a predetermined voltage is applied to the X electrode Xi and the Y electrode Yi to initialize the cell Cij. At this time, a predetermined voltage may be applied to the address electrode Aj.

In the address period Ta, light emission or non-light emission of each cell Cij is selected by address designation. In the address period Ta, a scan panel is applied to the Y electrodes Yl, Υ2,..., Η by applying j scans, and the address pulses are applied to the address electrodes Aj corresponding to the scan pulses. This selects the light emission of cell Cij.

[0044] If the address pulse of the address electrode Aj is generated corresponding to the scan pulse of the Y electrode Yi, the light emission of the cell Cij formed by the Y electrode Yi, the X electrode Xi, and the address electrode Aj is selected. The If the address pulse of the address electrode Aj is not generated corresponding to the scan pulse of the Y electrode Yi, the light emission of the cell Cij formed by the Y electrode Yi, the X electrode Xi, and the address electrode Aj is not selected and is not Light emission is selected.

[0045] When an address pulse is generated in response to the scan pulse, an address discharge occurs between the address electrode Aj and the Y electrode Yi, and this is used as a spark to discharge between the X electrode Xi and the Y electrode Yi S Occur. As a result, negative charges are accumulated in the X electrode Xi, positive charges are accumulated in the Y electrode Yi, and wall charges of an amount capable of sustaining discharge are accumulated in the next sustain period Ts.

[0046] In the sustain period Ts, opposite-phase sustain pulses are applied between the X electrode Xi and the Y electrode Yi, and the X electrode Xi and Y electrode of the cell selected in the address period Ta! / Sustain discharge occurs between Yi and emits light. In each of the subfields 21 to 30 shown in FIG. 6, the number of sustain pulses applied to the X electrode Xi and the Y electrode Yi (the number of times of light emission in each subfield) is different. A plurality of subfields having the same number of times of light emission may be provided. Therefore, for each cell Cij, the gradation value can be determined by appropriately selecting light emission or non-light emission in the subfields 21 to 30.

[0047] Here, in the wall charge erasing period Te in the sustain period Ts, the normal sustain pulse is used. Sustain discharge at a lower pressure (low potential) is applied to the X electrode Xi or the Y electrode Yi, and light emission by the sustain discharge and wall charge erasure are performed in the cell Cij that emits light in the subfield. . It is also known that wall charges are erased by short pulses. In addition, erasing includes the case where wall charges are reduced to such an extent that sustain discharge cannot be maintained, and is not limited to the meaning of complete erasing. This alleviates the difference in wall charge at the end of the sustain period between the light-emitting cell Cij and the non-light-emitting cell Cij in the subfield, and the initialization operation (reset) in the reset period of the next subfield. Discharge) can be performed stably and reliably.

FIG. 7 is a timing chart showing an operation example of the plasma display device in the present embodiment. FIG. 7 shows an example of drive waveforms related to the X electrode Xi, the Y electrode Yi, and the address electrode Aj in one subfield of a plurality of subfields constituting one frame.

In FIG. 7, odd-numbered rows of X electrodes Xi and Y electrodes Yi are indicated by X electrodes Xo and Y electrodes Yo, and even-numbered rows of X electrodes Xi and Y electrodes Yi are indicated by X electrodes Xe and Y electrodes Y. ing. As for the address electrode Aj, red, green, and blue phosphors are deposited on the upper side, and the address electrodes are denoted by A (R), A (G), and A (B). ! /

[0050] As described above, one subfield is divided into a reset period Tr including a full write period and a full erase period, an address period Ta, and a sustain period Ts including a wall charge erase period Te.

[0051] In the reset period Tr, a positive ramp voltage pulse (write blunt wave) 60 in which the voltage gradually increases is applied to the Y electrodes Yo and Ye, and a predetermined negative voltage (write voltage) is applied to the X electrodes Xo and Xe. 50 is applied. After the voltage applied to the Y electrodes Yo and Ye returns to the ground level, a negative ramp voltage pulse (adjusted blunt wave) 61 that gradually decreases the voltage is applied to the Y electrodes Yo and Ye, and the X electrode A predetermined positive voltage (adjustment voltage) 51 is applied to Xo and Xe.

[0052] In this way, in the reset period Tr, discharge is performed by the Y electrodes Yo and Ye and the X electrodes Xo and Xe, and wall charge formation (entire writing) and wall charge erasing (full erase) are performed. . In the reset period Tr, all cells Cij are initialized (reset).

[0053] Next, in the address period Ta, the cell Cij is assigned in accordance with the input display data. In order to perform Z-off, address discharge is performed line-sequentially. In this embodiment, address discharge (address selection) is performed for odd-numbered rows in the first half address period Tal, and address discharge (address selection) is performed for even-numbered rows in the second half address period Ta2. )I do

In the first half address period Tal, the scan voltage 52 is applied to the X electrode Xo. In addition, when a voltage is applied to the Y electrode Yo corresponding to a certain odd-numbered display line, the scan pulse 62 is applied to the Υ electrode Υο selected by the line sequence, and a predetermined negative is applied to the non-selected Υ electrode Yo. A voltage is applied. In the first half address period Tal, a ground level voltage is applied to the X electrode Xe and the negative electrode Ye.

[0055] In the first half address period Tal, the address electrode A (R) corresponding to the cell causing the sustain discharge in each address electrode A (R), A (G), A (B), that is, the cell to emit light. , A (G), A (B) are selectively applied with address pulses 71, 81, 91 in synchronization with the scan pulse 62 of each row. As a result, a discharge occurs between the address electrodes A (R), A (G), and A (B) of the cell that emits light and the Y electrode Yo selected in line order, and this is used as a priming. As a result, wall charges of an amount capable of the next sustain discharge are accumulated on the MgO protective film surface on the X electrode Xo and the Y electrode Yo.

Similarly, in the second half address period Ta2, the scan voltage 53 is applied to the X electrode Xe. Further, the scan pulse 63 is applied to the Y electrode Ye selected by line sequential, and a predetermined negative voltage is applied to the non-selected Y electrode Ye. In the second half address period Ta2, a ground level voltage is applied to the X electrode Xo and the Y electrode Yo.

[0057] Further, in the second half address period Ta2, the address electrodes A (R), A (G), and A (B) corresponding to the cells that generate (emit light) sustain discharge are synchronized with the scan pulse 63 of each row. Address pulses 72, 82 and 92 are selectively applied. As a result, a discharge occurs between the address electrodes A (R), A (G), and A (B) of the cell that emits light and the Y electrode Ye selected in line order, and this is used as the priming (seeker) X Wall charges of the amount that can be subjected to the next sustain discharge are accumulated on the MgO protective film surface on the electrodes Xe and Y.

[0058] In the sustain period Ts, voltages having different polarities (sustain pulses, sustain pulses) 54, 55, 64, 65 are alternately applied to the X electrodes Xo, Xe and Y electrodes Yo, Ye of each display line. Then, a sustain discharge is performed between the X electrode Xo, Xe and the Y electrode Yo, Ye of the light emitting cell, and one subfield image is displayed.

[0059] In the wall charge erasing period Te in the sustain period Ts, first, a sustain pulse (pre-erase pulse) 56 similar to the normal sustain pulse 54 is applied to the X electrodes Xo and Xe, and the Y electrodes Yo and Ye are applied. A sustain pulse (high voltage pulse before erasure) 66 having a voltage higher than the normal sustain pulse 64 is applied. From this, the X electrodes Xo, Xe and Y electrodes Yo, Ye of the light emitting cell cause a stronger discharge than the normal sustain discharge between the X electrodes Xo, Xe and Y electrodes Yo, Ye of the light emitting cell. It has a lot of wall charges.

[0060] In the wall charge erasing period Te, a sustain pulse (erase pulse) 57 having a voltage lower than that of the normal sustain pulse 55 is applied to the X electrodes Xo and Xe, and a normal sustain pulse is applied to the Y electrodes Yo and Ye. A sustain pulse (erase pulse) 67 similar to 65 is applied. As a result, the normal sustain is achieved by using more wall charges than usual formed by the pre-erase pulse 56 and the pre-erase high-pressure pulse 66 between the X electrode Xo, Xe and the Y electrode Yo, Ye of the light emitting cell. It is possible to erase or reduce the wall charge between X electrode Xo, Xe and Y electrode Yo, Ye while emitting light in the cell by applying a voltage and causing sustain discharge, which is lower than in-discharge. Become 會.

In the above description, in the address period Ta, the address electrodes A (R), A (G), and A (B) corresponding to the cells that emit light according to the input display data are Address pulses are selectively applied in synchronization with the scan pulses of each row, and address discharge is performed between the address electrodes A (R), A (G), A (B) and the Y electrode Yi. In other words, the address discharge is performed in accordance with the input display data faithfully.

[0062] However, when a cell of the green phosphor layer is selected as a cell to emit light in accordance with input display data, a blue cell adjacent to the cell is caused to emit light regardless of the input data. You may make it select as a cell. That is, when an address discharge is performed in a cell of the green phosphor layer, an address discharge is simultaneously performed in the cell of the blue phosphor layer adjacent to the cell, and the address discharge delay in the cell of the green phosphor layer is adjacent. You may make it ease using the priming effect by the cell of the blue fluorescent substance layer which touches. As a result, a large address discharge delay that may cause a malfunction can be mitigated, and the operation can be reliably performed. Note that the luminance ratio between the green cell and the blue cell is approximately 6: 1, so when the green cell is lit, even if a blue cell that is not normally lit is lit, the display is conspicuous. The impact on quality is small. In particular, a subfield corresponding to a low gradation is more inconspicuous, and a subfield corresponding to a low gradation generally has a small amount of priming particles present in the discharge space, so that a high effect can be expected.

[0064] In the above-described embodiment, the height of the vertical barrier ribs is made lower than that of the other vertical barrier ribs by making the horizontal width of the vertical barrier ribs before firing the barrier ribs wider than the width of the other vertical barrier ribs. . However, the method of making the height of the vertical barrier ribs lower than other vertical barrier ribs is not limited to this.

In the above-described embodiment, a plasma display panel having only vertical barrier ribs is described as an example. However, the present invention can be applied to a plasma display panel having a horizontal barrier rib on the vertical barrier ribs. Needless to say.

[0066] In addition, each of the above-described embodiments is merely an example of a specific example for carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. Is. That is, the present invention can be implemented in various forms without departing from the technical idea or the main characteristic power thereof.

Industrial applicability

[0067] As described above, according to the present invention, the height of the vertical barrier ribs arranged between two specific types of phosphor layers is made lower than that of the other vertical barrier ribs, so that the priming effect of adjacent cells can be achieved. Can be used to reduce the delay of the address discharge and expand the drive margin, thereby realizing stable operation of the plasma display panel.

Claims

The scope of the claims

[1] a first substrate on which a plurality of first and second electrodes arranged in parallel are formed;

A plurality of third electrodes arranged in a direction substantially perpendicular to the first and second electrodes, a vertical barrier partitioning a discharge space corresponding to the third electrode, and a discharge defined by the vertical barrier ribs. A plasma display comprising: a second substrate on which at least three kinds of phosphor layers applied in an electric space are formed; and wherein the first substrate and the second substrate are sealed via a discharge space. Ray panel,

A plasma display panel characterized in that, among the at least three types of phosphor layers, the height of the vertical barrier ribs disposed between the two specific phosphor layers is lower than the other vertical barrier ribs.

[2] The plasma display panel according to claim 1, wherein a height of a part of the vertical barrier ribs arranged between the two specific types of phosphor layers is set lower than that of the other vertical barrier ribs.

[3] The two specific types of phosphor layers are a phosphor layer having a low emission luminance among a target phosphor layer and a phosphor layer disposed adjacent thereto. The plasma display panel according to claim 1.

[4] The phosphor layer includes three kinds of phosphor layers of red, green, and blue, and the green phosphor layer and the blue phosphor layer are adjacent to each other,

2. The vertical barrier rib disposed between the green phosphor layer and the blue phosphor layer has at least a part of a height lower than that of other vertical barrier ribs. Plasma display panel.

[5] The vertical barrier rib disposed between the two specific types of phosphor layers is characterized in that a portion whose height is lower than that of the other vertical barrier rib is wider than the other vertical barrier rib. The plasma display panel according to claim 1.

6. The plasma display panel according to claim 5, wherein the distance between the adjacent vertical partition walls is equal.

[7] The distance between the vertical partition wall having a height lower than that of the other vertical partition wall and at least one vertical partition wall adjacent to the vertical partition wall is greater than the distance between the other vertical partition walls. The plasma display panel according to claim 5, characterized by the above.

[8] The plasma display panel according to claim 1, wherein the at least three kinds of phosphor layers have different heights.

[9] In the vertical barrier rib arranged between the two specific types of phosphor layers, the height of the vicinity of the second electrode that performs address discharge with the third electrode is set to another vertical height. 3. The plasma display panel according to claim 2, wherein the plasma display panel is lower than the partition wall.

[10] A first substrate on which a plurality of first and second electrodes arranged in parallel are formed, and a plurality of third electrodes arranged in a direction substantially perpendicular to the first and second electrodes A second substrate on which at least three kinds of phosphor layers are formed, and vertical barrier ribs that divide a discharge space corresponding to the third electrode, and a discharge space that is divided by the vertical barrier ribs. Is a driving method of a plasma display panel sealed through a discharge space,

The plasma display panel is formed such that, among the at least three types of phosphor layers, the height of the vertical barrier ribs disposed between the two specific phosphor layers is lower than the other vertical barrier ribs,

In the case where address discharge is performed in a cell of a phosphor layer having a high emission luminance among the two specific types of phosphor layers, a cell of a phosphor layer having a low emission luminance among the two types of specific phosphor layers. A method for driving a plasma display panel, characterized in that address discharge is also performed.

[11] The two specific types of phosphor layers are a green phosphor layer and a blue phosphor layer, and when the address discharge is performed in the cells of the green phosphor layer, the blue phosphor layer 11. The method for driving a plasma display panel according to claim 10, wherein the cells of the phosphor layer are also caused to perform address discharge.

[12] Among the plurality of subfields having different gradations constituting one frame, when address discharge is performed in the cells of the green phosphor layer in the low gradation subfield, 12. The method for driving a plasma display panel according to claim 11, wherein the cells of the phosphor layer are also subjected to address discharge.