WO2008042144A3 - A semiconductor device comprising isolation trenches inducing different types of strain - Google Patents

A semiconductor device comprising isolation trenches inducing different types of strain Download PDF

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Publication number
WO2008042144A3
WO2008042144A3 PCT/US2007/020598 US2007020598W WO2008042144A3 WO 2008042144 A3 WO2008042144 A3 WO 2008042144A3 US 2007020598 W US2007020598 W US 2007020598W WO 2008042144 A3 WO2008042144 A3 WO 2008042144A3
Authority
WO
WIPO (PCT)
Prior art keywords
isolation trenches
different types
strain
semiconductor device
inducing different
Prior art date
Application number
PCT/US2007/020598
Other languages
French (fr)
Other versions
WO2008042144A2 (en
Inventor
Christoph Schwan
Joe Bloomquist
Peter Javorka
Manfred Horstmann
Sven Beyer
Markus Forsberg
Frank Wirbeleit
Karla Romero
Original Assignee
Advanced Micro Devices Inc
Christoph Schwan
Joe Bloomquist
Peter Javorka
Manfred Horstmann
Sven Beyer
Markus Forsberg
Frank Wirbeleit
Karla Romero
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE102006046377A external-priority patent/DE102006046377A1/en
Application filed by Advanced Micro Devices Inc, Christoph Schwan, Joe Bloomquist, Peter Javorka, Manfred Horstmann, Sven Beyer, Markus Forsberg, Frank Wirbeleit, Karla Romero filed Critical Advanced Micro Devices Inc
Priority to CN200780040260XA priority Critical patent/CN101536175B/en
Priority to GB0906452A priority patent/GB2456094A/en
Priority to JP2009530385A priority patent/JP2010505269A/en
Publication of WO2008042144A2 publication Critical patent/WO2008042144A2/en
Publication of WO2008042144A3 publication Critical patent/WO2008042144A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7846—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the lateral device isolation region, e.g. STI

Abstract

By forming isolation trenches (102 A, 102B) of different types of intrinsic stress on the basis of separate process sequences, the strain characteristics of adjacent active semiconductor regions (105A, 105B) may be adjusted so as to obtain overall device performance. For example, highly stressed dielectric fill material (107A, 107B) including compressive and tensile stress may be appropriately provided in the respective isolation trenches (102A, 102B) in order to correspondingly adapt the charge carrier mobility of respective channel regions (121 A, 121B).
PCT/US2007/020598 2006-09-29 2007-09-24 A semiconductor device comprising isolation trenches inducing different types of strain WO2008042144A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN200780040260XA CN101536175B (en) 2006-09-29 2007-09-24 A semiconductor device comprising isolation trenches inducing different types of strain
GB0906452A GB2456094A (en) 2006-09-29 2007-09-24 A semiconductor device comprising isolation trenches inducing different types of strain
JP2009530385A JP2010505269A (en) 2006-09-29 2007-09-24 Semiconductor device having isolation trenches that induce different types of strain

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE102006046377A DE102006046377A1 (en) 2006-09-29 2006-09-29 Semiconductor device e.g. integrated circuit, has active semiconductor regions with peripheries formed by isolation trenches with dielectric filling materials, respectively, where filling materials are comprised of silicon nitride
DE102006046377.3 2006-09-29
US11/734,320 2007-04-12
US11/734,320 US7547610B2 (en) 2006-09-29 2007-04-12 Method of making a semiconductor device comprising isolation trenches inducing different types of strain

Publications (2)

Publication Number Publication Date
WO2008042144A2 WO2008042144A2 (en) 2008-04-10
WO2008042144A3 true WO2008042144A3 (en) 2008-08-14

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/020598 WO2008042144A2 (en) 2006-09-29 2007-09-24 A semiconductor device comprising isolation trenches inducing different types of strain

Country Status (1)

Country Link
WO (1) WO2008042144A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150295033A1 (en) * 2012-11-30 2015-10-15 Ps5 Luxco S.A.R.L. Apparatus and method for manufacturing same

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1304734A2 (en) * 2001-10-17 2003-04-23 STMicroelectronics S.A. Isolating trench and method for making the same
US6657276B1 (en) * 2001-12-10 2003-12-02 Advanced Micro Devices, Inc. Shallow trench isolation (STI) region with high-K liner and method of formation
US20040063300A1 (en) * 2002-10-01 2004-04-01 Taiwan Semiconductor Manufacturing Company Shallow trench filled with two or more dielectrics for isolation and coupling or for stress control
US20040113174A1 (en) * 2002-12-12 2004-06-17 International Business Machines Corporation Isolation structures for imposing stress patterns
US20040212035A1 (en) * 2003-04-25 2004-10-28 Yee-Chia Yeo Strained-channel transistor and methods of manufacture
US20050260806A1 (en) * 2004-05-19 2005-11-24 Taiwan Semiconductor Manufacturing Co., Ltd. High performance strained channel mosfets by coupled stress effects
US20060060925A1 (en) * 2004-09-17 2006-03-23 International Business Machines Corporation Semiconductor device structure with active regions having different surface directions and methods
US20060091461A1 (en) * 2004-10-29 2006-05-04 Jian Chen Transistor structure with dual trench for optimized stress effect and method therefor

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1304734A2 (en) * 2001-10-17 2003-04-23 STMicroelectronics S.A. Isolating trench and method for making the same
US6657276B1 (en) * 2001-12-10 2003-12-02 Advanced Micro Devices, Inc. Shallow trench isolation (STI) region with high-K liner and method of formation
US20040063300A1 (en) * 2002-10-01 2004-04-01 Taiwan Semiconductor Manufacturing Company Shallow trench filled with two or more dielectrics for isolation and coupling or for stress control
US20040113174A1 (en) * 2002-12-12 2004-06-17 International Business Machines Corporation Isolation structures for imposing stress patterns
US20040212035A1 (en) * 2003-04-25 2004-10-28 Yee-Chia Yeo Strained-channel transistor and methods of manufacture
US20050260806A1 (en) * 2004-05-19 2005-11-24 Taiwan Semiconductor Manufacturing Co., Ltd. High performance strained channel mosfets by coupled stress effects
US20060060925A1 (en) * 2004-09-17 2006-03-23 International Business Machines Corporation Semiconductor device structure with active regions having different surface directions and methods
US20060091461A1 (en) * 2004-10-29 2006-05-04 Jian Chen Transistor structure with dual trench for optimized stress effect and method therefor

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
"Improving MOS performance by modulation of stresses using stressed isolation trench dielectric", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 41, no. 1, 1 January 1998 (1998-01-01), pages 487 - 490, XP000772183 *

Also Published As

Publication number Publication date
WO2008042144A2 (en) 2008-04-10

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