WO2008039098A1

WO2008039098A1 - A modified min-sum kernel for a low density parity check (ldpc) code decoder

Info

Publication number: WO2008039098A1
Application number: PCT/RU2006/000508
Authority: WO
Inventors: Andrey Gennad'evich Efimov; Andrey Vladimirovich Belogolovy; Aliaksei Vladimirovich Chapyzhenka
Original assignee: Intel Corporation
Priority date: 2006-09-29
Filing date: 2006-09-29
Publication date: 2008-04-03

Abstract

A decoder to convert the reliability values, in 2's complement form, to a sign-magnitude form based on a bit-wise logical negation operation and update the reliability values based on low density parity check code (LDPC) coding. The decoder converts the updated reliability values, in sign-magnitude form, to a 2's complement form based on a bit-wise logical negation operation. In one embodiment, the bit-wise logical negation operation may be performed using a multi-input X-OR logic gate.

Description

A MODIFIED MIN-SUM KERNEL FOR A LOW DENSITY PARITY CHECK

(LDPC) CODE DECODER

BACKGROUND

A communication environment generally refers to a group of interconnected wired and/or wireless devices such as, for example, laptops, mobile phones, servers, fax machines, printers, etc, which may send/receive data. The transmitting devices may often encode the information before transferring the encoded data over a communication medium provisioned between the devices. The transmitting devices may use low density parity check (LDPC) codes, turbo codes, and such other codes to encode the information.

The receiving devices may perform decoding, error detection and correction and such other operations to extract the information bits. The receiving device may comprise a decoder to perform decoding. The decoder may use LDPC codes to decode the received signal to extract the information. The decoding process may comprise iterative decoding, in which the decoder, iteratively, decodes until extracting the information or for a pre-specified number of iterations before requesting the transmitter to re-transmit. The iterative decoding process comprises receiving initial reliability values and then updating the reliability values in each iteration.

The decoder may comprise various kernels for performing sub-tasks of decoding. A min-sum kernel may perform a sub-task of updating reliability values. The min-sum kernel may comprise blocks such as logic gates, multiplexers, summers and such other blocks. It may be desirable to reduce the chip area occupied by kernels.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention described herein is illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements. FIG. 1 illustrates an embodiment of a communication system comprising a transceiver 100 and communication channel 150.

FIG. 2 illustrates an embodiment of a decoder 180 depicted in FIG. 1. FIG. 3 illustrates an embodiment of the decoder 180, which updates reliability values.

FIG. 4 illustrates an embodiment of a logic circuitry used in the decoder 180. FIG. 5 illustrates an embodiment of the system comprising a transceiver 100 of FIG.l.

DETAILED DESCRIPTION

The following description describes a modified Min-sum kernel for a low density parity check (LDPC) decoder. In the following description, numerous specific details such as logic implementations, resource partitioning/sharing/duplication implementations, types and interrelationships of system components, and logic partitioning/integration choices are set forth in order to provide a more thorough understanding of the present invention. It will be appreciated, however, by one skilled in the art that the invention may be practiced without such specific details. In other instances, control structures, gate level circuits, and full software instruction sequences have not been shown in detail in order not to obscure the invention. Those of ordinary skill in the art, with the included descriptions, will be able to implement appropriate functionality without undue experimentation.

References in the specification to "one embodiment", "an embodiment", "an example embodiment", etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

Embodiments of the invention may be implemented in hardware, firmware, software, or any combination thereof. Embodiments of the invention may also be implemented as instructions stored on a machine-readable medium, which may be read and executed by one or more processors. A machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computing device). For example, a machine-readable medium may include read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustical or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.), and others. Further, firmware, software, routines, instructions may be described herein as performing certain actions. However, it should be appreciated that such descriptions are merely for convenience and that such actions in fact result from computing devices, processors, controllers, or other devices executing the firmware, software, routines, instructions, etc.

An embodiment of a communication system is illustrated in FIG. 1. The communication system may comprise a transceiver 100 and a communication medium 150. The transceiver 100 may send and receive signals over the communication medium 150. In one embodiment, the transceiver 100 may transmit the signals, according to, for example, Ethernet standards, over the communication medium 150 at a rate of 10 gigabits per second (Gbps). In one embodiment, the transceiver 100 may implement, Ethernet 1OG, IEEE 802.1 In and IEEE 802.16e standards and such other similar standards that use LDPC codes for decoding. The communication medium 150 may represent a wired medium such as a co-axial cable, an optical fiber, and a wireless medium. The transceiver 100 may be used, for example, in network interface cards (NIC), physical layer devices (PHYs) and such other devices. In one embodiment, the transceiver 100 may comprise a transmitter 120 and a receiver 130. The transmitter 120 may generate a signal or a symbol or a codeword from a data bit stream and transmit the signal on the communication medium 150. In one embodiment, the transmitter 120 may process the data bit stream using techniques such as framing, scrambling, encoding, and mapping. In one embodiment, the transmitter 120 may encode the data bit stream using low density parity check (LDPC) codes. The transmitter 120 may modulate the signal using pulse amplitude modulation (PAM), binary phase shift keying (BPSK) and such other modulation techniques.

The receiver 130 may generate data bits from a received signal before sending the data bits for further processing, for example, to a switch, router, or any device configured to receive data bits. In one embodiment, the receiver 130 may process the code-words using techniques such as demodulation and decoding. In one embodiment, the receiver 130 may use LDPC codes and iterative decoding techniques to decode the code- words.

An embodiment of the receiver 130 may comprise a demodulator 140 and a decoder 180. In one embodiment, the demodulator 140 may extract the information signal from the modulated signal. In one embodiment, the demodulator 140 may generate soft decision values based on the received symbols or code-words and provide the soft decision values to the decoder 180. In one embodiment, the soft decisions may represent a likelihood that a bit may represent a one or zero. The soft decision values may be used to determine the value of the bit from the received codeword. In one embodiment, the demodulator 140 may use information relating to the confidence of the received codeword and the properties, such as a signal-to-noise ratio (SNR), of the communication medium 150 to generate the soft decision values. In one embodiment, the decoder 180 may generate data bits by decoding the code- words based on, for example, a belief propagation, a Min-sum, a multi-threshold, or a turbo-decoding message-passing (TDMP) decision scheme. The decoder 180 may perform iterative decoding based on the LDPC codes. In one embodiment, the decoder 180 may perform iterative decoding until a desired data bit stream is generated from the codeword or until a number of iterations equaling Iog2 (n) is complete, where n is the length of the codeword.

In one embodiment, the decoder 180 may generate initial reliability values (Ri) and initial hard decision values (Xi) based on the soft decision values. The decoder 180 may decode the code-words using a LDPC parity check matrix (H) and the initial reliability values (Ri). The decoder 180 may iteratively compute parity check values starting from the initial values of Ri and may generate a new hard decision vector Xnew. The decoder 180 may terminate the iterations if the new hard decision vector Xnew represents the desired data bit stream or the decoder 180 may perform predetermined number of iterations before requesting for a re-transmission. An embodiment of the decoder 180 is illustrated in Fig. 2. In one embodiment, the decoder 180 may comprise an input/output interface 210, a conversion unit 220, a memory 250, and an update unit 290.

The input/output interface 210 may receive input values such as the code- word, soft decisions and such other values from the demodulator 180 and pass the values to the variable nodes 230 after processing. The input/output interface 210 may also receive the data bits or output hard decision values from the variable nodes 230 and pass the data bits for further processing, for example, to a switch, router, or any device configured to receive the data bits. The input/output interface 210 may provide physical, electrical, and protocol interfaces to transfer data units between the decoder 130 and the other blocks such as the demodulator 140 or any other device coupled to the decoder 180.

The memory 250 may store one or more code-words, initial reliability values, updated reliability values that may be used by the VNUs 230 and CNUs 280 to decode the code-words to extract the data bits. In one embodiment, the memory 280 may comprise a dynamic random access memory (DRAM) and a static random access memory (SRAM).

The update unit 290 may comprise variable node update units (VNU) 230-A to 230-G and check nodes update units (CNU) 280-A to 280-E. hi one embodiment, the

VNUs 230-A to 230-G and CNUs 280-A to 280-E together may decode a code-word based on the LDPC decoding. In one embodiment, the VNUs 230-A to 230-G may be coupled to CNUs 230-A to 230-E based on the position of 'ones' in parity check matrix

H 200. For example, the (7, 5) parity check matrix H 200 is shown comprising five rows and seven columns. The decoder 180, thus, comprises five CNUs 280-A to 280-E and seven VNUs 230-A to 230-G.

As the first row of the parity matrix H 200 comprises a 'one' in first, third, fourth, fifth, and sixth column, the CNU 280-A is, accordingly, shown coupled to the

VNUs 230-A, 230-C, 230-D, 230-E, and 230-F, which correspond to the first, third, fourth, fifth, and the sixth column. Similarly, CNUs 280-B, 280-C, 280-D, and 280-E may be coupled to VNUs 230 (A, C, D, and F), 230 (A, B, C, and G), 230 (B, D, E, and

G), and 230 (B, E, F, and G) based on the second, third, fourth, and the fifth row the matrix H 200 respectively. In one embodiment, the decoder 180 may update the reliability values based on a Min-sum algorithm. A single iteration of the Min-sum algorithm is described as follows: For example, the CNU 280-A may receive reliability values (rl, r3, r4, r5, and r6) from the VNUs 230-A 230-C, 230-D, 230-E, and 230-F and may determine the minimum of reliability values minl l=min(r3, r4, r5, r6); minl3=min(rl, r4, r5, r6); minl4=min(rl, r3, r5, r6); minl5=min(rl, r3, r4, r6); and minl6=min(rl, r3, r4, r5). The CNU 280-A may then pass the minimum reliability values minl l, minl3, minl4, minl5, and minlό to the VNUs 230-A, 230-C, 230-D,

230-E, and 230-F respectively.

Like-wise, the CNU 280-B may determine the minimum reliability values min21, min23, min24, and min26 based on the reliability values (rl, r3, r4, and r6) received from the VNUs 230-A, 230-C, 230-D₅ and 230-F respectively. The CNU 280- C may determine the minimum reliability values min31, min32, min33, and min37 based on the reliability values (rl, r2, r3, and r7) received from the VNUs 230-A, 230- B, 230-C, and 230-G respectively. The CNU 280-D may determine the minimum reliability values min42, min44, min45, and min47 based on the reliability values (r2, i4, r5, and r7) received from the VNUs 230-B, 230-D, 230-E, and 230-G respectively. The CNU 280-E may determine the minimum reliability values min52, min55, min56, and min57 based on the reliability values (r2, r5, r6, and r7) received from the VNUs 230-B, 230-E, 230-F, and 230-G respectively. In one embodiment, the VNUs 230 may receive, from the negation operator 221, initial reliability values (Ri) in the sign-magnitude form. The VNUs 230 may then provide the reliability values to the CNUs 280 to which it is coupled with. In one embodiment, the VNUs 230 may receive minimum reliability values from the CNUs and may determine a sum of the minimum reliability values. For example, the VNU 230-A may determine a first updated reliability value as equaling a sum of the minimum reliability values minl l, min21, and min31 received from the CNUs 280- A, 280-B, and 280-C. Likewise, the VNU 230-B, through 230-G may determine an updated reliability value as equaling a sum of the minimum reliability values (min32, min42, and min52), (minl3, min23, and min33), (minl4, min24, and min44), (minl5, min45, and min55), (mini 6, min26, and min56), and (min37, min47, and min57) received from the CNUs coupled to the VNUs 230-B to 230-G respectively.

The conversion unit 220 may comprise bit-wise logic negation operators such as the X-OR gates. In one embodiment, the conversion unit 220 may comprise a first bitwise logic negation operator 221 and a second bit- wise logic negation operator 225. In one embodiment, the first bit-wise logic negation operator may receive a 'K' bit initial reliability value, which is in 2's complement form. The first bit- wise logic negation operator may generate a first value comprising (K-I) magnitude bits and a sign bit. The first value may be provided to the update unit 290.

Also, the second bit- wise logic negation operator may comprise an (K-I) bit X- OR logic gate, which may receive a (K-I) bit first updated reliability value. In one embodiment, the second bit- wise logic negation operator 225 may convert the (K-I) bit first updated reliability value into a second value, which may be in 2's complement form. As the logic negation operators 221 and 225 may comprise a multi-input X-OR gates the chip silicon area or the real estate of the integrated chip may be reduced. Such an approach may reduce the cost and power consumption.

An embodiment of the decoder 180 updating the reliability values based on the modified Min-sum algorithm is illustrated in Fig. 3. In block 310, the decoder 180 may generate an initial reliabilities vector (Ri) based on the soft decision values.

At initialization, for every element, Yi, of the received signal, the decoder 180 may generate reliability values Ri and initial hard decision values Xi based on the soft decision values. In one embodiment, the decoder 180 may set the reliability values Ri to the absolute value of Yi and the hard decision value Xi to one if Yi is greater than zero, and to zero otherwise. For example, the decoder 180 may generate a Xi = 0 and Ri = 2.48, if the value of Yi equals -2.48.

In block 330, the decoder 180 may convert each reliability value Ri, which is in the 2' s complement form, to a sign-magnitude form based on logical bit- wise negation operation. In one embodiment, for each 'n' belonging to N(m), the decoder 180 may, from the reliability value '"" , determine the sign portion ""' as depicted in Equation (1) and the magnitude portion ^m" as depicted in Equation (2) based on the logical bit-wise negation operation.

C C m^» = sign ( "'" ) Equation ( 1 )

n wherein N(m) represents a set of bits that belong to m-th parity check, ^m" represents the input reliability of n-th bit in m-th parity check, ""' is the sign of

Rmn, '""represents the magnitude of ""', and ""' represents a bit-wise negation n operation performed on '"" .

In block 350, the decoder 180 may update the sign and magnitude of the reliability value. In one embodiment, the VNUs 230 and CNUs 280, together, may p update the sign and magnitude of the reliability value "'" . The decoder 180 may update n the values of sign and magnitude of the reliability value '"" , respectively, as described above, which is based on the Equations (3) and (4) given below: - n 'e N π(m )\«{ n.} Equation (3)

M_mn = min M_mn, nw(mn^{») m}" Equation (4) wherein N(m)\n represents a set of bits belonging to m-th parity check except n-

th bit; ^mn represents the sign of the updated reliability value ^m" ; "'" represents the

D O magnitude of the updated reliability value "'" ; "'"' represents the sign of the reliability value determined from the minimum reliability values excluding the minimum reliability value, which corresponds to an index n, ^m"' represents the magnitude of the reliability value determined from the minimum reliability values computed excluding a minimum reliability value, which corresponds to index n. In block 380, the decoder 180 may convert each updated reliability value Rmn, which is in the sign-magnitude form, to a 2's complement form based on logical bitwise negation operation. In one embodiment, the decoder 180 may convert the sign- magnitude form of the updated reliability value in to the 2's complement form based on the Equation (5) shown below. = \

Equation (5)

D wherein ^m" represents the updated reliability value in 2's complement form;

and the operator " " represents a bit-wise negation operator.

In one embodiment, implementing the decoder 180 based on the bit- wise negation operation may reduce the number of logic blocks used to update the reliability values. Such an approach may reduce the silicon area required to implement the modified Min-sum algorithm.

An embodiment of the logic blocks performing the min-sum kernel based on the modified Min-sum algorithm of Fig. 3 is illustrated in Fig. 4. As depicted in Fig. 4(a), a prior conversion block may comprise, at least, three logic elements: a (k-1) bit inverter 410, a (K-I) bit summator 430, and a (K-I) bit multiplexer 450 to convert the reliability values in 2's complement to sign-magnitude form while updating the reliability values.

Each reliability value may comprise K bits. For example, the reliability value, in 2's complement, may equal (1110 0101) and the (K-I) bit inverter 410 may generate (0001 1010) due to inversion. The output of the (K-I) bit summator 430 may generate 0001 1011.

In one embodiment, the logic negation block 221 of the conversion block 220 may be used to convert the reliability values in 2's complement form to the sign- magnitude form while updating the reliability values based on the modified Min-sum algorithm described in Fig. 3. In one embodiment, the logic negation block 221 may comprise a (K-I) bit X-OR gate 480, which may convert, as described in block 330 of Fig. 3, the reliability value in 2's complement form to sign-magnitude form by performing a logical negation operation. For example, the reliability value, in 2's complement form, 1110 0101 may be provided as input to the (K-I) bit X-OR gate 480. The (K-I) bit X-OR gate 480 may generate an output equaling 0001 1010. In one embodiment, the difference in the output generated by the logic diagram of Fig. 4(b) and Fig. 4(a) equals a least significant bit (LSB), which may be negligible. In one embodiment, the deviation in the bit error rate (BER) caused due to the difference in the output generated by the logic diagrams of Fig. 4(a) and (b) may be within the acceptable range. Also, the (K-I) bit X-OR gate 480 of the logic negation block 221 may convert the reliability value, in sign-magnitude form, to 2's complement form as described in block 380 of Fig. 3.

An embodiment of a network system 500 is illustrated in FIG. 5. The network system 500 may comprise a network device 510 and a network 550. The network device 510 may correspond to a router, laptop computer, desktop computer, a hand held device, network interface card or any such devices that may be coupled to the network 550.

The network 550 may comprise one or more intermediate devices such as switches and routers, which may receive, process, and send the packets to an appropriate intermediate device. The network 550 may enable network devices such as the network device 510 to transmit and/or receive data. The intermediate devices of the network 550 may be configured to support TCP/IP, ATM and any such communication protocols. The network 550 may be coupled to the network devices such as the network device 510 via communication medium that may transfer packets corresponding to technologies such as 1OG Ethernet.

The network device 510 may generate one or more packets and send the packets to other network devices coupled to the network 550. The network device 510 may receive packets from other network devices via the network 550. In one embodiment, the network device 510 may comprise a processor 512, memory 514, and a network interface 518. The processor 512 may cause the interface 518 to provide a voice, data, or video, to a user of the network device 510, in response to executing instructions and the memory 514 may store the instructions executed by the processor 512. The network interface 518 may comprise, for example, a network interface card embodying a transceiver such as transceiver 100.

In one embodiment, the transceiver 100 may communicate with the network 550 in accordance with the evolving 10GBase-T standard as defined by the IEEE 802.3an series of standards, however, other standards may be used as well. In some embodiments, the transceiver 100 may communicate with the network 550 using any type of medium such as but not limited to twisted pairs of copper wire, optic channels, wireless channels, power-line channels, acoustic/sonar channels, printed circuit board (PCB), backplanes, coaxial cable, or any other medium. For example, the communication medium 150 may be category 5, 6, 6a, or 7 network cabling and/or any other shielded or unshielded cabling.

The transceiver 100 may process the code- words or symbols representing data generated by applications such as an e-mail, voice, data, video or a file transfer application and received, for example, over a 10GbE (10giga-bit Ethernet) from the network 550. A receiver such as the receiver 130 of transceiver 100 may receive the code-words or symbols and decode the code-words to generate bit streams using techniques described above. The receiver 130 may send the data streams to user interfaces, which may convert the data streams into a corresponding signal.

Certain features of the invention have been described with reference to example embodiments. However, the description is not intended to be construed in a limiting sense. Various modifications of the example embodiments, as well as other embodiments of the invention, which are apparent to persons skilled in the art to which the invention pertains are deemed to lie within the spirit and scope of the invention.

Claims

WHAT IS CLAIMED IS:

1. A method of decoding comprising generating a first set of values, in sign-magnitude form, by converting a plurality of reliability values, in 2's complement form, based on logical bit-wise negation operation, generating a plurality of updated reliability values from the first set of values, and generating a second set of values, in 2's complement form, by converting the plurality of updated reliability values, in sign-magnitude form, based on logical bit- wise negation operation.

2. The method of claim 1 comprises generating a first value based on a first reliability value, wherein the first value equals a result of a bit-wise X-OR operation of the bits of the first reliability value and the most significant bit of the first reliability value, wherein the first set of values comprise the first value and the plurality of reliability values comprise the first reliability value.

3. The method of claim 1, wherein the first reliability value comprises K bits and the first value comprises (K-I) magnitude bits and a sign bit.

4. The method of claim 1 comprises generating the plurality of updated reliability values based on a low-density parity check coding.

5. The method of claim 1 comprises generating a second value from a first updated reliability value, wherein the first value equals a result of a bit-wise X-OR operation of the bits of the first updated reliability value and the most significant bit of the first updated reliability value, wherein the second set of values comprise the second value and the plurality of updated reliability values comprise the first updated reliability value.

6. A decoder comprising a conversion unit to generate a first set of values, in sign-magnitude form, by converting a plurality of reliability values, in 2's complement form, based on logical bitwise negation operation and to generate a second set of values, in 2's complement form, by converting the plurality of updated reliability values, in sign-magnitude form, based on logical bit-wise negation operation, and an update unit to generate a plurality of updated reliability values from the first set of values.

7. The decoder of claim 6, wherein the conversion unit generates a first value based on a first reliability value, wherein the first value equals a result of a bit- wise X- OR operation of the bits of the first reliability value and the most significant bit of the first reliability value, wherein the first set of values comprise the first value and the plurality of reliability values comprise the first reliability value.

8. The decoder of claim 6, wherein the first reliability value comprises K bits and the first value comprises (K-I) magnitude bits and a sign bit.

9. The decoder of claim 6, wherein the update unit generates the plurality of updated reliability values based on a low-density parity check coding.

10. The decoder of claim 6, wherein the conversion unit generates a second value from a first updated reliability value, wherein the first value equals a result of a bit-wise X-OR operation of the bits of the first updated reliability value and the most significant bit of the first updated reliability value, wherein the second set of values comprise the second value and the plurality of updated reliability values comprise the first updated reliability value.

11. A receiver comprising a demodulator to generate soft decisions based on a received signal, and a decoder to generate a plurality of initial reliability values, to generate a first set of values, in sign-magnitude form, by converting the plurality of initial reliability values, in 2's complement form; a plurality of updated reliability values from the first set of values; and a plurality of updated reliability values from the first set of values, and to generate a second set of values, in 2's complement form, by converting the plurality of updated reliability values, in sign-magnitude form, based on logical bit- wise negation operation.

12. The receiver of claim 11, wherein the decoder generates a first value based on a first reliability value, wherein the first value equals a result of a bit-wise X-OR operation of the bits of the first reliability value and the most significant bit of the first reliability value, wherein the first set of values comprise the first value and the plurality of reliability values comprise the first reliability value.

13. The receiver of claim 11, wherein the decoder generates the plurality of updated reliability values based on a low-density parity check coding.

14. The receiver of claim 11, wherein the decoder generates a second value from a first updated reliability value, wherein the first value equals a result of a bit- wise X- OR operation of the bits of the first updated reliability value and the most significant bit of the first updated reliability value, wherein the second set of values comprise the second value and the plurality of updated reliability values comprise the first updated reliability value.

15. A system comprising a transmitter, a network interface to receive code-words over a communication medium, a receiver to generate soft decisions based on the code-words, to generate a plurality of initial reliability values; a first set of values, in sign-magnitude form, by converting the plurality of initial reliability values, in 2's complement form; a plurality of updated reliability values from the first set of values, and a plurality of updated reliability values from the first set of values, and to generate a second set of values, in 2's complement form, by converting the plurality of updated reliability values, in sign- magnitude form, based on logical bit-wise negation operation.

16. The system of claim 15, wherein the receiver receives the one or more codewords at a rate of at least 10 giga bits per second in accordance with 10GBase-T standard.

17. The system of claim 15, the transmitter generates the one or more codewords by encoding a bit stream based on a low-density parity check codes, sends the code-words over the communication medium at a rate of at least 10 giga bits over the communication medium.

18. The system of claim 15 represents a network interface card.

19. The system of claim 15 the system further includes at least one of a computer, a switch, a router, a handheld, a cell phone, or a server.