WO2008035352A3 - A method and a storage device estimating a completion time for a storage operation - Google Patents

A method and a storage device estimating a completion time for a storage operation Download PDF

Info

Publication number
WO2008035352A3
WO2008035352A3 PCT/IL2007/001266 IL2007001266W WO2008035352A3 WO 2008035352 A3 WO2008035352 A3 WO 2008035352A3 IL 2007001266 W IL2007001266 W IL 2007001266W WO 2008035352 A3 WO2008035352 A3 WO 2008035352A3
Authority
WO
WIPO (PCT)
Prior art keywords
completion time
storage
storage device
storage operation
controller
Prior art date
Application number
PCT/IL2007/001266
Other languages
French (fr)
Other versions
WO2008035352A2 (en
Inventor
Nir Perry
Original Assignee
Sandisk Il Ltd
Nir Perry
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/781,260 external-priority patent/US7930507B2/en
Application filed by Sandisk Il Ltd, Nir Perry filed Critical Sandisk Il Ltd
Priority to KR1020097003242A priority Critical patent/KR101455085B1/en
Publication of WO2008035352A2 publication Critical patent/WO2008035352A2/en
Publication of WO2008035352A3 publication Critical patent/WO2008035352A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)
  • Retry When Errors Occur (AREA)

Abstract

A storage device or system provides to a host processor an estimation of a completion time of a storage operation. The completion time may be based on the duration of automatic storage operations, which are not administered by the host processor. The storage device includes a non-volatile memory and a controller. The storage system includes: a storage device having a non-volatile memory; and a controller module. The controller or controller module estimates the completion time of a storage operation and provides to the processor the estimated completion time before the storage operation completes.
PCT/IL2007/001266 2006-09-18 2007-10-23 A method and a storage device estimating a completion time for a storage operation WO2008035352A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020097003242A KR101455085B1 (en) 2006-09-18 2007-10-23 A method and a storage device estimating a completion time for a storage operation

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US82593006P 2006-09-18 2006-09-18
US60/825,930 2006-09-18
US11/781,259 2007-07-22
US11/781,260 US7930507B2 (en) 2006-09-18 2007-07-22 Method of providing to a processor an estimated completion time of a storage operation
US11/781,260 2007-07-22
US11/781,259 US8117415B2 (en) 2006-09-18 2007-07-22 Storage device estimating a completion time for a storage operation

Publications (2)

Publication Number Publication Date
WO2008035352A2 WO2008035352A2 (en) 2008-03-27
WO2008035352A3 true WO2008035352A3 (en) 2008-06-26

Family

ID=39200966

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IL2007/001266 WO2008035352A2 (en) 2006-09-18 2007-10-23 A method and a storage device estimating a completion time for a storage operation

Country Status (2)

Country Link
KR (1) KR101455085B1 (en)
WO (1) WO2008035352A2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8688893B2 (en) 2009-06-23 2014-04-01 Intel Mobile Communications GmbH Memory device and memory interface
US8406076B2 (en) * 2010-06-28 2013-03-26 Sandisk Technologies Inc. FRDY pull-up resistor activation
KR102291803B1 (en) * 2015-04-07 2021-08-24 삼성전자주식회사 Operation method of a nonvolatile memory system, and operation method of user system including the same
KR102547795B1 (en) * 2016-05-04 2023-06-27 에스케이하이닉스 주식회사 Data processing system and operating method of data processing system
KR102689927B1 (en) 2018-11-16 2024-07-31 에스케이하이닉스 주식회사 Memory system and operating method thereof
CN116882335B (en) * 2023-09-06 2023-12-22 上海芯存天下电子科技有限公司 Operation time simulation acquisition method and device, electronic equipment and storage medium

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0715261A1 (en) * 1994-11-29 1996-06-05 Compaq Computer Corporation Arbiter organization for serial bus transfers
US6415367B1 (en) * 1999-12-16 2002-07-02 Intel Corporation Apparatus for reducing asynchronous service latency in a time slot-based memory arbitration scheme
US20020152374A1 (en) * 2001-02-08 2002-10-17 International Business Machines Corporation Apparatus and method for dynamic load balancing of multiple cryptographic devices
US20030163478A1 (en) * 2002-02-27 2003-08-28 International Business Machines Corporation Apparatus and method for generating graphic presentation of estimated time of completion of a server request
WO2005006194A2 (en) * 2003-06-30 2005-01-20 Raytheon Company Efficient memory controller
WO2006035344A1 (en) * 2004-09-28 2006-04-06 Koninklijke Philips Electronics N.V. Data processing system and method for memory arbitration

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002278824A (en) * 2001-03-21 2002-09-27 Seiko Epson Corp Method and device for controlling access, printer system and storage medium storing computer, readable program

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0715261A1 (en) * 1994-11-29 1996-06-05 Compaq Computer Corporation Arbiter organization for serial bus transfers
US6415367B1 (en) * 1999-12-16 2002-07-02 Intel Corporation Apparatus for reducing asynchronous service latency in a time slot-based memory arbitration scheme
US20020152374A1 (en) * 2001-02-08 2002-10-17 International Business Machines Corporation Apparatus and method for dynamic load balancing of multiple cryptographic devices
US20030163478A1 (en) * 2002-02-27 2003-08-28 International Business Machines Corporation Apparatus and method for generating graphic presentation of estimated time of completion of a server request
WO2005006194A2 (en) * 2003-06-30 2005-01-20 Raytheon Company Efficient memory controller
WO2006035344A1 (en) * 2004-09-28 2006-04-06 Koninklijke Philips Electronics N.V. Data processing system and method for memory arbitration

Also Published As

Publication number Publication date
WO2008035352A2 (en) 2008-03-27
KR20100106199A (en) 2010-10-01
KR101455085B1 (en) 2014-10-27

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