WO2008030093A3 - Data processing circuit with a plurality of instruction modes - Google Patents

Data processing circuit with a plurality of instruction modes Download PDF

Info

Publication number
WO2008030093A3
WO2008030093A3 PCT/NL2007/050434 NL2007050434W WO2008030093A3 WO 2008030093 A3 WO2008030093 A3 WO 2008030093A3 NL 2007050434 W NL2007050434 W NL 2007050434W WO 2008030093 A3 WO2008030093 A3 WO 2008030093A3
Authority
WO
WIPO (PCT)
Prior art keywords
instruction
selection
mode
operations
instructions
Prior art date
Application number
PCT/NL2007/050434
Other languages
French (fr)
Other versions
WO2008030093A2 (en
Inventor
Jeroen Anton Johan Leijten
Rik-Jan Zwartenkot
Original Assignee
Silicon Hive Bv
Jeroen Anton Johan Leijten
Rik-Jan Zwartenkot
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP2009527311A priority Critical patent/JP5388851B2/en
Priority to US12/440,205 priority patent/US8145888B2/en
Priority to KR1020137015565A priority patent/KR101326414B1/en
Priority to KR1020137015566A priority patent/KR101398770B1/en
Priority to EP07808567A priority patent/EP2069912B1/en
Priority to AT07808567T priority patent/ATE466331T1/en
Application filed by Silicon Hive Bv, Jeroen Anton Johan Leijten, Rik-Jan Zwartenkot filed Critical Silicon Hive Bv
Priority to DE602007006215T priority patent/DE602007006215D1/en
Priority to KR1020137023899A priority patent/KR101419668B1/en
Priority to KR1020097006743A priority patent/KR101306354B1/en
Publication of WO2008030093A2 publication Critical patent/WO2008030093A2/en
Publication of WO2008030093A3 publication Critical patent/WO2008030093A3/en
Priority to US13/419,135 priority patent/US8838945B2/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/445—Exploiting fine grain parallelism, i.e. parallelism at instruction level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30054—Unconditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30138—Extension of register space, e.g. register cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/323—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for indirect branch instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3816—Instruction alignment, e.g. cache line crossing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
  • Devices For Executing Special Programs (AREA)
  • Communication Control (AREA)

Abstract

A data processing circuit has an execution circuit (18) with a plurality of functional units (20). An instruction decoder (17) is operable in a first and a second instruction mode. In the first instruction mode instructions have respective fields for controlling each of the functional units (20), and in the second instruction mode instructions control one functional unit. A mode control circuit (12) controls the selection of the instruction modes. In an embodiment, the instruction decoder uses time-stationary decoding of the selection of operations to be executed by the execution circuit (18) and the selection of destination registers from the set of registers (19). Mode switching is a more efficient way of reducing instruction time for time stationary processors than indicating functional units for which the instruction contains commands. When instructions are scheduled, constraints are preferably imposed on operations for which operation selection and destination register selection are included on different sides of an instruction mode change. Such operations are avoided in an embodiment. In another embodiment, selected operations are scheduled for which operation selection and destination register selection are included on different sides of an instruction mode change. When an instruction containing a jump is encountered, the mode control circuit sets the instruction mode for subsequent instructions in conformity with information provided by the execution of the jump command.
PCT/NL2007/050434 2006-09-06 2007-09-06 Data processing circuit with a plurality of instruction modes WO2008030093A2 (en)

Priority Applications (10)

Application Number Priority Date Filing Date Title
US12/440,205 US8145888B2 (en) 2006-09-06 2007-09-06 Data processing circuit with a plurality of instruction modes, method of operating such a data circuit and scheduling method for such a data circuit
KR1020137015565A KR101326414B1 (en) 2006-09-06 2007-09-06 Data processing circuit
KR1020137015566A KR101398770B1 (en) 2006-09-06 2007-09-06 Method of scheduling operations for a programmable data processing
EP07808567A EP2069912B1 (en) 2006-09-06 2007-09-06 Data processing circuit with a plurality of instruction modes, method of operating such a data circuit and scheduling method for such a data circuit
AT07808567T ATE466331T1 (en) 2006-09-06 2007-09-06 DATA PROCESSING CIRCUIT HAVING MULTIPLE TYPES OF INSTRUCTIONS, METHOD FOR OPERATION OF SUCH DATA CIRCUIT, AND SCHEDULING METHOD FOR SUCH DATA CIRCUIT
JP2009527311A JP5388851B2 (en) 2006-09-06 2007-09-06 Data processing circuit having multiple instruction modes, data circuit processing method, and data circuit scheduling method
DE602007006215T DE602007006215D1 (en) 2006-09-06 2007-09-06 DATA PROCESSING CIRCUIT WITH SEVERAL INSTRUCTION SWITCHING AND SCHEDULING METHOD FOR SUCH DATA SWITCHING
KR1020137023899A KR101419668B1 (en) 2006-09-06 2007-09-06 Data processing circuit and data processing method
KR1020097006743A KR101306354B1 (en) 2006-09-06 2007-09-06 Data processing circuit with a plurality of instruction modes
US13/419,135 US8838945B2 (en) 2006-09-06 2012-03-13 Data processing circuit with a plurality of instruction modes for processing time-stationary encoded instructions, and method of operating/scheduling such data circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP06120236.2 2006-09-06
EP06120236 2006-09-06

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US12/440,205 A-371-Of-International US8145888B2 (en) 2006-09-06 2007-09-06 Data processing circuit with a plurality of instruction modes, method of operating such a data circuit and scheduling method for such a data circuit
US13/419,135 Division US8838945B2 (en) 2006-09-06 2012-03-13 Data processing circuit with a plurality of instruction modes for processing time-stationary encoded instructions, and method of operating/scheduling such data circuit

Publications (2)

Publication Number Publication Date
WO2008030093A2 WO2008030093A2 (en) 2008-03-13
WO2008030093A3 true WO2008030093A3 (en) 2008-05-02

Family

ID=38535383

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/NL2007/050434 WO2008030093A2 (en) 2006-09-06 2007-09-06 Data processing circuit with a plurality of instruction modes

Country Status (7)

Country Link
US (2) US8145888B2 (en)
EP (1) EP2069912B1 (en)
JP (3) JP5388851B2 (en)
KR (4) KR101306354B1 (en)
AT (1) ATE466331T1 (en)
DE (1) DE602007006215D1 (en)
WO (1) WO2008030093A2 (en)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010096119A1 (en) * 2008-10-29 2010-08-26 Adapteva Incorporated Variable instruction width digital signal processor
US8832475B1 (en) * 2009-05-10 2014-09-09 Cypress Semiconductor Corporation Programmable power mode sequencer
GB2474666B (en) * 2009-10-21 2015-07-15 Advanced Risc Mach Ltd Hardware resource management within a data processing system
KR101647818B1 (en) * 2010-04-13 2016-08-12 삼성전자주식회사 Apparatus for routing data between multicore and method thereof
US20130061213A1 (en) * 2011-08-26 2013-03-07 Cognitive Electronics, Inc. Methods and systems for optimizing execution of a program in a parallel processing environment
US10055227B2 (en) 2012-02-07 2018-08-21 Qualcomm Incorporated Using the least significant bits of a called function's address to switch processor modes
US9477834B2 (en) 2012-02-08 2016-10-25 Arm Limited Maintaining secure data isolated from non-secure access when switching between domains
GB2501343A (en) * 2012-02-08 2013-10-23 Advanced Risc Mach Ltd Data processing apparatus and method using secure domain and less secure domain
US9213828B2 (en) 2012-02-08 2015-12-15 Arm Limited Data processing apparatus and method for protecting secure data and program code from non-secure access when switching between secure and less secure domains
US9116711B2 (en) 2012-02-08 2015-08-25 Arm Limited Exception handling in a data processing apparatus having a secure domain and a less secure domain
US10210349B2 (en) 2012-02-08 2019-02-19 Arm Limited Data processing apparatus and method using secure domain and less secure domain
KR102179385B1 (en) 2013-11-29 2020-11-16 삼성전자주식회사 Method and processor for implementing instruction and method and apparatus for encoding instruction and medium thereof
US20170185400A1 (en) 2015-12-23 2017-06-29 Intel Corporation Mode-specific endbranch for control flow termination
US9785800B2 (en) 2015-12-23 2017-10-10 Intel Corporation Non-tracked control transfers within control transfer enforcement
US10534610B2 (en) 2016-07-20 2020-01-14 International Business Machines Corporation PC-relative addressing and transmission
GB2553010B (en) * 2017-01-16 2019-03-06 Imagination Tech Ltd Efficient data selection for a processor
CN111209231B (en) * 2018-11-21 2021-05-11 上海寒武纪信息科技有限公司 Data processing method and device and related products
CN111079908B (en) * 2018-10-18 2024-02-13 上海寒武纪信息科技有限公司 Network-on-chip data processing method, storage medium, computer device and apparatus
WO2020078470A1 (en) 2018-10-18 2020-04-23 上海寒武纪信息科技有限公司 Network-on-chip data processing method and device
CN111210012B (en) * 2018-11-21 2022-12-09 上海寒武纪信息科技有限公司 Data processing method and device and related products
CN114020330B (en) * 2021-11-04 2023-11-03 苏州睿芯集成电路科技有限公司 Method for mode switching in RISC-V processor authentication, electronic device and storage medium
WO2024028565A1 (en) * 2022-08-05 2024-02-08 Arm Limited No-operation-compatible instruction
CN117714711B (en) * 2024-02-05 2024-04-30 北京象帝先计算技术有限公司 Decoding method, decoding system, electronic device and readable storage medium

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999014669A1 (en) * 1997-09-17 1999-03-25 Sony Electronics Inc. Digital signal processor with variable width instructions
EP1065586A2 (en) * 1999-06-29 2001-01-03 Kabushiki Kaisha Toshiba Computer system comprising a plurality of parallel processors
WO2002029562A2 (en) * 2000-10-05 2002-04-11 Koninklijke Philips Electronics N.V. Retargetable compiling system and method
US20020116436A1 (en) * 2001-02-20 2002-08-22 Siroyan Limited Context preservation

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2810068B2 (en) * 1988-11-11 1998-10-15 株式会社日立製作所 Processor system, computer system, and instruction processing method
US6401196B1 (en) * 1998-06-19 2002-06-04 Motorola, Inc. Data processor system having branch control and method thereof
WO2002042907A2 (en) * 2000-11-27 2002-05-30 Koninklijke Philips Electronics N.V. Data processing apparatus with multi-operand instructions
JP2002280415A (en) 2001-03-16 2002-09-27 Matsushita Electric Ind Co Ltd Semiconductor device
JP2005535974A (en) 2002-08-16 2005-11-24 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ Apparatus, method, and compiler for enabling variable length instruction processing in a very long instruction word processor
CN1816799A (en) 2003-04-16 2006-08-09 皇家飞利浦电子股份有限公司 Support for conditional operations in time-stationary processors

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999014669A1 (en) * 1997-09-17 1999-03-25 Sony Electronics Inc. Digital signal processor with variable width instructions
EP1065586A2 (en) * 1999-06-29 2001-01-03 Kabushiki Kaisha Toshiba Computer system comprising a plurality of parallel processors
WO2002029562A2 (en) * 2000-10-05 2002-04-11 Koninklijke Philips Electronics N.V. Retargetable compiling system and method
US20020116436A1 (en) * 2001-02-20 2002-08-22 Siroyan Limited Context preservation

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
LEE E A: "Programmable DSP Architectures: Part II", IEEE ACOUSTICS, SPEECH, AND SIGNAL PROCESSING MAGAZINE, IEEE INC. NEW YORK, US, vol. 6, no. 1, January 1989 (1989-01-01), pages 4 - 14, XP002979466 *

Also Published As

Publication number Publication date
JP2013218710A (en) 2013-10-24
JP5638108B2 (en) 2014-12-10
KR20130087568A (en) 2013-08-06
KR101419668B1 (en) 2014-07-15
JP5388851B2 (en) 2014-01-15
US8838945B2 (en) 2014-09-16
ATE466331T1 (en) 2010-05-15
WO2008030093A2 (en) 2008-03-13
US20120179894A1 (en) 2012-07-12
US8145888B2 (en) 2012-03-27
KR101326414B1 (en) 2013-11-11
KR101398770B1 (en) 2014-05-27
US20100185835A1 (en) 2010-07-22
KR20130109251A (en) 2013-10-07
EP2069912B1 (en) 2010-04-28
DE602007006215D1 (en) 2010-06-10
JP5638107B2 (en) 2014-12-10
KR20130087569A (en) 2013-08-06
KR101306354B1 (en) 2013-09-09
JP2010503107A (en) 2010-01-28
EP2069912A2 (en) 2009-06-17
JP2013218711A (en) 2013-10-24
KR20090092753A (en) 2009-09-01

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