WO2008027875A3 - Methods and systems for tiling video or still image data - Google Patents

Methods and systems for tiling video or still image data Download PDF

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Publication number
WO2008027875A3
WO2008027875A3 PCT/US2007/076969 US2007076969W WO2008027875A3 WO 2008027875 A3 WO2008027875 A3 WO 2008027875A3 US 2007076969 W US2007076969 W US 2007076969W WO 2008027875 A3 WO2008027875 A3 WO 2008027875A3
Authority
WO
WIPO (PCT)
Prior art keywords
systems
still image
image data
methods
dimensional
Prior art date
Application number
PCT/US2007/076969
Other languages
French (fr)
Other versions
WO2008027875A2 (en
Inventor
Pierre-Yves J Taloud
Franck Seigneret
Sylvain Dubois
Jean Pierre Noel
Original Assignee
Texas Instruments Inc
Pierre-Yves J Taloud
Franck Seigneret
Sylvain Dubois
Jean Pierre Noel
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/617,820 external-priority patent/US7737986B2/en
Application filed by Texas Instruments Inc, Pierre-Yves J Taloud, Franck Seigneret, Sylvain Dubois, Jean Pierre Noel filed Critical Texas Instruments Inc
Publication of WO2008027875A2 publication Critical patent/WO2008027875A2/en
Publication of WO2008027875A3 publication Critical patent/WO2008027875A3/en

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0207—Addressing or allocation; Relocation with multidimensional access, e.g. row/column, matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/122—Tiling
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/123—Frame memory handling using interleaving
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present disclosure describes methods and systems for tiling video or still image data. At least some preferred embodiments include a method for accessing data that includes partitioning a display of graphical data (250) into a plurality of two-dimensional tiles; mapping a two-dimensional tile of the plurality of two-dimensional tiles to a single memory row within a memory (120); and maintaining the graphical data for the two-dimensional tile in the single memory row.
PCT/US2007/076969 2006-08-29 2007-08-28 Methods and systems for tiling video or still image data WO2008027875A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
EP06291383 2006-08-29
EP06291383.5 2006-08-29
US11/617,820 2006-12-29
US11/617,820 US7737986B2 (en) 2006-08-29 2006-12-29 Methods and systems for tiling video or still image data

Publications (2)

Publication Number Publication Date
WO2008027875A2 WO2008027875A2 (en) 2008-03-06
WO2008027875A3 true WO2008027875A3 (en) 2008-07-17

Family

ID=39136778

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/076969 WO2008027875A2 (en) 2006-08-29 2007-08-28 Methods and systems for tiling video or still image data

Country Status (1)

Country Link
WO (1) WO2008027875A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2484736B (en) * 2010-10-22 2014-11-05 Displaylink Uk Ltd Image generation
US9165538B2 (en) 2013-03-13 2015-10-20 Displaylink (Uk) Limited Image generation

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5510857A (en) * 1993-04-27 1996-04-23 Array Microsystems, Inc. Motion estimation coprocessor
US6230235B1 (en) * 1996-08-08 2001-05-08 Apache Systems, Inc. Address lookup DRAM aging
US20030142102A1 (en) * 2002-01-30 2003-07-31 Emberling Brian D. Texture mapping performance by combining requests for image data
US20050041489A1 (en) * 1995-02-28 2005-02-24 Renesas Technology Corporation Data processing apparatus and shading apparatus

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5510857A (en) * 1993-04-27 1996-04-23 Array Microsystems, Inc. Motion estimation coprocessor
US20050041489A1 (en) * 1995-02-28 2005-02-24 Renesas Technology Corporation Data processing apparatus and shading apparatus
US6230235B1 (en) * 1996-08-08 2001-05-08 Apache Systems, Inc. Address lookup DRAM aging
US20030142102A1 (en) * 2002-01-30 2003-07-31 Emberling Brian D. Texture mapping performance by combining requests for image data

Also Published As

Publication number Publication date
WO2008027875A2 (en) 2008-03-06

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