WO2008025238A1 - Storage device with large capacity and method based on flash memory - Google Patents

Storage device with large capacity and method based on flash memory Download PDF

Info

Publication number
WO2008025238A1
WO2008025238A1 PCT/CN2007/002499 CN2007002499W WO2008025238A1 WO 2008025238 A1 WO2008025238 A1 WO 2008025238A1 CN 2007002499 W CN2007002499 W CN 2007002499W WO 2008025238 A1 WO2008025238 A1 WO 2008025238A1
Authority
WO
WIPO (PCT)
Prior art keywords
controller
flash memory
data
master
slave
Prior art date
Application number
PCT/CN2007/002499
Other languages
French (fr)
Chinese (zh)
Inventor
Qingyi Lin
Original Assignee
Fortune Spring Technology (Shenzhen) Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to CN 200610062172 priority Critical patent/CN100573435C/en
Priority to CN200610062172.7 priority
Application filed by Fortune Spring Technology (Shenzhen) Corporation filed Critical Fortune Spring Technology (Shenzhen) Corporation
Publication of WO2008025238A1 publication Critical patent/WO2008025238A1/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from or digital output to record carriers, e.g. RAID, emulated record carriers, networked record carriers
    • G06F3/0601Dedicated interfaces to storage systems
    • G06F3/0628Dedicated interfaces to storage systems making use of a particular technique
    • G06F3/0655Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0661Format or protocol conversion arrangements
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from or digital output to record carriers, e.g. RAID, emulated record carriers, networked record carriers
    • G06F3/0601Dedicated interfaces to storage systems
    • G06F3/0602Dedicated interfaces to storage systems specifically adapted to achieve a particular effect
    • G06F3/061Improving I/O performance
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from or digital output to record carriers, e.g. RAID, emulated record carriers, networked record carriers
    • G06F3/0601Dedicated interfaces to storage systems
    • G06F3/0668Dedicated interfaces to storage systems adopting a particular infrastructure
    • G06F3/0671In-line storage system
    • G06F3/0673Single storage device
    • G06F3/0679Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A storage device with large capacity based on flash memory, adopting master-slave structure, performing communication management with internal communication protocol, comprising external interface, multiple controllers, and semiconductor storage media. And a storing method with large capacity based on flash memory is also provided, including steps of: distributing data to be wrote by a master controller, and transmitting the data and command to each corresponding slave controller one by one according to an internal communication protocol; detecting whether the Ready/Busy signal of each slave controller is set free; when all the Ready/Busy signals corresponding to all the slave controllers are set free, performing next cycle of transmitting of data and command.

Description

A high capacity storage device and method Technical Field of the flash memory based on

The present invention belongs to the field of flash memory storage, more particularly to a mass storage device and method based on flash memory. Background technique·

Flash memory and traditional hard drives currently on the market mainstream data storage media. Wherein the flash memory main advantage is that power has a smaller volume, high shock resistance and good reliability and the like. USB storage disk on the market, MP3 player, PMP personal media players and memory cards are based on the vast majority of flash memory as a storage medium. Predictably, in the emphasis on light and small trend, flash memory applications will become increasingly popular.

Currently on the market flash memory specifications cover many types comprising SLC (Single level cell), MLC (multi level cell), and AG-NAND, these flash memory in addition to the difference in size, and the efficiency of reading and writing data mode there are also different. But at SLC. The flash memory is the highest efficiency and reliability in reading and writing, but its higher price. So now mostly use SLC flash memory for the mainstream, but with the prices of the product down, making the product supplier has to be done to compromise in other ways, and gradually the use of MLC manufacturers is also increasing. Flash MLC flash memory manufacturers for research and development is sparing no effort. Flash at twice the compound annual growth rate increasing.

Currently on the market to start a small part of the manufacturers to develop flash memory instead of traditional hard disk drives. The main value is its power and shock resistance is better than traditional hard drives. Currently traditional hard drive market share is still much higher than the flash memory hard drive, the main reason is the cost of early flash memory is too high, supply is unstable, slow transfer rate and low capacity problem. But with the manufacturing flash memory suppliers continue to invest to develop and increase production capacity, the use of more advanced technology, so that the capacity of the flash memory has constantly continued to increase, the price gradually rationalized, flash memory is no longer confined to small mobile storage device. Foresee in the next few years, flash memory hard drive will most likely replace the traditional hard drive data to be stored

1 Make sure that this is the mainstream media.

When the flash memory technology matures, various manufacturers began to think about how to use the flash memory on IA products. With the flash memory after a number of manufacturers such as Samsung, Toshiba and other plant expansion to increase capacity, all current mobile storage device products, the storage medium with the largest share of flash memory. However, flash memory access efficiency is generally not high, and there is the problem of limited capacity, not on a storage medium in large systems, in addition to their main reason resulting in the flash memory access speed, the entire flash memory access system design architecture is a major problem.

Currently flash memory hard drives architecture designed mostly in a single flash memory controller to control the flash memory, the system in this way can only be applied in a low number of flash memory. But faced with the urgent needs of the market for high-capacity and high number of flash memory storage devices is increasing, a single flash memory controller system, can only control a small number of flash memory is not enough. How can we control more of flash memory to achieve the traditional hard drive capacity, the problem of how to improve the load capacitance will reduce the operating frequency when the multi-flash memory access, in order to maintain a high operating frequency to achieve with traditional hard disk rather the speed of technological development of various manufacturers desperately wants.

In addition to capacity issues, access efficiency is also a key issue. Traditional hard drives, specifications have been developed to ULTRA 133, data bus bandwidth of 133 Mbytes per second can be achieved, far exceeding the access speed of the flash memory. So want to use flash memory instead of traditional hard drives, there are still some problems to be overcome.

Therefore, at this stage of flash memory hard drive technology still faces some limitations and problems included poor efficiency of data transmission capacity and so on.

Because flash memory hard drives currently on the market demand is not large Gen 4, specifically for this need to open a special IC functionality, it takes a lot of costs, is not economical cost. So if you can on the current capabilities of existing flash memory controller to be extended, and through external logic, so that it can meet the needs of flash memory hard drive, would be a good choice. SUMMARY Example embodiments of the present invention is to provide a device based on a mass storage flash memory of the prior art to solve the poor storage access speed, capacity expansion difficult problems.

Example embodiments of the present invention is achieved, based on the mass storage flash memory device, using the master - slave architecture, communication protocol managed through internal communication to enhance storage capacity and performance, including substituted for traditional hard drive external interface interface, a plurality of controllers, a semiconductor storage medium.

A further object of embodiments of the present invention is to provide a method of mass-storage-based flash memory, comprising the steps of: the master controller assigns data to be written, and an internal communication protocol Gen sequentially according to the data and command to the from each corresponding controller; checks each / Busy signal has been released from the Ready controller; when all corresponding Busy signal from the controller release Ready /, under a transmit data and commands.

Embodiment of the present invention can be applied to various large-capacity flash memory storage device, to achieve such as the current drive capacity, transmission speed, thus replacing the traditional hard object. Further according to the present invention only be extended to the current function of a conventional flash memory controller, for this requires no special development of specialized flash disk controller, thereby reducing development costs, shorten the development cycle. BRIEF DESCRIPTION

FIG 1 is a schematic diagram of the control pin embodiment of the present invention;

FIG 2 is a diagram of the basic architecture of the multiple flash memory system embodiment of the present invention;

FIG 3 is a schematic diagram of a frequency system according to the present invention;

FIG 4 is a flowchart of the present invention, the controller activates embodiment;

FIG 5 is a prior art flash memory control flowchart;

FIG 6 is a modified embodiment of the flash memory according to the present invention is a control flowchart;

FIG 7 is a flowchart of data write embodiment of the present invention;

FIG 8 is a flowchart illustrating a data reading embodiments of the present invention;

FIG 9 is a diagram embodiment of the present invention, a single controller in the signal diagram PCB layout; and

FIG 10 is a multiplex signal diagram of a load circuit multiple satellites flash memory embodiment of the present invention. The main components of Legend]

100: control pin of flash memory

101: master / slave pin patterns selected

102: frequency input pin

103: frequency output pin

104: signal input pin ICP

105: signal output pin ICP

200: External IDE / CF interface interface

201: internal bus system

202: internal communication using the internal communication protocol DETAILED DESCRIPTION

To make the objectives, technical solutions and advantages of the present invention will become more apparent hereinafter in conjunction with the accompanying drawings and embodiments of the present invention will be further described in detail. It should be understood that the specific embodiments described herein are only used for de-feng the present invention, not to limit the present invention.

Embodiment utilizes a plurality of flash memory controllers, the present invention uses master - slave control mode architecture to improve performance and capacity constraints.

In the plurality of controllers, the master and slave controllers have the same number and the pin definitions, logic inside the same. A user may utilize I / O pin, or set from the main controller. Internal communication protocol from the primary data is transmitted through Data-in and Data-Out. Which pin is defined as shown in FIG.

2, a controller of any external control signal and the operation of the multi protocol between the chip, that he is not a master controller. The main controller may even choose not to connect flash memory, but its main purpose is to external access upon receipt of the command, which is determined from a flash controller to access, and then through a specific ICP (Inter- Chip Protocol), will be responsible for accessing the command to access the flash memory from the controller, then the controller will access data from, and returned through the system data bus. This system data bus may be 8, 16 or 32. At system startup, the master controller needs to move data from system configuration information, create a table. The main controller needs to know the architecture of the system topology, and external flash memory where the data to be accessed which is controlled by a controller, and how the data sent to the controller. Through this way we can use the existing controller, easily upgrade the capacity of the system.

In order to more stars primary synchronization between the controller, the main controller responsible for providing a frequency from the controller, as shown in FIG. Is the frequency of the main oscillator of the controller from outside the system, the signal obtained via CLKJN. This PLL circuit after a frequency frequency-divided in the controller, and then via the other frequency after frequency CLK- OUT signal to all the slave controllers.

In addition, since the IDE interface and speed CF memory speed of more than flash memory, so we need some mechanism to accelerate. Speed ​​limit flash memory at each access flash memory need to check this flash memory of Ready / Busy is already released, at this time if the flash memory is still in the busy condition, Ready / Busy did not lay down, you can not do write their actions, this section requires a lot of time waiting. 5, when the writing of a data controller must be determined on a flash memory controller of a Ready / Busy signal when released, to write data to the controller from the second teeth. We adopt a number of teeth simultaneously access controller to reduce the performance impact of Ready / Busy, as shown in FIG. To write data to the main controller assumed when the flash memory controller, the host controller commands and data are sequentially transferred to the ICP from the controller, the controller writes data from the flash memory. After completion of the primary transfer from the controller will check each Ready flash memory corresponding to the / Busy signal if now been released. If they are released before the next data to be written and the command sequence is transmitted to the controller. The advantage of this approach is that each of the flash memory can save waiting Ready / Busy signal from the accumulated time of the controller.

The system starts the process shown in Figure 4, each controller checks itself patterns for I / O pin, if the level is high, the controller is set to indicate that the main controller, a control indicates otherwise It is set from the controller. If the controller is the master controller, to take into account the synchronization system must first decide the operating frequency, the operating frequency is a user set value. If the user wishes to have a better performance, the operating frequency may be set to a high value, but multiple pieces connected to the flash memory controller when friends, will face the problem of stability. Further, on the issue of stability shown in FIG. 9, when the control signal is normally output from the basic circuit board, the surface will appear in FIG π type. But the larger the load imposed on the circuit, such as the excessive number of electronic components, will be considered in addition to generating a high frequency or attenuation phenomena due to board layout, when the load is increasing, rendering the signal waveform in FIG. In FIG. 10, for example, when connecting multiple pieces in the flash memory controller circuit board because of the increased load controller, the output signal will have a great high frequency attenuation and phase shift, so the signal in FIG. presents wave. Thus, when this occurs all the controllers need to reduce the operating frequency to reduce high frequency attenuation and phase shift is generated. '

Then the master controller needs to know the topology of the system architecture, the data within the known range of any logical sector which a controller. Because the master and slave can have its own management, so we know the main logical sector data can not be determined from the placement of the controller (flash memory location) and how, what logic can only inform fans want from notification through ICP data area. After the topology is created, because the Lord Himself can choose whether or not to control the flash, if the flash is connected, the primary master and slave itself along with the two functions. At this time, some forms requires an initial master, such as the physical address correspondence table (Logical To Physical Translation Table) and the like. Finally only the IDE / CF interface initialization settings and waiting for remote IDE / CF commands, perform data access operation. If the controller is set to the slave mode, only some form of initialization operation, the master controller uses the command and wait for the inside of a communication protocol.

The write process shown in Figure 7, when the IDE / CF interface to want to write operation, the main controller receives this command IDE / CF Interface (LBA buffer), contains the logical sector written sector length area and the like. Main first sets the DMA buffer (if IDE / CF interface Ultra mode) position data and a data length, when the control system starts then established topology data architecture, the data confirm the need to use and a logical position of the write-once every ICP which is transmitted to the controller. Wait until the outside through the IDE / CF DMA data buffer filled (one sector is 512 bytes), then use this data inside the DMA, the data to the corresponding slave controller, the controller using its internal table, writing data to the flash memory to which it is attached.

When all are written from the controller, it checks whether the release of all controllers Ready / Busy signal from the release if you can have the next round of the write operation, until all the data is written to complete until.

The read process shown in Figure 8, when the IDE / CF interface to want to read operation, the main controller receives this command IDE / CF Interface (LBA buffer), contains a read command the logical sector address and sector length and the like. Main first sets the DMA buffer (if IDE / CF interface Ultra mode) position data and a data length, when the control system starts then the established framework topology data, a reading operation needs to know that the ICP in which the control logical location is to read data. Then a command and a logical sector position from the controller to all, after the main controller checks whether all the Ready Busy # controller have been placed. If said data from all of the controllers are to be read, the master controller uses the read data by the internal DMA controller is transmitted from the buffer into the system, then the system master controller buffer external DMA transfer data to the remote.

Wherein the signal in a single controller PCB layout view of FIG. 9, as shown in FIG. 10 is a multiplex signal loading circuit flash memory multiple satellites FIG.

Further, when the system controller is connected over a certain number of flash memory, because the noise phenomena some electronic components such as capacitors accumulation amount, generated at this time it is necessary to reduce the operating frequency of all controllers. Since the operating frequency for all controllers provided by the master controller, the master controller must have a set of circuit frequency can be set, a plurality of sets of frequency can be generated to meet the needs of a different number of flash memory, to achieve the best performance.

Further, the flash memory controller chip common market, after a certain number of flash control, because the load capacitance and PCB layout elements, a data bus connected to four to eight in the flash memory, able to maintain its operating frequency at relatively high rated range, but also to maintain the accuracy of the basic wave type, this amount exceeds the range, often by lowering the operating frequency must be to ensure the accuracy of the wave, so the use of a plurality of independent data bus access within a fixed number of flash memory, can reduce the complexity of the PCB layout to ensure the accuracy of the flash memory access, in order to maintain overall high capacity, high performance and stability.

The above are only preferred embodiments of the present invention but are not intended to limit the present invention, any modifications within the spirit and principle of the present invention, equivalent substitutions and improvements should be included in the protection of the present invention within range.

Claims

Rights request
1, a high capacity storage device is flash-based memory, comprising:
The device uses the master - slave architecture, communication protocol managed through internal communication to enhance storage capacity and performance, including substituted for traditional hard drive interface, the external interface, a plurality of controllers, a semiconductor storage medium.
2. The apparatus of claim 1, wherein the external interface interface IDE / CF interface interfaces.
3. The apparatus as claimed in claim 1, wherein the device is a SLC / MLC NAND-type flash memory, AGAND type flash memory, the NROM flash memory or a NOR type flash memory. ·
4. The apparatus as claimed in claim 1, wherein the controller comprises a master controller and at least one slave controller.
5. The apparatus as claimed in claim 4, wherein the master and slave controllers have the same number of pins and the definition of logic inside the same; shall contain the master and slave controllers to provide other control pin the semiconductor memory components; the master and slave controller provides the at least one I / O pin, the controller is set from the master or ^; from the primary controller also provides at least Data-in and Data-Out pin, internal communication protocol for data transfer from the primary; CLK-iN provides the primary and CLK- OUT pin for synchronous operation timing of the entire system from a plurality of controllers should be at least the controller.
6. The apparatus as claimed in claim 1, wherein the master controller further comprises a set of operating frequency setting circuit for generating a plurality of sets of frequency.
7. The apparatus as claimed in any one of claims 1 to 6 claims, wherein the device is a U-disk (including but not limited to USB Pendriver 1.1 / 2.0), PMP player, a memory card (including but not limited to SD / MMC / CF / Memory Stick / XD) and MP3 players
8. A method of mass storage flash memory-based, characterized in that, said method comprising the steps of:
Master controller allocates data to be written, and the communication protocol according to the internal sequence data and commands from the controller corresponding to the respective; 'checks each / Busy signal has been released from the Ready controller;
When all corresponding Busy signal from the controller release Ready /, under a transmit data and commands.
9. The method according to claim 8, characterized in that the method for the U disk (including but not limited to USB Pendriver 1.1 / 2.0), PMP player, a memory card (including but not limited to SD / MMC / CF / Memory Stick / XD) and MP3 players.
PCT/CN2007/002499 2006-08-18 2007-08-20 Storage device with large capacity and method based on flash memory WO2008025238A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN 200610062172 CN100573435C (en) 2006-08-18 2006-08-18 Large-volume storing apparatus based on flash memory body
CN200610062172.7 2006-08-18

Publications (1)

Publication Number Publication Date
WO2008025238A1 true WO2008025238A1 (en) 2008-03-06

Family

ID=37954345

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2007/002499 WO2008025238A1 (en) 2006-08-18 2007-08-20 Storage device with large capacity and method based on flash memory

Country Status (2)

Country Link
CN (1) CN100573435C (en)
WO (1) WO2008025238A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8205037B2 (en) 2009-04-08 2012-06-19 Google Inc. Data storage device capable of recognizing and controlling multiple types of memory chips operating at different voltages
US8239729B2 (en) 2009-04-08 2012-08-07 Google Inc. Data storage device with copy command
US10082957B2 (en) 2016-07-20 2018-09-25 Western Digital Technologies, Inc. Dual-ported PCI express-based storage cartridge including single-ported storage controllers

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8244937B2 (en) 2008-09-30 2012-08-14 Micron Technology, Inc. Solid state storage device controller with parallel operation mode
CN101546194B (en) 2009-05-07 2012-01-04 成都市华为赛门铁克科技有限公司 Interface device, interface control method and memory system

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000017726A2 (en) * 1998-09-18 2000-03-30 Computron Switchable master/slave memory controller
JP2003030045A (en) * 2001-07-16 2003-01-31 Hitachi Communication Technologies Ltd Storage device
JP2005293177A (en) * 2004-03-31 2005-10-20 Tdk Corp Memory controller and flash memory system

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1447242A (en) 2002-03-25 2003-10-08 太和科技股份有限公司 Control device suitable to quick flash memory card and its construction methods
CN1147933C (en) 2002-04-22 2004-04-28 信息产业部电子第15研究所 Process for producing high speed and high-capacity flash solid memory
CN100458745C (en) 2004-08-31 2009-02-04 深圳市朗科科技股份有限公司 Extended flash disk

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000017726A2 (en) * 1998-09-18 2000-03-30 Computron Switchable master/slave memory controller
JP2003030045A (en) * 2001-07-16 2003-01-31 Hitachi Communication Technologies Ltd Storage device
JP2005293177A (en) * 2004-03-31 2005-10-20 Tdk Corp Memory controller and flash memory system

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8205037B2 (en) 2009-04-08 2012-06-19 Google Inc. Data storage device capable of recognizing and controlling multiple types of memory chips operating at different voltages
US8239729B2 (en) 2009-04-08 2012-08-07 Google Inc. Data storage device with copy command
US8239724B2 (en) 2009-04-08 2012-08-07 Google Inc. Error correction for a data storage device
US8239713B2 (en) 2009-04-08 2012-08-07 Google Inc. Data storage device with bad block scan command
US8244962B2 (en) 2009-04-08 2012-08-14 Google Inc. Command processor for a data storage device
US8250271B2 (en) 2009-04-08 2012-08-21 Google Inc. Command and interrupt grouping for a data storage device
US8327220B2 (en) 2009-04-08 2012-12-04 Google Inc. Data storage device with verify on write command
US8380909B2 (en) 2009-04-08 2013-02-19 Google Inc. Multiple command queues having separate interrupts
US8433845B2 (en) 2009-04-08 2013-04-30 Google Inc. Data storage device which serializes memory device ready/busy signals
US8447918B2 (en) 2009-04-08 2013-05-21 Google Inc. Garbage collection for failure prediction and repartitioning
US8566508B2 (en) 2009-04-08 2013-10-22 Google Inc. RAID configuration in a flash memory data storage device
US8566507B2 (en) 2009-04-08 2013-10-22 Google Inc. Data storage device capable of recognizing and controlling multiple types of memory chips
US8578084B2 (en) 2009-04-08 2013-11-05 Google Inc. Data storage device having multiple removable memory boards
US8595572B2 (en) 2009-04-08 2013-11-26 Google Inc. Data storage device with metadata command
US8639871B2 (en) 2009-04-08 2014-01-28 Google Inc. Partitioning a flash memory data storage device
US9244842B2 (en) 2009-04-08 2016-01-26 Google Inc. Data storage device with copy command
US10082957B2 (en) 2016-07-20 2018-09-25 Western Digital Technologies, Inc. Dual-ported PCI express-based storage cartridge including single-ported storage controllers

Also Published As

Publication number Publication date
CN100573435C (en) 2009-12-23
CN1936817A (en) 2007-03-28

Similar Documents

Publication Publication Date Title
US6026465A (en) Flash memory including a mode register for indicating synchronous or asynchronous mode of operation
US6795899B2 (en) Memory system with burst length shorter than prefetch length
US8055833B2 (en) System and method for increasing capacity, performance, and flexibility of flash storage
US8266367B2 (en) Multi-level striping and truncation channel-equalization for flash-memory system
US5822251A (en) Expandable flash-memory mass-storage using shared buddy lines and intermediate flash-bus between device-specific buffers and flash-intelligent DMA controllers
US5410680A (en) Solid state memory device having serial input/output
US9390035B2 (en) Method and apparatus for supporting storage modules in standard memory and/or hybrid memory bus architectures
KR101274306B1 (en) Memory system controller
KR101557624B1 (en) A memory device for the hierarchical memory structure,
US20090193184A1 (en) Hybrid 2-Level Mapping Tables for Hybrid Block- and Page-Mode Flash-Memory System
KR100483643B1 (en) Memory device
ES2718463T3 (en) Hybrid memory device with a single interface
US7979614B1 (en) Flash memory/disk drive interface and method for same
US20030145141A1 (en) Universal serial bus flash memory integrated circuit device
US9454319B2 (en) Storage system data hardening
US7762818B2 (en) Multi-function module
US8335123B2 (en) Power management of memory systems
US8341332B2 (en) Multi-level controller with smart storage transfer manager for interleaving multiple single-chip flash memory devices
US7318117B2 (en) Managing flash memory including recycling obsolete sectors
US8510494B2 (en) USB 3.0 support in mobile platform with USB 2.0 interface
US8166221B2 (en) Low-power USB superspeed device with 8-bit payload and 9-bit frame NRZI encoding for replacing 8/10-bit encoding
US5920884A (en) Nonvolatile memory interface protocol which selects a memory device, transmits an address, deselects the device, subsequently reselects the device and accesses data
US9223507B1 (en) System, method and computer program product for fetching data between an execution of a plurality of threads
KR101507192B1 (en) Daisy-chain memory configuration and usage
CN102177549B (en) A composite memory having a bridging device for connecting discrete memory devices to a system

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07800720

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase in:

Ref country code: DE

NENP Non-entry into the national phase in:

Ref country code: RU

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: COMMUNICATION UNDER RULE 112(1) EPC, EPO FORM 1205A DATED 21/07/09

122 Ep: pct application non-entry in european phase

Ref document number: 07800720

Country of ref document: EP

Kind code of ref document: A1