WO2008023409A1

WO2008023409A1 - Method for manufacturing semiconductor device

Info

Publication number: WO2008023409A1
Application number: PCT/JP2006/316423
Authority: WO
Inventors: Katsuyoshi Matsuura
Original assignee: Fujitsu Microelectronics Limited
Priority date: 2006-08-22
Filing date: 2006-08-22
Publication date: 2008-02-28

Abstract

[PROBLEMS] To provide a method for manufacturing a semiconductor device which can prevent the deterioration of a capacitor dielectric film. [MEANS FOR SOLVING PROBLEMS] A method for manufacturing a semiconductor device comprising the steps of forming a base insulating film (11) above a silicon substrate (1), forming a capacitor (Q) provided with a lower electrode (23a), a capacitor dielectric film (24a) formed of a ferroelectric material, and an upper electrode (25a) on the base insulating film (11), forming a first capacitor protection insulating film (39) covering the capacitor (Q), forming an interlayer insulating film (40) on the first capacitor protection insulating film (39) by a plasma CVD method in which bias voltage is applied to the side of the silicon substrate (1), and annealing the interlayer insulating film (40) in an ozone- or oxygen-containing atmosphere.

Description

Specification

Manufacturing method of semiconductor device

Technical field

The present invention relates to a method for manufacturing a semiconductor device.

Background art

[0002] Flash memories and ferroelectric memories are known as nonvolatile memories that can store information even when the power is turned off.

Among these, the flash memory has a floating gate embedded in the gate insulating film of an insulated gate field effect transistor (IGFET), and information is stored by storing charges representing stored information in the floating gate. Remember. However, such a flash memory has a drawback in that it requires a tunnel current to flow through the gate insulating film when writing or erasing information, and a relatively high voltage is required.

[0004] On the other hand, the ferroelectric memory is also called FeRAM (Ferroelectric Random Access Memory), and stores information using the hysteresis characteristic of the ferroelectric film provided in the ferroelectric capacitor. The ferroelectric film generates polarization according to the voltage applied between the upper electrode and the lower electrode of the capacitor, and the spontaneous polarization remains even if the voltage is removed. When the polarity of the applied voltage is reversed, this spontaneous polarization is also reversed, and information is written to the ferroelectric film by making the direction of the spontaneous polarization correspond to “1” and “0”. FeARM has the advantage that the voltage required for writing is lower than in flash memory and that writing can be performed faster than in flash memory.

[0005] As the above ferroelectric film, PZT (Pb (Zr, Ti) 0

3), PZT materials such as La-doped PZT (PLZT),

Bi layer structure compounds such as SBT (SrBi Ta O) and SBTN (SrBi (Ta, Nb) O) are used.

2 2 9 2 2 9

The

However, these ferroelectric thin films are easily reduced by hydrogen in the process of forming an interlayer insulating film on the capacitor and the like, and the ferroelectric characteristics such as the residual polarization charge amount are likely to deteriorate. In order to prevent such deterioration of the ferroelectric film, it normally has a key functioning as a hydrogen barrier film. The capacitor is covered with a capacitor protection insulating film.

[0007] Conventionally, 0.35 m FeRAM designed with a minimum dimension of 0.35 μm uses an alumina (A1 0) film formed by sputtering as such a capacitor protective insulating film.

twenty three

Yes.

[0008] For example, Patent Document 1 discloses that an alumina film having a film density exceeding 2.7 gZcm ³ is formed so as to cover all the capacitors covered by a platter structure, thereby providing hydrogen or the like. It is described that the reducing gas is prevented from entering from the lateral direction of the capacitor and the reduction of the ferroelectric film is prevented. In this case, by adopting RF (Radio Frequency) sputtering using an alumina target, an amorphous alumina film with fewer particles can be formed. Further, since the gas is not contained in the film formation atmosphere, the ferroelectric film due to the film formation of the alumina film is not deteriorated.

[0009] As a method for forming the alumina film, there is a CVD method in addition to the sputtering method.

[0010] Since the CVD method provides better step coverage of the alumina film than the sputtering method, an alumina film having a sufficient thickness on the side surface of the capacitor even if the miniaturization advances and the interval between the capacitors becomes narrower. The lateral force of the capacitor can also effectively prevent hydrogen from entering.

[0011] Because of these characteristics, the alumina film formed by the CVD method is preferably formed as a capacitor protective insulating film in a stacked FeRAM that is advantageous for miniaturization of capacitors. In particular, in the next generation FeRAM, which has been further miniaturized compared to the current situation, for example, a 0.18 m stack type FeRAM designed with a minimum dimension of 0.18 m, the alumina film formed by the CVD method as described above. Is considered essential.

In the formation of an alumina film by the CVD method, trimethylaluminum [A1 (CH 3)] (TMA: Tri-Methyl Aluminum) is usually used as the organoaluminum compound, and water (H 0) is used as the oxidant.

3 3 2

) Is used.

FIG. 1 is a schematic diagram showing a mechanism for forming an alumina film by atomic layer deposition (ALD), which is a kind of CVD method.

[0014] As shown in FIG. 1, in film formation by ALD, A) first adsorbs H 0 so as to cover the entire surface of the substrate 200, and then B) evacuates excess H 0. Purge, and force C), TM A) is flown to react with the adsorbed OH groups to form Al 0 in the atomic layer, and D) extra TMA

twenty three

Is evacuated and purged. An alumina film is formed by repeating a series of cycles A) to D).

However, when water is used as the oxidizing agent in this way, hydrogen or moisture is adsorbed on the ferroelectric film or moisture remains on the alumina film when the alumina film is formed. In this case, the capacitor dielectric film may be reduced and deteriorated by moisture during heat treatment such as the recovery annealing of the capacitor.

In view of this point, in Patent Document 2, when an alumina film is formed by an ALD method as a capacitor protective insulating film of FeRAM, ozone (0

3) is used. According to this, since ozone is a hydrogen-free oxidant, it is possible to prevent hydrogen and moisture from adsorbing to the capacitor dielectric and moisture from remaining in the alumina film when the alumina film is formed.

[0017] Here, in Patent Document 1 and Patent Document 2 described above, an alumina film is formed along the surface of the capacitor. However, in order to more effectively prevent hydrogen and moisture from entering the capacitor. Preferably, an alumina film is also formed on the interlayer insulating film covering the capacitor.

For example, in Patent Document 3, an alumina film is formed as a capacitor protection insulating film on the planarized surface of an interlayer insulating film. Since the alumina film is formed on a flat surface, it does not require excellent coverage characteristics and can be formed by sputtering.

By the way, when FeRAM is further miniaturized, there is a possibility that “soot” is generated in the interlayer insulating film filling the space between the capacitors. When a large “soot” enters the capacitor width, the film thickness of the interlayer insulation film that holds the side of the capacitor decreases, and the “slow” partial force is applied to the interlayer insulation film when the upper and lower electrodes thermally expand. Cracks run and reduce the reliability of the metal wiring on the interlayer insulating film. Such a problem is prominent when the plasma CVD method using TEOS (TetraEthOxySilane: Si (OC H)) gas is adopted as a method for forming an interlayer insulating film.

2 5 4

It can be seen.

[0020] Therefore, in order to suppress the occurrence of such "soot", it has been studied to adopt an HDPCVD (High Density Plasma CVD) method as a method of forming an interlayer insulating film on the capacitor.

[0021] In the HDPCVD method, a reaction bias is applied by applying a large bias voltage to a semiconductor substrate. Sputtering and film-forming at the same time proceed, and the space between narrow capacitors can be filled with an interlayer insulating film while suppressing the generation of “soot”.

However, in this HDPCVD method, a reducing substance such as H + ions is attracted to the semiconductor substrate by the bias voltage, and the capacitor dielectric film may be deteriorated by the reducing substance.

[0023] Therefore, when an interlayer insulating film is formed by HDPCVD, it is preferable to form a dense alumina film having good coverage characteristics by the above-described ALD method as a capacitor protective insulating film that covers the surface of the capacitor. Better ,.

Patent Document 1: Japanese Patent Laid-Open No. 2001-44375

Patent Document 2: JP 2004-193280 A

Patent Document 3: Japanese Unexamined Patent Publication No. 2006-49795

Disclosure of the invention

An object of the present invention is to provide a method for manufacturing a semiconductor device capable of preventing deterioration of a capacitor dielectric film.

According to one aspect of the present invention, a step of forming a base insulating film above a semiconductor substrate, a lower electrode, a capacitor dielectric film made of a ferroelectric material on the base insulating film, and Forming a capacitor having an upper electrode; forming a first capacitor protective insulating film covering the capacitor; and plasma for applying a bias voltage to the semiconductor substrate side on the first capacitor protective insulating film A method of manufacturing a semiconductor device is provided, which includes a step of forming an interlayer insulating film by a CVD method and a step of annealing the interlayer insulating film in an atmosphere containing ozone or oxygen.

According to the present invention, the interlayer insulating film is formed by a plasma CVD method (HDPC VD method) in which a bias voltage is applied to the semiconductor substrate side. The interlayer insulating film formed in this way is excellent in embeddability, and can fill a narrow space between capacitors without generating “soot”, while water that can deteriorate the capacitor dielectric film. Contains a lot in the film.

Therefore, in the present invention, the interlayer dielectric film is annealed in an atmosphere containing ozone or oxygen, and the interlayer dielectric film is dehydrated, whereby the capacitor dielectric film is reduced by the moisture in the interlayer dielectric film. Prevent deterioration. [0028] By adding ozone to the annealing atmosphere in this manner, the oxidizing power of the atmosphere increases, so that the effect of dehydration can be expected even when the annealing substrate temperature is lowered, and the substrate temperature is increased. This can suppress the deterioration of the capacitor dielectric film.

[0029] The first capacitor protective insulating film formed so as to cover the capacitor functions to prevent a reducing substance such as hydrogen from entering the capacitor. If an alumina film is formed as the first capacitor protective insulating film by the ALD method with excellent coverage characteristics, a sufficient first capacitor protective insulating film should be formed on the side surface of the capacitor even if the semiconductor device is miniaturized. The lateral force can effectively prevent the reducing substance from entering the capacitor.

[0030] Furthermore, in the ALD method, by using hydrogen-free ozone as an oxidizing agent, it is possible to prevent the capacitor dielectric film from being deteriorated by hydrogen during the formation of the first capacitor protection insulating film.

In addition, the annealing for the interlayer insulating film described above is preferably performed after the step of planarizing the surface of the interlayer insulating film by a CMP (Chemical Mechanical Polishing) method. In this way, even if the moisture contained in the CMP slurry is absorbed by the interlayer insulating film, the moisture can be removed by sealing. Furthermore, since the volume of the interlayer insulating film is reduced by CMP, the amount of water degassed from the interlayer insulating film during annealing can be reduced, and the deterioration of the capacitor due to the moisture released from the interlayer insulating film is suppressed.禾 IJ points can be obtained.

[0032] Then, after the step of annealing the interlayer insulating film, a step of forming a second capacitor protective insulating film on the interlayer insulating film, a first capacitor protective insulating film on the upper electrode, an interlayer insulating film, Also, do the process of forming holes in the second capacitor protective insulating film.

In this case, the damage received by the capacitor dielectric film during the process is recovered by annealing the capacitor dielectric film in an oxygen-containing atmosphere after forming the above holes. Even if such a recovery annealing is performed, the interlayer insulating film is annealed for the purpose of dewatering as described above, and therefore the interlayer insulating film sandwiched between the first and second capacitor dielectric films. However, it does not become steamed due to moisture in the film. Therefore, the capacitor dielectric film deteriorates due to the moisture, or the second capacitor protective insulating film cracks. Can be prevented.

Brief Description of Drawings

FIG. 1 is a schematic diagram showing a mechanism for forming an alumina film by the ALD method.

[FIG. 2] FIGS. 2 (a) to 2 (c) are cross-sectional views (part 1) in the middle of the manufacture of the semiconductor device according to the embodiment of the present invention.

3 (a) and 3 (b) are cross-sectional views (part 2) of the semiconductor device according to the embodiment of the present invention in the middle of manufacture.

4 (a) and 4 (b) are cross-sectional views (part 3) of the semiconductor device according to the embodiment of the present invention in the middle of manufacture.

FIGS. 5 (a) and 5 (b) are cross-sectional views (part 4) of the semiconductor device according to the embodiment of the present invention during manufacture.

6 (a) and 6 (b) are cross-sectional views (part 5) in the middle of manufacturing the semiconductor device according to the embodiment of the present invention.

FIGS. 7A and 7B are cross-sectional views (part 6) of the semiconductor device according to the embodiment of the present invention in the middle of manufacture.

FIGS. 8A and 8B are cross-sectional views (part 7) of the semiconductor device according to the embodiment of the present invention in the middle of manufacture.

FIGS. 9 (a) and 9 (b) are cross-sectional views (part 8) of the semiconductor device according to the embodiment of the present invention in the middle of manufacture.

FIG. 10 is a sectional view (No. 9) in the middle of manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 11 is a configuration diagram of an HDPCVD apparatus used in the embodiment of the present invention.

[FIG. 12] FIG. 12 is a diagram (No. 1) showing a result of TDS analysis performed in order to investigate the dehydration effect of an acid silicon film by annealing in the embodiment of the present invention.

FIG. 13 is a diagram (No. 2) showing a result of TDS analysis performed for examining the effect of dehydration of an oxide silicon film by annealing in the embodiment of the present invention.

[FIG. 14] FIG. 14 shows the removal of an oxide silicon film by annealing in an embodiment of the present invention. It is the figure (the 3) which shows the result of the TDS analysis performed in order to investigate the water effect.

[FIG. 15] FIG. 15 was conducted in order to investigate how the water content of the acid silicon film formed by the HDPCVD method depends on the film formation temperature in the embodiment of the present invention. It is the figure (the 1) which shows the result of TDS analysis.

[FIG. 16] FIG. 16 was carried out in order to investigate how the moisture content of an acid silicon film formed by the HDPCVD method depends on the film formation temperature in the embodiment of the present invention. It is the figure which shows the result of TDS analysis (the 2).

BEST MODE FOR CARRYING OUT THE INVENTION

Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 to 10 are cross-sectional views in the middle of manufacturing the semiconductor device according to the embodiment of the present invention.

This semiconductor device is a stack type FeRAM advantageous for miniaturization, and is manufactured as follows.

[0038] First, steps required until a sectional structure shown in FIG.

[0039] First, a trench for STI (Shallow Trench Isolation) that defines an active region of a transistor is formed on the surface of an n-type or p-type silicon (semiconductor) substrate 1, and an insulating material such as silicon oxide is formed therein. The element isolation insulating film 2 is formed by embedding the film. The element isolation structure is not limited to STI, and the element isolation insulating film 2 may be formed by a LOCOS (Local Oxidation of Silicon) method.

[0040] Next, after p-type impurities are introduced into the active region of the silicon substrate 1 to form the p-well 3, the surface of the active region is thermally oxidized to form a thermal oxide film that becomes the gate insulating film 4 To do.

Subsequently, an amorphous or polycrystalline silicon film is formed on the entire upper surface of the silicon substrate 1, and these films are patterned by photolithography to form two gate electrodes 5.

[0042] On the p-well 3, the two gate electrodes 5 described above are arranged in parallel at a distance from each other, and these gate electrodes 5 constitute a part of the word line.

Next, n-type impurities are introduced into the silicon substrate 1 beside the gate electrode 5 by ion implantation using the gate electrode 5 as a mask to form first and second source / drain extensions 6a and 6b. Thereafter, an insulating film is formed on the entire upper surface of the silicon substrate 1, and the insulating film is etched back to form an insulating sidewall 7 next to the gate electrode 5. As the insulating film, for example, an oxide silicon film is formed by a CVD method.

Subsequently, n-type impurities are ion-implanted again into the silicon substrate 1 while using the insulating sidewalls 7 and the gate electrode 5 as a mask, so that the surface layer of the silicon substrate 1 on the side of the two gate electrodes 5 is obtained. Then, first and second source Z drain regions 8a and 8b spaced apart from each other are formed.

Through the above steps, the active region of the silicon substrate 1 includes the first and second MOS transistors configured by the gate insulating film 4, the gate electrode 5, and the first and second source / drain regions 8a 8b. TR TR is formed.

1 2

[0047] Next, after forming a refractory metal layer such as a cobalt layer on the entire upper surface of the silicon substrate 1 by sputtering, the refractory metal layer is heated to react with silicon. A melting point metal silicide layer 9 is formed. The refractory metal silicide layer 9 is also formed on the surface layer portion of the gate electrode 5, thereby reducing the resistance of the gate electrode 5.

[0048] Thereafter, the unreacted refractory metal layer on the element isolation insulating film 2 or the like is removed by wet etching.

Subsequently, a silicon nitride (SiN) film is formed to a thickness of about 200 on the entire upper surface of the silicon substrate 1 by plasma CVD, and this is used as the cover insulating film 10. Next, an acidic silicon film is formed on the cover insulating film 10 as a base insulating film 11 with a thickness of about 100 nm by a plasma CVD method using TEOS gas.

Next, the upper surface of the base insulating film 11 is polished and planarized by a CMP (Chemical Mechanical Polishing) method. As a result of this CMP, the thickness of the base insulating film 11 is about 700 nm on the flat surface of the silicon substrate 1.

Then, the cover insulating film 10 and the base insulating film 11 are patterned by photolithography to form contact holes on the first and second source / drain regions 8a 8b. Further, after forming a glue film (adhesion film) and a tungsten film in this contact hole in order, the excess glue film and tungsten film on the underlying insulating film 11 are polished and removed by CMP, and these are removed. The first and second conductive plugs 12a and 12b are left only in the contact holes. [0052] These first and second conductive plugs 12a and 12b are electrically connected to the first and second source / drain regions 8a and 8b, respectively.

[0053] The glue film is formed by forming a titanium film having a thickness of about 30 nm and a titanium nitride film having a thickness of about 50 nm in this order.

Next, as shown in FIG. 2B, a titanium film is formed to a thickness of about 20 by sputtering on each of the base insulating film 11 and the first and second conductive plugs 12a and 12b. The titanium film 20 η m is used as the base conductive film 21.

[0055] Since titanium constituting the underlying conductive film 21 has self-orientation, the crystallinity of the underlying conductive film 21 is good.

[0056] Subsequently, as shown in FIG. 2 (c), the substrate temperature is set at 650 ° C in a nitrogen atmosphere for the purpose of easily oxidizing and improving the acid resistance of the underlying conductive film 21 made of titanium. Then, RTA (Rapid Thermal Anneal) with a processing time of 120 seconds is performed on the base conductive film 21 to nitride the base conductive film 21. The flow rate of nitrogen in this RTA is not particularly limited, but in this embodiment it is 10 slm (standard litter I min). Here, the unit slm represents a flow rate in a standard state (1.013 × 10 5 Pa, 0 ° C.).

Since the crystallinity of the base conductive film 21 before nitriding is good, the base conductive film 21 after nitriding in this way has a good crystallinity and is a film formed later on the base conductive film 21 It will function as a crystallinity improving film that improves the crystallinity of the film.

Next, steps required until a sectional structure shown in FIG.

First, a titanium aluminum nitride (TiAIN) film is formed as a conductive oxygen noria film 22 on the base conductive film 21 by a reactive sputtering method to a thickness of about lOOnm.

[0060] The conductive oxygen nore film 22 made of titanium aluminum nitride has an excellent oxygen permeation preventing function, and the first and second conductive plugs 12a and 12b below the surface are oxidized to cause contact failure. Play a role in preventing life.

Next, an iridium film is formed as a first conductive film 23 on the conductive oxygen noria film 22 by a sputtering method to a thickness of about lOOnm.

[0062] Then, the first PZT film and the second PZT film are respectively formed on the first conductive film 23 by MOCVD (Metal Organic CVD) with a substrate temperature of 620 ° C and a pressure of 5 Torr. Thickness 5nm, These PZT films are formed as a ferroelectric film 24 having a total film thickness of 120 nm.

[0063] The first and second PZT films have the same composition. However, since the crystallinity of the PZT film becomes better when the film is formed at a low oxygen partial pressure, the first layer should be formed with the oxygen partial pressure in the film formation atmosphere lower than that of the second layer. To improve the crystallinity. However, if the second layer is deposited at a low oxygen partial pressure, the leakage current increases due to the increase in oxygen vacancies in the PZT film. Therefore, priority is given to reducing the leakage current for the second layer, giving higher oxygen than the first layer. Film is formed with partial pressure.

[0064] In this MOCVD method, Pb (DPM) (chemical formula Pb (C H 0))), Zr (dmhd) (chemical formula Z

2 11 19 2 2 4 r (C H O)) and Ti (0—iOr) (DPM) (chemical formula Ti (C H O) (C H O))

9 15 2 4 2 2 3 7 2 11 19 2 2

Dissolved in THF (Tetra Hydro Furan: C H 2 O) solvent are Pb, Zr and Ti, respectively.

4 8

Used as a raw material.

Subsequently, an iridium oxide film having a thickness of about 150 is formed on the ferroelectric film 24 by sputtering, and this iridium oxide film is used as the second conductive film 25.

[0066] Then, in order to improve conductivity, which is often insufficient only with the second conductive film 25, the second conductive film

An iridium film as a conductivity enhancement film 26 is formed on the film 25 by sputtering to a thickness of about 50 mm.

Next, as shown in FIG. 3 (b), a titanium nitride film having a thickness of about 200 ηm is formed on the conductivity improving film 26 by sputtering, and the titanium nitride film is used as the first mask material layer. 27. Further, an oxide silicon film is formed as a second mask material layer 28 on the first mask material layer 27 to a thickness of about 700 using a plasma CVD method using TEOS gas.

Next, as shown in FIG. 4 (a), the second hard mask 28a is formed by patterning the second mask material layer 28 in an island shape.

[0069] Next, steps required until a sectional structure shown in FIG.

[0070] First, the first hard mask 27a is formed by etching the first mask material layer 27 using the second hard mask 28a as a mask.

Next, dry etching is performed on the films 23 to 26 in regions not covered with the first and second hard masks 27a and 28a. Thus, the upper electrode 25a composed of the conductivity improving film 26 and the second conductive film 25 is formed, and the ferroelectric film 24 is used as the capacitor dielectric film 24a. More The first conductive film 23 remains only under the capacitor dielectric film 24a.

[0072] The dry etching gas is not particularly limited, but a mixed gas of HBr and oxygen is used as an etching gas for the first conductive film 23, the second conductive film 25, and the conductivity improving film 26. . On the other hand, as an etching gas for the ferroelectric film 24, a mixed gas of chlorine and argon is used.

[0073] In addition, since the conductive oxygen barrier film 22 has an etching resistance to the etching gas for the first conductive film 23, a conductive oxygen barrier is formed on the entire surface of the base conductive film 21 even after the etching is completed. The membrane 22 remains.

[0074] Subsequently, as shown in FIG. 5A, the second hard mask 28a is removed by dry etching.

Next, steps required until a sectional structure shown in FIG.

First, while using the first hard mask 27a (see FIG. 5 (a)) as a mask, the underlying conductive film 2

Etch 1 and the conductive oxygen noble film 22 to leave these films only under the capacitor dielectric film 24a. This etching is performed by dry etching, and as the etching gas, for example, a mixed gas of argon and chlorine is used.

[0077] Further, since the first hard mask 27a is also etched by this etching gas, the first hard mask 27a is removed at the end of etching.

Thus, under the capacitor dielectric film 24a, the lower electrode 23a composed of the base conductive film 21, the conductive oxygen barrier film 22, and the first conductive film 23 is connected to the first conductive plug 12a. It is formed to be electrically connected. And this lower electrode 23a, capacitor dielectric film

Capacitor Q is constituted by 24a and upper electrode 25a.

[0079] As described above, in the stack type FeRAM, the hard mask 27a common to the lower electrode 23a, the capacitor dielectric film 24a, and the upper electrode 25a is used as an etching mask. There is no. Therefore, the capacitor Q can be miniaturized and high integration of FeRAM can be achieved.

Next, as shown in FIG. 6A, an alumina film covering the capacitor Q is formed to a thickness of about 40 nm, and the alumina film is used as the first capacitor protection insulating film 39.

[0081] Alumina constituting the first capacitor protective insulating film 39 is excellent in hydrogen permeation preventing ability. Therefore, external hydrogen is blocked by the first capacitor protection insulating film 39, and deterioration of the capacitor dielectric film 24a due to hydrogen can be prevented.

The method for forming the first capacitor protective insulating film 39 is not particularly limited. However, since the interval between the adjacent capacitors Q is narrow, it is preferable to form the first capacitor protection insulating film 39 by the ALD method capable of forming a film having excellent coverage characteristics. By adopting the ALD method in this way, the first capacitor protective insulating film 39 having a sufficient thickness can be formed on the side surface of the capacitor Q, and the lateral force is also easy to prevent hydrogen from entering the capacitor Q. Become.

[0083] When the ALD method is employed, trimethylaluminum is used as the organoaluminum compound. Hydrogen-free ozone is used as the oxidizing agent used with the organoaluminum compound. Compared with the case where water is used as the oxidizer, the amount of hydrogen in the atmosphere of ALD decreases when ozone is used, and the capacitor dielectric film 24a deteriorates due to hydrogen when the first capacitor protection insulating film 39 is formed. Can be suppressed.

Note that if good coverage characteristics are not required as described above, the first capacitor protective insulating film 39 may be formed by sputtering.

[0085] Next, steps required until a sectional structure shown in FIG.

FIG. 11 is a configuration diagram of an HDPCVD apparatus used in this process.

In the apparatus, a first high-frequency power source 104 is connected to a coil 103 provided above the chamber 100, and a second high-frequency power source 102 is further connected to the substrate platform 101. The coil 103 is wound in a plane parallel to the main surface of the silicon substrate 1, and the cross section is shown in the drawing.

[0088] By applying a high frequency power supply to the substrate mounting table 101 in this way, a bias voltage is applied to the silicon substrate 1, so that the plasmad reaction gas is drawn into the silicon substrate 1. In addition to those that contribute to film deposition, some of these reactive gases spatter the deposited film. By this sputtering action, film deposition and sputtering are simultaneously performed on the shoulder portion of the capacitor Q, thereby preventing the film from being thickly formed on the shoulder portion. As a result, the film thickness of the side surface of the capacitor Q is made uniform, and an insulating film with good embedding can be formed between the capacitors Q having a high aspect ratio. In this embodiment, in such an HDPCVD apparatus, a mixed gas of SiH, 0, and Ar is used.

4 2

Is used as a reaction gas, and film formation is performed under the following conditions.

• SiH flow ···, Osccm

Four

• 0 flow straight · · · 525sccm

2

Ar flow · ^ Osccm

15mTorr

• 1st high frequency power supply 64 frequency · '· 13. 56MHz

'1st high frequency power supply 64 parts 3500W

'Frequency of second high frequency power supply 62'

'Second high frequency power supply 62 2400W

• Deposition temperature (target temperature just above capacitor Q) · · '300 ° C

As a result, as shown in FIG. 6B, an oxide silicon film having a thickness that fills the space between the capacitors Q is formed on the first capacitor protection insulating film 39 as an interlayer insulating film 40. Since the interlayer insulating film 40 formed by HD PCVD has good embedding properties, even if the high integration progresses and the interval between the capacitors Q is narrowed, "s" is formed in the interlayer insulating film 40 between them. There is nothing to do.

[0090] Note that the deposition temperature of the interlayer insulating film 40 is not limited to the above 300 ° C, but 250 ° C or more 350

It must be below ° C! The significance of this temperature range will be described later.

Next, as shown in FIG. 7A, the upper surface of the interlayer insulating film 40 is polished and flattened by the CMP method. The film thickness of the interlayer insulating film 40 after CMP is about 300 nm on the upper electrode 25a.

By the way, according to the investigation conducted by the inventor of the present application, it has become clear that the interlayer insulating film 40 formed by the HDPCVD method contains a large amount of moisture. The survey results will be described later.

Also in the CMP described above, the moisture in the slurry permeates the interlayer insulating film 40 and the interlayer insulating film 40 contains a large amount of moisture.

As described above, if the interlayer insulating film 40 contains a large amount of moisture, even if the first capacitor protective insulating film 39 is formed, the capacitor dielectric film 24a may be deteriorated.

Therefore, in the present embodiment, as shown in FIG. 7B, in a mixed atmosphere of ozone and oxygen. Then, the interlayer insulating film 40 is annealed and the interlayer insulating film 40 is dehydrated.

The annealing conditions are not particularly limited! In this embodiment, however, a mixed gas of ozone and oxygen generated by an ozonizer (ozone generator) is supplied to a chamber (not shown) at a flow rate of lOslm. Ozone concentration in the mixture gas is 200gZNm ^3. Then, the annealing is performed for 30 minutes under a pressure of 0.133 kPa and a substrate temperature of 350 ° C. to 600 ° C., for example, 400 ° C.

Note that it is not preferable that the substrate temperature during annealing be higher than 600 ° C. because a dehydration reaction occurs remarkably in the interlayer insulating film 40 and a large amount of H 0 is generated.

2

Further, if the interlayer insulating film 40 once heated at the time of film formation is annealed at a substrate temperature lower than the film formation temperature, the dehydration effect due to the annealing cannot be expected. In this embodiment, since the deposition temperature of the interlayer insulating film 40 is 250 ° C. to 350 ° C., the interlayer insulating film 40 is effectively formed by setting the substrate temperature at the above annealing to 350 ° C. or higher. Can be dehydrated.

Furthermore, since this annealing is performed on the interlayer insulating film 40 whose volume has been reduced by CMP, the amount of moisture degassed from the interlayer insulating film 40 is reduced as compared with the case where it is performed before CMP. Therefore, it is possible to suppress the deterioration of the capacitor Q due to moisture from the interlayer insulating film 40.

[0100] Subsequently, as shown in FIG. 8 (a), a flat alumina film is formed on the interlayer insulating film 40 by sputtering to a thickness of about 50 mm, and the alumina film is formed as a second capacitor protective insulating film. The film 41 is used.

[0101] Since the second capacitor protection insulating film 41 is formed on the planarized second interlayer insulating film 40, excellent coverage characteristics are not required, and can be formed by an inexpensive sputtering method as described above. .

Here, the alumina constituting the second capacitor protective insulating film 41 is difficult to etch by a chemical reaction. Therefore, in order to facilitate the formation of holes in the second capacitor protective insulating film 41 in the etching process described later and to improve the hydrogen blocking performance, a dense and thin alumina film is used to form the second capacitor protective insulating film 41 using the ALD method. It is preferable to form as. In this case, the second capacitor protection insulating film 41 is formed as thin as about 30 °.

[0103] After that, a plasma using TEOS gas is formed on the second capacitor protective insulating film 41. A silicon oxide film is formed to a thickness of about 200 by CVD, and this silicon oxide film is used as a cap insulating film 42.

Subsequently, as shown in FIG. 8 (b), the first holes 40a are formed in these films on the upper electrode 25a by patterning each of the films 39-42.

[0105] Next, in order to recover the damage received by the capacitor dielectric film 24a in the steps so far, the silicon substrate 1 is placed in a furnace (not shown) and the substrate temperature is set to 500 ° C in an oxygen atmosphere. I do.

Here, since the first and second capacitor protective insulating films 39 and 41 are formed on the upper surface and the lower surface of the interlayer insulating film 40, respectively, the escape path of moisture in the interlayer insulating film 40 vaporized by this recovery annealing Is limited to the first hole 40a. Therefore, if the annealing process in FIG. 7B is omitted, a large amount of moisture in the interlayer insulating film 40 is vaporized during the recovery annealing, and the interlayer insulating film 40 and the capacitor Q below it are steamed by the vaporized moisture. As a result, the second capacitor protective insulating film 41 is cracked or the capacitor Q deteriorates.

On the other hand, in this embodiment, since the interlayer insulating film 40 is dehydrated in advance by the annealing process of FIG. 7B, the capacitor Q does not deteriorate even if the recovery annealing is performed! ,.

However, if the substrate temperature in the annealing process of FIG. 7B is too low, the interlayer insulating film 40 is insufficiently dehydrated, and the second capacitor protective insulating film 41 is cracked during this recovery annealing. There is a fear. If this is a concern, it is preferable to set the substrate temperature of the annealer in Fig. 7 (b) as high as possible, for example, 500 ° C! /.

Next, as shown in FIG. 9 (a), the second holes 40b are formed in these films on the second conductive plug 12b by patterning the films 39 to 42.

Incidentally, in the formation process of the second hole 40b (FIG. 9 (a)) and the formation process of the first hole 40a (FIG. 8 (b)), the second hole 40b made of alumina, which is difficult to chemically etch, is used. Capacitor protection Insulating film 41 is etched. Here, if the second capacitor protection insulating film 41 is thick, this etching becomes difficult, and it becomes difficult to process the holes 40a and 40b with high accuracy by the etching. Therefore, if this is a concern, as described above, the second capacitor protective insulating film 41 can be thinned to about 30 mm by the ALD method, which can form a dense film thinly. Preferably formed.

[0111] Next, steps required until a sectional structure shown in FIG.

[0112] First, a titanium nitride film is formed as a glue film on the cap insulating film 42 and in the first and second holes 40a, 40b by a sputtering method.

Further, a tungsten film is formed on the glue film by the CVD method, and the first and second holes 40a and 40b are completely filled with this tungsten film.

[0114] Then, unnecessary glue films and tungsten films on the cap insulating film 42 are polished and removed by CMP, and these films are removed only in the first and second holes 40a and 40b. Leave as conductive plugs 45a and 45b.

Of these plugs, the third conductive plug 45a is electrically connected to the upper electrode 25a of the capacitor Q.

On the other hand, the fourth conductive plug 45b is electrically connected to the second conductive plug 12b and constitutes a part of the bit line together with the second conductive plug 12b. By configuring the bit line with the two-stage conductive plugs 12b and 45b in this way, the aspect ratio of the holes embedded in the plugs 12b and 45b can be reduced, and each hole can be easily etched. It becomes possible to form. Such a two-stage plug contact structure is called a via-to-via contact.

Here, when the titanium nitride film constituting the glue film of the third conductive plug 45a touches the first conductive film 25 constituting the upper electrode 25a, the upper electrode 25a and the third conductive plug 45a There is a disadvantage that the contact resistance between the two becomes high. In view of this point, in this embodiment, since the conductivity improving film 26 made of iridium is formed on the uppermost layer of the upper electrode 25a, the contact resistance between the upper electrode 25a and the third conductive plug 45a is reduced. Can be lowered.

Then, as shown in FIG. 10, a metal multilayer film is formed on the cap insulating film 42 and each of the conductive plugs 45a and 45b by sputtering, and this metal multilayer film is patterned. Thus, the metal wiring 47a and the conductive pad 47b for the bit line are formed.

[0119] As the metal laminated film, a titanium film having a thickness of about 60, a titanium nitride film having a thickness of about 30, a copper-containing aluminum film having a thickness of about 400 nm, a titanium film having a thickness of about 5 nm, and a thickness of about A 70 nm titanium nitride film is formed in this order. [0120] Here, when the metal laminated film is patterned, the cap insulating film 42 functions as an etching stopper film, thereby preventing the thin second capacitor protective insulating film 41 from being etched and diminishing the hydrogen blocking effect. can do.

[0121] Further, when the metal wiring 47a is formed on the second capacitor protection insulating film 41 without the cap insulating film 42, it is caused by the difference in stress between the second capacitor protection insulating film 41 and the metal wiring 47a. As a result, stress migration may occur in the metal wiring 47a. On the other hand, if the metal wiring 47a is formed on the cap insulating film 42 made of silicon oxide as described above, such stress migration can be suppressed and the reliability of the metal wiring 47a can be improved. Can do.

As described above, the basic structure of the semiconductor device according to this embodiment is completed.

In the present embodiment described above, the interlayer insulating film 40 is formed by the HDPCVD method in the step of FIG. 6B, and the interlayer insulating film 40 is removed in the ozone-containing atmosphere in the step of FIG. 7B. Nealed.

[0124] In order to investigate the dehydration effect due to annealing in such an ozone-containing atmosphere, the inventor of the present application performed thermal desorption spectra (TDS) on various samples. .

The results are shown in FIG.

In FIG. 12, samples A and B are obtained by forming a silicon oxide film with a thickness of 50 Onm on a silicon wafer by a plasma CVD method using TEOS gas. The CVD method is not an HDP CVD method but a normal plasma CVD method.

[0127] Sample A and sample B have different film formation conditions. When sample A was formed as an interlayer insulating film 40, it was a condition that had cracked during the recovery annealing. Sample B is a condition that does not cause such cracks.

[0128] Sample C is a film in which a 500 nm thick silicon oxide film is formed on a silicon wafer by HDPCVD using the same film formation conditions as those of the interlayer insulating film 40 described above.

[0129] Sample D is obtained by annealing the same silicon oxide film as Sample C under the same conditions as in Fig. 7 (b).

[0130] Furthermore, Sample E was examined in the absence of a silicon wafer. Represents the background of

[0131] In this investigation, each sample A to D was obtained by cutting a silicon wafer into lcm x lcm squares for analysis.

[0132] Figure 12 shows only the spectrum with a mass number of 18 corresponding to H 0 in the TDS method.

2

Lot. The horizontal axis represents the temperature at TDS, and the vertical axis represents the ionic strength. However, the temperature on the horizontal axis indicates the stage temperature when the sampnore is installed, and does not represent the surface temperature of the sampnore.

[0133] First, focusing on Sample A and Sample B, which were formed by the usual plasma CVD method using TEOS gas, Sample A, which had been cracked during the recovery annealing in the past, had 250 It can be seen that there is a dehydration peak around ° C. This is presumed to be because H 2 O stored in the macropores in the silicon oxide film came out to the outside by heating,

2

This shows that the silicon oxide film of Sample A is a porous film.

[0134] On the other hand, in sample C employing the HDPCVD method under the same conditions as in the present embodiment, dehydration started around 250 ° C and increased toward the high temperature side without having a peak. The increase on the high temperature side is presumed to be because H 0 produced by the dehydration reaction between the OH groups of Si—OH bonds that existed in the silicon oxide film with little force has come out of the film. Is

2

The

[0135] Considering the difference from sample E, which shows the device package ground, sample C using HDPCVD is included in the film compared to samples A and B using normal plasma CVD. It can be seen that the amount of water produced is large.

From this result, it can be understood that in this embodiment in which a silicon oxide film formed by the HDPCVD method is adopted as the interlayer insulating film 40, the dehydration treatment for the interlayer insulating film 40 is essential.

[0137] Thus, in order to confirm the effect of the dehydration, when attention is paid to the dehydrated sample D, the dehydration amount from the sample D is drastically reduced at a stage temperature force of about S450 ° C.

FIG. 13 is a graph obtained by TDS analysis of samples A to E having the same structure as in FIG. 12, after leaving a silicon oxide film for one week.

[0139] Compared to Fig. 12, Sample A cracked during the recovery annealing was 250

Torn paper () It can be seen that the dehydration peaks at around ° C and around 350 ° C increased. This is presumed to be because H 0 was further occluded in the macropores in the silicon oxide silicon film by leaving it to stand.

2

[0140] On the other hand, in the case of Sample B without the above cracks, it is a dense film in which the dehydration peak does not increase even if left as it is. Therefore, the sample B silicon oxide film is suitable for the FeRAM interlayer insulation film, except that it has poor embedding characteristics.

[0141] On the other hand, in Sample C in which a silicon oxide film was formed by the HDPCVD method, dehydration per 350 ° C increased compared to FIG. This suggests that the silicon oxide film of sample C is a porous film, similar to sample B formed using TEOS gas.

[0142] In Sample D that was annealed in an ozone-containing atmosphere, no increase in dehydration was observed compared to FIG. From this, it can be seen that the acid-modified silicon film modified by annealing does not absorb moisture. Therefore, after the above annealing is performed on the interlayer insulating film 40 formed by the HDPCVD method, annealing for the purpose of dehydration is not performed in-situ before the formation of the second capacitor protective insulating film 41. However, the interlayer insulating film 40 can be used for FeRAM.

[0143] Next, a TDS analysis conducted by the present inventor in order to investigate the effect of annealing in an ozone-containing atmosphere will be described.

[0144] FIG. 14 is a graph showing the results of the TDS analysis.

In FIG. 14, samples A, D, and E are the same as those described in FIGS.

[0146] On the other hand, samples Dl and D2 were both subjected to annealing for dehydration on a silicon oxide film formed by the HDPCVD method. However, the annealing conditions are different between sample D1 and sample D2.

[0147] In sample D1, the substrate temperature was set to 500 ° C higher than that of sample D, and the silicon oxide film was annealed in an ozone-containing atmosphere. The gas flow rate, pressure, and processing time are the same as Sample D.

[0148] Sample D2 was obtained by annealing an oxide silicon film at a substrate temperature of 500 ° C in a 100% oxygen atmosphere. [0149] Sample Dl does not show a significant increase in the amount of dehydration on the high temperature side like Sample D. Dehydration on the high temperature side is caused by a dehydration reaction between OH groups of Si—OH bonds that exist in the silicon oxide film with little force. Therefore, it can be inferred from the above results that the Si—OH bonds in the film are reduced by raising the substrate temperature during annealing of the silicon oxide film.

[0150] In addition, the dehydration profile of Sample D1 showed the same profile as Sample A, which is suitable for FeRAM production, when the sample heating temperature was up to 600 ° C.

[0151] Here, in order to enhance the dehydration effect of the silicon oxide film, ozone having a higher acid power than oxygen is added to the annealing atmosphere for the silicon oxide film as in this embodiment. Seems to be preferred.

[0152] However, comparing sample D1 using ozone with sample D2 using oxygen, there is no significant difference between the profiles. This is presumably because, in sample D1, the substrate temperature during annealing was as high as 500 ° C, so ozone was killed during annealing of the silicon oxide film.

[0153] However, if annealing is performed at a substrate temperature lower than 500 ° C, ozone that is dead and active is reduced in the annealing atmosphere, and the dehydration effect of the acid silicon film is lower than that in annealing in an oxygen-only atmosphere. Is thought to improve.

Here, when the substrate temperature during annealing is increased, the dehydration effect of the interlayer insulating film 40 is improved, while the moisture in the interlayer insulating film 40 passes through the first capacitor protective insulating film 39 and forms the capacitor dielectric film 24a. It is conceivable to diffuse to Therefore, the substrate temperature during annealing is preferably as low as possible in view of preventing deterioration of the capacitor dielectric film 24a during annealing. If ozone is added to the annealing atmosphere as described above, it is considered that the dehydration effect on the interlayer insulating film 40 is maintained by the strong oxidizing power of ozone even if the substrate temperature is lowered in this way.

[0155] By the way, it is considered that the amount of water contained in the silicon oxide film formed by the HDPCVD method varies depending on the film formation temperature.

FIGS. 15 and 16 are graphs obtained by investigating the moisture content of the silicon oxide film formed at various film formation temperatures by TDS analysis using the HDPCVD method. [0157] In these figures, sample E was measured in the absence of a silicon wafer, as in Figs.

[0158] Samples D3 to D5 had film formation temperatures of 250 ° C and 30 respectively in the HDPCVD method.

A silicon oxide film is formed on a silicon wafer at 0 ° C and 400 ° C.

As is apparent from FIGS. 15 and 16, sample D5, which has the highest film formation temperature among the three samples, has the smallest amount of water released from the film. Sample D3, which has the lowest film formation temperature, has the highest water content.

[0160] The silicon oxide film used as the interlayer insulating film 40 preferably has a low moisture content. However, if the deposition temperature is increased to 400 ° C in order to reduce the moisture content, Therefore, the capacitor dielectric film 24a may be deteriorated by the hydrogen activated.

Therefore, from the viewpoint of preventing the capacitor dielectric film 24a from being deteriorated when the interlayer insulating film 40 is formed, the film forming temperature of the interlayer insulating film 40 is as low as possible, for example, 350 ° C. or less. Is preferred.

On the other hand, if the film forming temperature is too low, the amount of moisture contained in the interlayer insulating film 40 is increased as shown in FIGS. 15 and 16. When the amount of moisture increases in this way, when the interlayer insulating film 40 is annealed, the capacitor dielectric film 24a is deteriorated by moisture in the film.

[0163] Therefore, from the viewpoint of preventing the deterioration of the capacitor dielectric film 24a due to moisture, it is not preferable that the film formation temperature of the interlayer insulating film 40 is too low. The film formation temperature is 250 ° C or higher. preferable.

[0164] In this way, by forming the interlayer insulating film 40 by the HDPCVD method at a film forming temperature of 250 ° C or higher and 350 ° C or lower, damage to the capacitor dielectric film 24a can be minimized. .

[0165] As described above, in the FeRAM manufacturing process, when the interlayer insulating film 40 is formed by the HDPCVD method, the film formation temperature is made very low so that the capacitor dielectric film 24a is not deteriorated by hydrogen, and By annealing and dehydrating the interlayer insulating film 40 after the film formation, the damage to the capacitor Q during the process can be most effectively reduced.

[0166] On the other hand, in ordinary logic products other than FeRAM, we are concerned about capacitor deterioration. Since there is no need, the interlayer insulating film can be formed at a higher deposition temperature than that of FeRAM. Since the interlayer insulating film obtained at such a high deposition temperature has a small amount of moisture in the film as described above, it is not necessary to perform annealing for dehydration as in this embodiment. .

In the present embodiment described above, annealing was performed on the interlayer insulating film 40 in a mixed atmosphere of oxygen and ozone, and the interlayer insulating film 40 was dehydrated.

[0168] For the purpose of such dehydration, the interlayer insulating film 40 is annealed in an atmosphere containing other oxidizing gas, for example, nitrogen dioxide (N 0), in addition to the mixed atmosphere of oxygen and ozone.

2

I will be relieved.

[0169] However, according to experiments conducted by the inventors of the present application, such a diacid-nitrogen anneal was applied to an oxide silicon film containing a large amount of moisture formed at a low temperature by the HDPCVD method. Even when I went there, I couldn't see the effect of dehydration.

[0170] Therefore, the silicon oxide film formed by the low-temperature HDPCVD method suitable as an interlayer insulating film of FeRAM is effective by annealing in a mixed atmosphere of ozone and oxygen as in this embodiment. Can be dehydrated.

[0171] However, as seen in sample D2 in Fig. 14, the effect of dehydration is seen to some extent even in a 100% oxygen atmosphere, so annealing may be performed in an oxygen-only atmosphere.

[0172] Although it is conceivable to dilute the annealing atmosphere with an inert gas, it is not preferable to add an inert gas to the atmosphere from the viewpoint of increasing the oxidizing power of the atmosphere. It is preferable to carry out the fire in an atmosphere that only powers oxygen and oxygen.

[0173] Further, in the above, annealing force is obtained by annealing the interlayer insulating film 40 in a non-plasma atmosphere, and the annealing may be performed in a plasma atmosphere!

Claims

The scope of the claims

[1] forming a base insulating film above the semiconductor substrate;

Forming a capacitor including a lower electrode, a capacitor dielectric film made of a ferroelectric material, and an upper electrode on the base insulating film;

Forming a first capacitor protective insulating film covering the capacitor;

Forming an interlayer insulating film on the first capacitor protective insulating film by a plasma CVD method for applying a bias voltage to the semiconductor substrate;

Annealing the interlayer insulating film in an atmosphere containing ozone or oxygen. A method of manufacturing a semiconductor device, comprising:

[2] The method for manufacturing a semiconductor device according to [1], wherein the step of annealing the interlayer insulating film is performed in an atmosphere composed of only ozone and oxygen.

[3] The method for manufacturing a semiconductor device according to [1], wherein the step of annealing the interlayer insulating film is performed in an atmosphere made of only oxygen.

4. The method for manufacturing a semiconductor device according to claim 1, wherein the step of annealing the interlayer insulating film is performed at a substrate temperature higher than a film forming temperature of the interlayer insulating film.

[5] The method of manufacturing a semiconductor device according to [1], wherein the step of annealing the interlayer insulating film is performed at a substrate temperature of 350 ° C. or higher and 600 ° C. or lower.

6. The semiconductor according to claim 1, wherein, in the step of forming the first capacitor protective insulating film, an alumina film is formed by an ALD (Atomic Layer Deposition) method as the first capacitor protective insulating film. Device manufacturing method.

7. The method for manufacturing a semiconductor device according to claim 6, wherein in the ALD method, a mixed gas of an organoaluminum compound and ozone is used as a reaction gas.

[8] The method further comprises a step of flattening the surface of the interlayer insulating film by a CMP (Chemical Mechanical Polishing) method,

2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of annealing the interlayer insulating film is performed after the flattening.

[9] After the step of annealing the interlayer insulating film, a step of forming a second capacitor protection insulating film on the interlayer insulating film; Forming a hole in the first capacitor protective insulating film, the interlayer insulating film, and the second capacitor protective insulating film on the upper electrode;

2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of annealing the capacitor dielectric film in an oxygen-containing atmosphere after the step of forming the holes.

[10] The method for manufacturing a semiconductor device according to claim 1, wherein the deposition temperature of the interlayer insulating film is 250 ° C. or higher and 350 ° C. or lower.

[11] The step of forming the capacitor comprises:

Forming a first conductive film on the base insulating film;

Forming a ferroelectric film on the first conductive film;

Forming a second conductive film on the ferroelectric film;

Forming a hard mask on the second conductive film;

The method of claim 1, further comprising: etching and removing the first conductive film, the ferroelectric film, and the second conductive film in a region not covered with the hard mask. A method for manufacturing a semiconductor device.