WO2008022447A1

WO2008022447A1 - Digital data acquisition system

Info

Publication number: WO2008022447A1
Application number: PCT/CA2007/001458
Authority: WO
Inventors: Bjarni V. Tryggvason
Original assignee: Tryggvason Bjarni V
Priority date: 2006-08-21
Filing date: 2007-08-21
Publication date: 2008-02-28

Abstract

A digital data acquisition apparatus multiplexer signals through a single analog to digital converter (ADC) and then to a digital signal processor (DSP), preferably a field programmable gate array which modulates several analog input signals such that one ADC can simultaneously sample several independent signals with the individual signals subsequently recovered within the DSP by digital processing.

Description

DIGITAL DATA ACQUISITION SYSTEM BACKGROUND OF THE INVENTION

FIELD OF THE INVENTION

This invention relates to a digital data acquisition system and in particular to a system and method for converting a plurality of analog signals into a digital signal.

The invention also provides a system in which the original analog signals are individually coded, combined into a single analog signal, which is digitized, and then the individual signals are recovered at high fidelity through digital processing.

DESCRIPTION OF RELATED ART

Over the past two decades the use of analog signal recording has been drastically reduced as high performance digital data acquisition electronics have been developed. Almost all systems now use digital data acquisition and analysis. An essential difference between analog recording and digital recording is that in analog recording a signal is recorded continuously for example on a magnetic tape or is analyzed in analog electronic circuits. The frequency content that can be retained in such recordings or analysis is a function of the recording medium capability and the ability of the electronics to follow the time variations in the signal. Equipment such as tape recorders are capable of recording very high signal frequencies. For example an analog tape recorder used in music recordings can record frequencies of 40,000 Hz and higher. A tape recorder for video signals will typically be able to record signal variations in the tens of MHz . When such devices are used to record signals that a have much lower frequency content, the fast response of the recording devices is able to record the signal without distortion of the low frequency portion of the signal since any high frequency signals mixed in with the signal of interest will be captured correctly. In analog recording the signal will be continuously recorded in time, capturing essentially the entire signal. With digital recording only a small fraction of a signal is sampled and stored or analyzed. The signal is passed to an analog to digital converter (ADC), which samples the instantaneous value of the signal only at discrete times as controlled by the sampling electronics. For example a particular signal may be sampled at 1000 times per second at time intervals spaced apart by 0.001 second. The sampling process with modern ADCs typically takes microseconds or less. Hence, only a small fraction of the signal is sampled and is used to approximate the whole signal in subsequent display or analysis. As described below care must be taken to ensure that this sampled subset of the original signal accurately represents the portion of the signal that is of interest.

An ADC converter generates an approximation of the continuously varying analog signal that discretizes the signal in two ways. First, the digital representation of the analog signal can represent the originally continuously varying analog signal only in the form of discrete steps, i.e. the digital approximation of the analog signal can take on only specific discrete values. For example if an 8-bit ADC is used to sample an analog signal that could range between 0 to 10V, the only levels that could be stored would be multiples of the minimum voltage change that could be detected, which would be 10 V/2⁸ = 10 V/256 = 0.039063 V. Hence any signal between 0 V and 0.039063 V would be represented as 0; a signal between 0.039063 V and 0.078125 V would be represented as 0.039063 V, a signal between 0.078126 V and 0.117189 V, would be represented as 0.078126 V, etc.

The digitizing process thus loses some of the information in the original signal. The number of bits in the digital representation of the signal defines the resolution of the ADC. A 10-bit ADC will have four times the resolution of an 8-bit ADC. A 16-bit ADC will have 256 times better resolution than an 8-bit ADC. For a 16-bit ADC the discrete step size in the above example becomes 0.000152 V, which clearly will have much less error than an 8-bit representation.

The second discretization occurs in time. As described above, an ADC will sample a signal only at specific time intervals. The signal will be sampled, for example over small time intervals of 1 microsecond or less. The sampling process will be repeated at fixed time intervals. As described above, for a sampling rate of 1000 s/s, the interval between samples will be 0.001 s. Hence only a small fraction of the original signal is sampled. In the example given 99.9 % of the signal is ignored, while only 0.1 % is sampled. Depending on the nature of the signal unless the proper analog signal conditioning is applied prior to digitizing, this can lead to significant distortion in the representation of the signal of interest. If in the time interval between samples the signal does not change by more than the discretization resolution, no information is lost due to the missing segment of the signal. However, if there is variation in the signal level in between the samples that exceeds the discretization resolution, there is a loss of information about the signal. Typically, in most real situations, a signal will be composed of a possibly slowly varying output from some measurement device plus an electrical noise signal that can have both well defined frequency content as well as random noise. The noise components can arise either due to the random input that drives a device producing a signal, or from noise added to the output signal of the device or picked up along the transmission path prior to the ADC. For example, the noise could come from pickup of the electromagnetic signals coming from the numerous radio and television signals. These are in the frequency range 500 kHz to GHz. Unless care is taken to protect the signal from such noise it will be added to any real signal coming from the device generating the signal of interest.

Since the noise portion of the signal is effectively random, the timing of the sampled portion of the signal will be uncorrelated with the occurrence of the noise signal. The effect of sampling a noisy signal at sampling rates that are lower than the frequency of the noise component is that the noise component will appear mixed in with the desired signal.

When a signal is sampled at a given rate, the maximum frequency that can be identified in the discretely sampled version of the signal is given by the Nyquist frequency, which is one-half the sampling rate. For example, if a signal is sampled at 1000 s/s, the Nyquist frequency will be 500 Hz. No signal above this frequency can be detected in the discretely sampled version of the signal even if the original analog signal contains frequency components above the Nyquist frequency (500 Hz in this example). However, the energy associated with signal components above the Nyquist frequency will appear in the sampled signal but at frequencies below the Nyquist frequency. This shifting of high frequencies into the frequency range that is preserved in the discretely sampled signal is called aliasing. The frequency band that is retained in the discretely sampled signal will include the band f,_ow < f< fh_igh or (f, ≤ f ≤ f_h ) where the limiting frequencies are given by

and f_h =

T 2δt

where T is the total time over which the signal was sampled and δt is the time interval between sampling of the signal. All frequency components that are in the original signal prior to digitizing will appear within this band. This includes both signal components that are within this band as well as signal components that have been aliased into the frequency band. This aliasing phenomenon is well known and is described in many books on digital data acquisition.

To ensure that the signal within the retained frequency band is a true representation of the portion of the original signal that is within the retained frequency band, the signal must be filtered prior to the digitizing process to remove frequency components that are at frequencies above the retained frequency band of. Hence digital data acquisition systems will typically include an electronic analog low pass filter circuit ahead of the ADC to attenuate signal frequencies above the frequencies of interest. This filter is typically referred to as a low pass filter (LPF). Many designs and devices for an LPF are available. There is however a common error made in selecting the cutoff frequency for the LPF in a digital data acquisition system. In many data acquisition systems the filter is set at or near the Nyquist frequency described above based on the assumption that this frequency is the highest one that can be identified within the retained signal. However, realistic low pass filters act to slowly attenuate the signal amplitudes above the LPF cutoff frequency. By convention, the cutoff frequency is defined as the frequency where the signal has been attenuated by 3 dB (30% of amplitude). If the cutoff frequency is set to the Nyquist frequency, there will typically be aliasing of signals into the frequency band of interest, since above the cutoff frequency the attenuation increases slowly with frequency. Hence, proper selection of the filter should place the LPF cutoff frequency at approximately one-fifth the Nyquist frequency if a fourth order filter is used. The attenuation at the Nyquist frequency will then be quite high, limiting aliasing into the frequency band of interest, which is then defined as /_; to 0.2/_A . Note that the digitized signal includes frequencies up to f_h . However, there can be increased error in the sampled signal as this Nyquist frequency is approached. The foregoing considerations result in the typical configuration for a data acquisition system illustrated in Fig. 1. The system includes a buffer amplifier 1 , which could be a differential amplifier, for receiving an analog signal, an LPF 2, a driver amplifier 3 and an ADC 4. It should be noted that these are the basic elements that are required. A practical system may include various additional elements such as multiplexers, band pass filters and precision voltage reference for calibration. The LPF in this system configuration must be an analog device and the cutoff frequency must be set consistently with the sampling interval and the ADC resolution. For a single purpose data acquisition system this poses little problem, because once the frequency band of interest is selected, the filter frequency and the sampling rate can be selected and set to constant values. However, data acquisition systems are typically designed for multiple applications, and thus are typically capable of a wide range of sampling rate. However, the LPF cutoff frequency must always be matched to the specific selected sampling rate. This requires that if the sampling rate is changed then the LPF cutoff frequency must also be changed. There are devices that allow for this. One option is to have the LPF as a plug in unit that can be physically changed according to the required sampling rate. This is cumbersome and requires the purchase or manufacture of new LPF modules for each sample rate. There are also signal conditioning electronics available that include complex filter stages where the filter cutoff frequency can be set within some range or where one of several preset filter cutoff frequencies can be selected. This requires complex and costly electronic circuitry. One variant of this approach that has modest cost is to use switched capacitive filters. However, this type of filter has relatively poor performance compared to filters with dedicated cutoff frequencies. Digital data acquisition systems are typically designed to sample multiple input signals. To limit the requirement for multiple ADCs, which are typically the most expensive components, the configuration shown in Figure 1 is altered as shown in Figure 2 which illustrates several analog input channels including amplifiers 1 and LPF's 2, and a multiplexer 5 which can select each analog signal sequentially and pass that on to a single ADC. This requires that the ADC sample at a much faster rate than is required for any single channel. It also results in non-simultaneous sampling of the signals, since the analog signals are passed in sequence to the ADC. As illustrated in Fig. 3, this can be corrected by adding a set of sample and hold (S&H) devices 6 that can be triggered to sample the analog signals simultaneously and hold them fixed while the multiplexer 5 sequences through the signals and passes them on to the ADC 4. This approach requires a number of electronic components to implement.

BRIEF SUMMARY OF THE INVENTION In accordance with the present invention, use is made of signal modulation and digital processing to achieve the multiplexing of several signals onto one stream such that one ADC can be used to sample several signals simultaneously without the need for either a physical multiplexing device or sample and hold devices. The new approach can achieve high performance and comparatively lower cost for a multi-channel data acquisition system.

In accordance with one aspect, the invention provides an apparatus for converting a plurality of individual analog signals of different frequencies into digital signals comprising:

(a) a buffer for each analog signal; (b) low pass filter, anti-aliasing means connected to each buffer;

(c) a buffer amplifier connected to each low pass filter for receiving a filtered analog signal therefrom;

(d) a summing amplifier for receiving a first analog signal from one said first amplifier; (e) a plurality of signal multipliers for receiving the analog signals from the remaining first amplifiers;

(f) an analog to digital converter for converting the summed analog signal from the summing amplifier to a digital signal;

(g) a digital signal processor for generating a square wave; and (h) a gain follower stage for receiving the square wave from the digital signal processor; and

(i) a plurality of band pass filters for receiving the square wave from the signal processor, each band pass filter being adapted to pass only one of the fundamental frequency or one higher harmonic thereof to their respective signal multiplier, whereby the outputs of the multipliers are fed to the summing amplifier with the first analog signal, and the summing amplifier output is passed to the analog to digital converter for converting the summed analog signal to digital signals.

In accordance with another aspect, the invention provides a method of converting a plurality of individual analog signals into digital signals comprising the steps of:

(a) passing all signals sequentially through individual gain/buffer stages and buffer amplifiers;

(b) passing a first signal from one buffer amplifier directly to a summing amplifier and then to a digital signal processor;

(c) passing each of the remaining signals from their respective buffer amplifiers through individual multipliers; (d) generating a square wave in the digital signal processor and feeding the square wave through band pass filters to said multipliers, wherein each filter is programmed to pass only one of the fundamental frequency or one higher harmonic thereof to their respective signal multiplier; (e) passing the output of each multiplier to said summing amplifier to produce a summed signal with said first signal; and (f) passing the summed signal to said digital signal processor for digital recovery of said signals.

BRIEF DESCRIPTION OF THE DRAWINGS Figures 1 to 3 are schematic block diagrams of prior art systems for converting analog signals into digital signals;

Figure 4 is a schematic block diagram of a digital data system in accordance with the present invention;

Figure 5 is a graph of voltage versus time for three unmodulated signals; Figure 6 is a graph of voltage versus time for the signals of Fig. 5 after modulation;

Figure 7 is a graph similar to Fig. 6 showing the sum of the modulated signals of Fig. 6. Figure 8 is a graph showing spectral densities of the three signals of Fig. 5;

Figure 9 is a graph showing the spectral density for the sum of the modulated signals; Figures 10 to 12 are graphs showing the individual, original and recovered signals of Fig. 5.

DETAILED DESCRIPTION OF THE INVENTION With reference to Figure 4, in the apparatus of the present invention a plurality of input channels (in this case four) are used to process individual analog signals. Each analog signal passes through a gain/buffer stage 8 (which can be an instrumentation or differential amplifier and could have variable gain) then through a low pass filter anti-aliasing stage 9, and a buffer amplifier 10. The output of the buffer amplifier 10 for a first channel passes directly to one input of a summing amplifier 11. The output of the buffers 10 for all other channels pass through multipliers 12 and then to other inputs of the summing amplifier 11. The signal from the amplifier 11 passes through an ADC 13 to an FPGA 14. Within the FPGA 14 a square wave is generated and passed through a gain follower stage 15. Also with in the FPGA the fundamental and harmonic components of the square wave are used to de-modulate the signal from the ADC 13 to recover the original input signals. The output of the gain follower stage 15 is passed to three band pass filter stages 17. One band filter 17 is set to pass only the fundamental frequency. A second band filter 17 passes only an amplified second harmonic and the third band pass filter 17 singles out and amplifies the third harmonic. The outputs of the band pass filters 17 are fed to the inputs of their respective multipliers 12. Alternatively, three gain follower stages 15 (one for each multiplier 12) receive separate sine waves at frequencies corresponding to either the fundamental or to one of the higher harmonics of the above-mentioned square wave from the FPGA and the band pass filters 17 are omitted, the outputs of the follower stages going directly to the multipliers 12. The multiplier outputs are passed to the respective inputs of the summing amplifier. The summing amplifier output is passed to the ADC 4. The ADC digital output is passed to the FPGA 13.

The individual signals are recovered within the FPGA 14 as follows: the summed signal is passed through a digital low pass filter to recover immediately the digitized version of a first signal 1. The summed signal is multiplied in the time domain by a sine wave corresponding to the fundamental of the square wave generated at the output of the FPGA 14. This multiplied signal is then passed through a low pass filter to recover a second signal. The summed signal is multiplied by a sine wave with a frequency at the first harmonic of the square wave. This signal is passed through a low pass filter to recover a third signal 3. The summed signal is multiplied by a sine wave with the frequency of the second harmonic. This is passed through a low pass filter to recover a fourth signal 4. The advantages of the system described above are that the electronics design is simplified while retaining high performance, and the architecture does not require physical multiplexers or sample and holds, yet provides simultaneous sampling and high performance.

Figure 5 shows three example signals, each with comparable bandwidth. The signals are modulated according to the approach shown in Figure 4 as follows: ym_λ {t) = y_λ {t)

ym₂ (t) = y₂ (t)sm(ω_]t)

ym₃ (t) = y₃{ήsm(ω₂ή

where y_x{t) , y₂it) and y₃(t) are the original signals, ym₂(ή and ym^{t) are the modulated version of signals 1 and 2 and ω_λ and ω₂ are the first and second harmonics of the modulating square wave. The amplitudes for the modulation signals are each set to one, reflecting appropriate amplification in the band pass filter stages between the follower and the multiplier stages.

The modulated signals are shown in Figure 6 and the summed modulated signals are shown in Figure 7. Figure 8 shows the power spectral densities for the original s signals and Figure 9 shows the power spectral density for the sum of the modulated signals.

The signal shown in Figure 7 is sampled by the single analog to digital converter (ADC). The output of the ADC is passed to the FPGA. Within the FPGA the summed signal is passed through a digital low pass filter to recover the original signal 1 ; the summed signal is multiplied by the first harmonic of the square wave, then low pass filtered to recover signal 2; the summed signal is multiplied by the second harmonic of the square wave and low pass filtered to recover signal 3. The original and recovered signals are shown in Figures 10, 11 and 12 for signal 1 , 2 and 3, respectively. These show that the original signals are recovered with great accuracy.

There are other methods for coding the signals such as bit patterns. The essential idea is to generate the codes (the sine wave harmonics of a square wave in the above example) to be applied to the signal inside the FPGA and to use these codes again inside the FPGA to decode the output of the ADC into accurate digital representations of the original signals. An important advantage is that the codes are generated in the FPGA and used subsequently in the FPGA to decode the summed signal into its signal components. The system described herein has clear advantages over current architectures for digital data acquisition electronics. The system eliminates the need for physical multiplexers and sample and holds. Simultaneous sampling is still achieved as is high performance. While the example shows three input signals, many more can be accommodated with a single ADC by using additional harmonics of the modulating square wave.

An alternative approach to the electronics is to have the FPGA output directly sine waves at the desired harmonics. This eliminates the need for band pass filters ahead of the multiplier states. While the modulation signals shown in the example are sine waves, there are alternatives to the modulation. For example, coded bit patterns could be used. Recovery of these within the FPGA can make use of Phase Lock Loop (PLL) techniques.

Claims

CLAIMS:

1. An apparatus for converting a plurality of individual analog signals of different frequencies into digital signals comprising:

2. The apparatus of claim 1 , wherein said digital signal processor is a field- programmable gate array.

3. The apparatus of claim 1 , wherein said buffer is an instrumentation or differential amplifier.

4. The apparatus of claim 3, wherein said buffer amplifier has variable gain.

5. A method of converting a plurality of individual analog signals into digital signals comprising the steps of:

(a) passing all of the analog signals simultaneously through individual gain/buffer stages, anti-aliasing filter stages, and output buffer amplifiers; (b) passing a first analog signal from one buffer amplifier directly to a summing amplifier;

(c) passing each of the remaining analog signals from their respective output buffer amplifiers through individual multipliers; (d) generating a set of code signals in a digital signal processor, with individual codes being generated to be combined with each analog signal;

(e) transmitting the code signals from the digital signal processor through buffer amplifiers and ultimately to one input of the multipliers, such that each multiplier receives a unique code signal;

(f) within the individual multipliers modulating each analog signal with the unique code generated within the digital signal processor;

(g) passing the output of each multiplier to said summing amplifier to produce at the output of the summing amplifier an analog signal that is the sum of all the coded analog signals;

(h) passing the summed signal to an analog to digital converter; (i) passing the output of the analog to digital converter to the digital signal processor, and;

(j) within the digital signal processor, using the code signal to decode the summed digital signal to recover the digital version of each of the analog input signals.

6. A method of converting a plurality of individual analog signals into digital signals comprising the steps of:

(a) passing all of the analog signals simultaneously through individual gain/buffer stages, anti-aliasing filter stages and output buffer amplifiers;

(b) passing a first analog signal from one buffer amplifier directly to a summing amplifier;

(c) passing each of the remaining analog input signals from their respective output buffer amplifiers through the individual multipliers;

(d) generating a square wave in a digital signal processor;

(e) transmitting the square wave from the digital signal processor through buffer amplifiers and ultimately to the inputs of the filter stages; (f) setting each filter stage to isolate and output only one of the fundamental frequency or one higher harmonic of the square wave with each filter outputting its own unique such frequency or higher harmonic amplified such that output sine wave from all filters have the same amplitude;

(g) passing the output sine wave from each filter to one input of individual multiplier stages such that each multiplier stage receives a sine wave with a unique frequency corresponding to either the fundamental frequency or one higher harmonic of the square wave; (h) within the individual multipliers modulating each analog input signal with the unique sine wave;

(i) passing the output of each multiplier to said summing amplifier to produce at the output of the summing amplifier an analog signal that is the sum of all the individually modulated analog input signals; (j) passing the summed signal to an analog to digital converter; and,

(k) passing the output of the analog to digital converter to the digital signal processor.

7. The method of claim 6, wherein the individual digitized signals are recovered in the digital signal processor by (i) passing the summed signal through a first digital low pass filter to recover the digitized version of a first signal; (ii) multiplying the summed signal by a sine wave corresponding to the fundamental of the square wave generated at the output of the digital signal processor; (iii) passing the multiplied signal through a second low pass filter to recover a second signal; (iv) multiplying the summed signal with a frequency at a second harmonic of the square wave and passing the thus multiplied signal through a low pass filter to recover a third signal; and (v) repeating step (iv) for each remaining signal at successively higher harmonics to recover any additional signals.