WO2008018989A3 - Fully- buffered dual in-line memory module with fault correction - Google Patents

Fully- buffered dual in-line memory module with fault correction Download PDF

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Publication number
WO2008018989A3
WO2008018989A3 PCT/US2007/016661 US2007016661W WO2008018989A3 WO 2008018989 A3 WO2008018989 A3 WO 2008018989A3 US 2007016661 W US2007016661 W US 2007016661W WO 2008018989 A3 WO2008018989 A3 WO 2008018989A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory
fully
memory module
line memory
blocks
Prior art date
Application number
PCT/US2007/016661
Other languages
French (fr)
Other versions
WO2008018989A2 (en
Inventor
Sehat Sutardja
Saeed Azimi
Original Assignee
Marvell World Trade Ltd
Sehat Sutardja
Saeed Azimi
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/584,946 external-priority patent/US7818639B2/en
Application filed by Marvell World Trade Ltd, Sehat Sutardja, Saeed Azimi filed Critical Marvell World Trade Ltd
Publication of WO2008018989A2 publication Critical patent/WO2008018989A2/en
Publication of WO2008018989A3 publication Critical patent/WO2008018989A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50016—Marginal testing, e.g. race, voltage or current testing of retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/72—Masking faults in memories by using spares or by reconfiguring with optimized replacement algorithms
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4061—Calibration or ate or cycle tuning

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

A memory module comprises first memory that stores data in memory blocks; second memory that temporarily stores data from at least one of the memory blocks and third memory for storing a relationship between addresses of the at least one of the memory blocks in the first memory and corresponding addresses of the data from the at least one of the memory blocks in the second memory. Storage capacities of the second and third memories are less than a storage capacity of the first memory. A control module selectively transfers data in the at least one of the memory blocks in the first memory to the second memory and stores and retrieves data from the second memory for the at least one of the memory blocks based on the relationship during the testing.
PCT/US2007/016661 2006-08-04 2007-07-24 Fully- buffered dual in-line memory module with fault correction WO2008018989A2 (en)

Applications Claiming Priority (16)

Application Number Priority Date Filing Date Title
US82142206P 2006-08-04 2006-08-04
US60/821,422 2006-08-04
US82398906P 2006-08-30 2006-08-30
US60/823,989 2006-08-30
US82536106P 2006-09-12 2006-09-12
US60/825,361 2006-09-12
US82797606P 2006-10-03 2006-10-03
US60/827,976 2006-10-03
US11/584,946 US7818639B2 (en) 2002-05-30 2006-10-23 Fully-buffered dual in-line memory module with fault correction
US11/584,946 2006-10-23
US11/655,449 US7814382B2 (en) 2002-05-30 2007-01-19 Fully-buffered dual in-line memory module with fault correction
US11/655,603 2007-01-19
US11/655,451 US7823030B2 (en) 2002-05-30 2007-01-19 Fully-buffered dual in-line memory module with fault correction
US11/655,451 2007-01-19
US11/655,603 US7870331B2 (en) 2002-05-30 2007-01-19 Fully-buffered dual in-line memory module with fault correction
US11/655,449 2007-01-19

Publications (2)

Publication Number Publication Date
WO2008018989A2 WO2008018989A2 (en) 2008-02-14
WO2008018989A3 true WO2008018989A3 (en) 2008-07-10

Family

ID=39033464

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/016661 WO2008018989A2 (en) 2006-08-04 2007-07-24 Fully- buffered dual in-line memory module with fault correction

Country Status (1)

Country Link
WO (1) WO2008018989A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102011079780A1 (en) * 2011-07-26 2013-01-31 Hilti Aktiengesellschaft Apparatus and method for testing a memory of an electrical device
US11481126B2 (en) 2016-05-24 2022-10-25 Micron Technology, Inc. Memory device error based adaptive refresh rate systems and methods

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5758056A (en) * 1996-02-08 1998-05-26 Barr; Robert C. Memory system having defective address identification and replacement
US6484271B1 (en) * 1999-09-16 2002-11-19 Koninklijke Philips Electronics N.V. Memory redundancy techniques
US6778457B1 (en) * 2003-02-19 2004-08-17 Freescale Semiconductor, Inc. Variable refresh control for a memory
US20040218439A1 (en) * 2003-01-29 2004-11-04 Stmicroelectronics S.A. Process for refreshing a dynamic random access memory
US7073099B1 (en) * 2002-05-30 2006-07-04 Marvell International Ltd. Method and apparatus for improving memory operation and yield

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5758056A (en) * 1996-02-08 1998-05-26 Barr; Robert C. Memory system having defective address identification and replacement
US6484271B1 (en) * 1999-09-16 2002-11-19 Koninklijke Philips Electronics N.V. Memory redundancy techniques
US7073099B1 (en) * 2002-05-30 2006-07-04 Marvell International Ltd. Method and apparatus for improving memory operation and yield
US20040218439A1 (en) * 2003-01-29 2004-11-04 Stmicroelectronics S.A. Process for refreshing a dynamic random access memory
US6778457B1 (en) * 2003-02-19 2004-08-17 Freescale Semiconductor, Inc. Variable refresh control for a memory

Also Published As

Publication number Publication date
WO2008018989A2 (en) 2008-02-14

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