WO2008016421A3 - Mixed-use memory array with different data states and method for use therewith - Google Patents

Mixed-use memory array with different data states and method for use therewith Download PDF

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Publication number
WO2008016421A3
WO2008016421A3 PCT/US2007/013772 US2007013772W WO2008016421A3 WO 2008016421 A3 WO2008016421 A3 WO 2008016421A3 US 2007013772 W US2007013772 W US 2007013772W WO 2008016421 A3 WO2008016421 A3 WO 2008016421A3
Authority
WO
WIPO (PCT)
Prior art keywords
data states
memory array
mixed
different data
states
Prior art date
Application number
PCT/US2007/013772
Other languages
French (fr)
Other versions
WO2008016421A2 (en
Inventor
Roy E Scheuerlein
Christopher J Petti
Original Assignee
Sandisk 3D Llc
Roy E Scheuerlein
Christopher J Petti
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/497,021 external-priority patent/US7486537B2/en
Priority claimed from US11/496,870 external-priority patent/US20080025069A1/en
Application filed by Sandisk 3D Llc, Roy E Scheuerlein, Christopher J Petti filed Critical Sandisk 3D Llc
Publication of WO2008016421A2 publication Critical patent/WO2008016421A2/en
Publication of WO2008016421A3 publication Critical patent/WO2008016421A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G11C17/165—Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5692—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency read-only digital stores using storage elements with more than two stable states
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5641—Multilevel memory having cells with different number of storage levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5646—Multilevel memory with flag bits, e.g. for showing that a "first page" of a word line is programmed but not a "second page"
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/72—Array wherein the access device being a diode

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)

Abstract

A mixed-use memory array with different data states and a method for use therewith are disclosed. In one preferred embodiment, a memory array is provided comprising a plurality of memory cells, each memory cell comprising a memory element comprising a switchable resistance material configurable to one of at least three resistivity states. A first set of memory cells uses X resistivity states to represent X respective data states, and a second set of memory cells uses Y resistivity states to represent Y respective data states, wherein X≠Y.
PCT/US2007/013772 2006-07-31 2007-06-12 Mixed-use memory array with different data states and method for use therewith WO2008016421A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/497,021 US7486537B2 (en) 2006-07-31 2006-07-31 Method for using a mixed-use memory array with different data states
US11/497,021 2006-07-31
US11/496,870 US20080025069A1 (en) 2006-07-31 2006-07-31 Mixed-use memory array with different data states
US11/496,870 2006-07-31

Publications (2)

Publication Number Publication Date
WO2008016421A2 WO2008016421A2 (en) 2008-02-07
WO2008016421A3 true WO2008016421A3 (en) 2008-05-02

Family

ID=38997615

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/013772 WO2008016421A2 (en) 2006-07-31 2007-06-12 Mixed-use memory array with different data states and method for use therewith

Country Status (2)

Country Link
TW (1) TWI483262B (en)
WO (1) WO2008016421A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4719910B2 (en) * 2008-11-26 2011-07-06 国立大学法人東北大学 Manufacturing method of semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0788113A1 (en) * 1996-01-31 1997-08-06 STMicroelectronics S.r.l. Multilevel memory circuits and corresponding reading and writing methods
US6483734B1 (en) * 2001-11-26 2002-11-19 Hewlett Packard Company Memory device having memory cells capable of four states
DE102004029939A1 (en) * 2004-06-21 2006-01-12 Infineon Technologies Ag Memory cell component with non-volatile memory (NVM) cells with cells distributed in memory sections so configured that cells of a memory section

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6034882A (en) * 1998-11-16 2000-03-07 Matrix Semiconductor, Inc. Vertically stacked field programmable nonvolatile memory and method of fabrication
US6420215B1 (en) * 2000-04-28 2002-07-16 Matrix Semiconductor, Inc. Three-dimensional memory array and method of fabrication
US6768661B2 (en) * 2002-06-27 2004-07-27 Matrix Semiconductor, Inc. Multiple-mode memory and method for forming same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0788113A1 (en) * 1996-01-31 1997-08-06 STMicroelectronics S.r.l. Multilevel memory circuits and corresponding reading and writing methods
US6483734B1 (en) * 2001-11-26 2002-11-19 Hewlett Packard Company Memory device having memory cells capable of four states
DE102004029939A1 (en) * 2004-06-21 2006-01-12 Infineon Technologies Ag Memory cell component with non-volatile memory (NVM) cells with cells distributed in memory sections so configured that cells of a memory section

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
LE K Y ET AL: "Evaluation of SiO2 Antifuse in a 3D-OTP Memory", IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 4, no. 3, September 2004 (2004-09-01), pages 416 - 421, XP011123442, ISSN: 1530-4388 *

Also Published As

Publication number Publication date
TW200818204A (en) 2008-04-16
TWI483262B (en) 2015-05-01
WO2008016421A2 (en) 2008-02-07

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