WO2008009609A2 - Coeur processeur a frequence pilotee et procede de demarrage dudit coeur processeur dans un mode programme - Google Patents
Coeur processeur a frequence pilotee et procede de demarrage dudit coeur processeur dans un mode programme Download PDFInfo
- Publication number
- WO2008009609A2 WO2008009609A2 PCT/EP2007/057129 EP2007057129W WO2008009609A2 WO 2008009609 A2 WO2008009609 A2 WO 2008009609A2 EP 2007057129 W EP2007057129 W EP 2007057129W WO 2008009609 A2 WO2008009609 A2 WO 2008009609A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- interface component
- mode
- processor core
- processor
- information
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 18
- 206010013142 Disinhibition Diseases 0.000 claims description 2
- 230000008569 process Effects 0.000 claims description 2
- 238000004364 calculation method Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 125000004122 cyclic group Chemical group 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 230000001934 delay Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000011282 treatment Methods 0.000 description 1
- 238000010200 validation analysis Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/08—Clock generators with changeable or programmable clock frequency
-
- C—CHEMISTRY; METALLURGY
- C07—ORGANIC CHEMISTRY
- C07D—HETEROCYCLIC COMPOUNDS
- C07D401/00—Heterocyclic compounds containing two or more hetero rings, having nitrogen atoms as the only ring hetero atoms, at least one ring being a six-membered ring with only one nitrogen atom
- C07D401/02—Heterocyclic compounds containing two or more hetero rings, having nitrogen atoms as the only ring hetero atoms, at least one ring being a six-membered ring with only one nitrogen atom containing two hetero rings
- C07D401/12—Heterocyclic compounds containing two or more hetero rings, having nitrogen atoms as the only ring hetero atoms, at least one ring being a six-membered ring with only one nitrogen atom containing two hetero rings linked by a chain containing hetero atoms as chain links
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
Definitions
- the invention relates to a frequency-controlled processor core and a method of starting said processor core in a programmed mode.
- the invention applies to processor cores embedded in aircraft.
- a processor core also known as the CPU card, is an onboard electronic card comprising a processor performing calculations and treatments.
- a processor core may in particular be embedded in an aircraft type system where it performs a set of specific numerical calculations.
- a processor core particularly in the aeronautical field, performs tasks of great criticality, such as the management of flight parameters, and must therefore have significant reliability.
- a processor core is defined by a detailed definition file and validated, and must be the subject of a validation / certification phase both conceptually and materially. It follows in particular that each modification of a characteristic of said processor core must be subject to an evolution of the definition file followed by a study of risk and / or impact on its reliability and those of related equipment.
- one of the characteristics of a processor core that can be modified not only during the design phase but also during the life cycle of said core is the frequency of the components included in the processor core.
- the modification of the frequency of the components included in the processor core is generally referred to as the "clamping / unclamping" of a processor core.
- it is desirable that the "clamping / unclamping" of the processor core can be performed without hardware modification ("without hardware retrofit").
- the interface component when the reading by the interface component of the information on the selected mode proves impossible or erroneous, the interface component is adapted to choose a default mode.
- the processor core comprises a clock delivering a reference clock signal. The frequency of said reference clock signal is then multiplied by the interface component to generate the signals whose frequency corresponding substantially to that described by the configuration of the chosen mode.
- the processor core may receive a protection signal, said signal authorizing or not depending on its value the writing of information to determine which mode of operation should be used.
- the information to determine which operating mode should be used is for example modifiable by programming the non-volatile memory and / or the processor.
- the invention also relates to a method for starting a processor core comprising at least one non-volatile memory comprising a startup program, a bridge interconnecting buses connecting the various components of said processor core, an interface component, the memory non-volatile having at least two frequency configurations each corresponding to a mode of operation of the buses and / or components of said processor core.
- the non-volatile memory includes information to determine which mode of operation is to be used, said information being read by the interface component to determine the mode chosen.
- the method comprises the following steps: a power-up step of the processor core, the components of the processor core being held by the interface component in an inhibited state; a step where the interface component prohibits the resetting of the non-volatile memory; a read access step by the interface component to the information relating to the selected operating mode and the associated configuration contained in the non-volatile memory; a step of generation by the interface component of one or more signals whose frequency corresponds to the configuration of the selected mode, said signals driving the buses and / or the components of said processor core; o a step of disinhibition by the interface component of the different components.
- the method includes a delay step until the reference clock signal satisfies certain defined stability criteria.
- the interface component chooses at the step in place of inaccessible or erroneous information a default mode.
- the method includes a delay step until the buses reach stably their target frequency.
- the latter determines multiplicative factors to be applied to the frequency of a reference clock signal to obtain one or more signals of which the frequency corresponds to that described in the configuration corresponding to the selected mode.
- the advantages of the invention include that it makes it possible to secure and make reliable the management of bus frequency changes. It can be totally managed at the hardware level of the processor core.
- the invention allows a hardware check of the restart configuration with a still valid default configuration, even if the storage area of the configuration is erased.
- FIG. 1 a block diagram of the processor core according to the invention
- FIG. 2 a diagram of a process for starting the processor core in a programmed mode according to the invention
- FIG. 1 shows a block diagram of a processor core according to the invention.
- the frequency-controlled processor core according to the invention comprises in particular at least one processor 1.
- the processor 1 is particularly suitable for performing numerical calculations.
- the processor 1 communicates via at least one processor bus 10 to the other components of the processor core.
- the processor core may also comprise RAM 3, for example DDR-SDRAM type memory.
- the RAM 3 is accessible via a memory bus 1 1.
- the processor core may also include external buses 13, such as one or more PCI buses.
- the processor core comprises a nonvolatile memory 4 comprising the startup program.
- the non-volatile memory 4 may for example be a FLASH memory bank.
- the processor core comprises an interface component 6 between a clock 5 (for example, a quartz), a multiplexed peripheral bus 1 1 to which is connected in particular the nonvolatile memory 4 comprising the startup program, and possibly a signal of protection 7 of the startup program.
- the interface component 6 may be a programmable component.
- the processor core comprises a bridge 2 responsible for managing and interconnecting the buses of said core.
- the startup program included in the nonvolatile memory 4 includes the instructions necessary to start the processor core.
- the non-volatile memory 4 comprises at least two frequency configurations, each corresponding to a mode of operation of the buses and / or components of the processor core: a bridled mode, an unbridled mode.
- the operating frequency of the buses in unbridled mode is greater or equal to the flanged mode.
- the nonvolatile memory 4 comprises information, contained for example in memory locations, for determining which mode of operation should be used for the next start of the processor core.
- the configuration relating to a given operating mode describes in particular the frequency at which the buses must operate and possibly, if relevant, the components of the processor core.
- the protection signal 7 authorizes or not according to its value the writing of the information to determine which mode of operation should be used. For example, when the protection signal 7 is received, it is possible to read but not to write the information to determine which mode of operation should be used. Conversely, when the protection signal 7 is not received, it is possible to write said information.
- the information to determine which operating mode is to be used can be modified by programming the nonvolatile memory 4 and / or the processor 1.
- the interface component 6 receives a reference clock signal 5 from the clock.
- the interface component 6 reads the information on the chosen mode included in the non-volatile memory 4. If the reading of the information on the chosen mode proves impossible or erroneous (the detection can for example be ensured by a mechanism cyclic redundancy check or Cyclic Redundancy Check or by checking the membership of the read values to a predefined value range), the interface component 6 selects a mode by default, corresponding, for example, to the lowest frequency of the different buses and / or components of the processor core. The default mode can in particular be programmed within the interface component 6. This mechanism provides an additional level of security, in particular avoiding the use of a value entered by mistake or inaccurate in the non-volatile memory.
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Organic Chemistry (AREA)
- Microcomputers (AREA)
- Output Control And Ontrol Of Special Type Engine (AREA)
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CA002658634A CA2658634A1 (fr) | 2006-07-21 | 2007-07-11 | Coeur processeur a frequence pilotee et procede de demarrage dudit coeur processeur dans un mode programme |
EP07787400A EP2049967A2 (fr) | 2006-07-21 | 2007-07-11 | Coeur processeur a frequence pilotee et procede de demarrage dudit coeur processeur dans un mode programme |
US12/374,664 US7941583B2 (en) | 2006-07-21 | 2007-07-11 | Controlled frequency core processor and method for starting-up said core processor in a programmed manner |
GB0901092A GB2454379A (en) | 2006-07-21 | 2007-07-11 | Controlled frequency core processor and method for starting-up said core processor in a programmed manner |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR06/06695 | 2006-07-21 | ||
FR0606695A FR2904129B1 (fr) | 2006-07-21 | 2006-07-21 | Coeur processeur a frequence pilotee et procede de demarrage dudit coeur processeur dans un mode programme |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2008009609A2 true WO2008009609A2 (fr) | 2008-01-24 |
WO2008009609A3 WO2008009609A3 (fr) | 2008-03-27 |
Family
ID=38162234
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2007/057129 WO2008009609A2 (fr) | 2006-07-21 | 2007-07-11 | Coeur processeur a frequence pilotee et procede de demarrage dudit coeur processeur dans un mode programme |
Country Status (6)
Country | Link |
---|---|
US (1) | US7941583B2 (fr) |
EP (1) | EP2049967A2 (fr) |
CA (1) | CA2658634A1 (fr) |
FR (1) | FR2904129B1 (fr) |
GB (1) | GB2454379A (fr) |
WO (1) | WO2008009609A2 (fr) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100146169A1 (en) * | 2008-12-05 | 2010-06-10 | Nuvoton Technology Corporation | Bus-handling |
US8276015B2 (en) * | 2009-02-23 | 2012-09-25 | International Business Machines Corporation | Managing the power-performance range of an application |
GB0908882D0 (en) * | 2009-05-22 | 2009-07-01 | Zarlink Semiconductor Inc | Digital/analog phase locked loop |
TWI443495B (zh) * | 2011-09-08 | 2014-07-01 | Asustek Comp Inc | 電腦裝置及中央處理器的頻率調整方法 |
US9135472B2 (en) | 2013-10-31 | 2015-09-15 | Square, Inc. | Systems and methods for secure processing with embedded cryptographic unit |
US10410202B1 (en) * | 2016-12-31 | 2019-09-10 | Square, Inc. | Expedited booting with brownout monitoring |
US10410189B2 (en) | 2017-09-30 | 2019-09-10 | Square, Inc. | Scanning system with direct access to memory |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5542077A (en) * | 1993-09-10 | 1996-07-30 | Compaq Computer Corporation | Personal computer with CMOS memory not having a separate battery |
US6269443B1 (en) * | 1998-12-29 | 2001-07-31 | Intel Corporation | Method and apparatus for automatically selecting CPU clock frequency multiplier |
FR2868563A1 (fr) * | 2004-03-30 | 2005-10-07 | Giga Byte Tech Co Ltd | Dispositif et procede capables de detecter un etat du bois en vue de regler une horloge |
US20050268139A1 (en) * | 2004-05-28 | 2005-12-01 | Asustek Computer Inc. | Main-board and control method thereof |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5935255A (en) * | 1996-02-23 | 1999-08-10 | Cypress Semiconductor Corp. | CPU core to bus speed ratio detection |
TW563012B (en) * | 2000-11-20 | 2003-11-21 | Via Tech Inc | System and method for automatically reading the clock doubling factor of system bus |
US6845444B2 (en) * | 2001-08-23 | 2005-01-18 | Silicon Integrated Systems Corp. | Method and apparatus for reducing strapping devices |
US7299370B2 (en) * | 2003-06-10 | 2007-11-20 | Intel Corporation | Method and apparatus for improved reliability and reduced power in a processor by automatic voltage control during processor idle states |
-
2006
- 2006-07-21 FR FR0606695A patent/FR2904129B1/fr active Active
-
2007
- 2007-07-11 GB GB0901092A patent/GB2454379A/en not_active Withdrawn
- 2007-07-11 WO PCT/EP2007/057129 patent/WO2008009609A2/fr active Application Filing
- 2007-07-11 CA CA002658634A patent/CA2658634A1/fr not_active Abandoned
- 2007-07-11 EP EP07787400A patent/EP2049967A2/fr not_active Withdrawn
- 2007-07-11 US US12/374,664 patent/US7941583B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5542077A (en) * | 1993-09-10 | 1996-07-30 | Compaq Computer Corporation | Personal computer with CMOS memory not having a separate battery |
US6269443B1 (en) * | 1998-12-29 | 2001-07-31 | Intel Corporation | Method and apparatus for automatically selecting CPU clock frequency multiplier |
FR2868563A1 (fr) * | 2004-03-30 | 2005-10-07 | Giga Byte Tech Co Ltd | Dispositif et procede capables de detecter un etat du bois en vue de regler une horloge |
US20050268139A1 (en) * | 2004-05-28 | 2005-12-01 | Asustek Computer Inc. | Main-board and control method thereof |
Also Published As
Publication number | Publication date |
---|---|
FR2904129B1 (fr) | 2008-09-26 |
US7941583B2 (en) | 2011-05-10 |
US20090327569A1 (en) | 2009-12-31 |
FR2904129A1 (fr) | 2008-01-25 |
CA2658634A1 (fr) | 2008-01-24 |
GB2454379A (en) | 2009-05-06 |
GB2454379A9 (en) | 2010-12-01 |
EP2049967A2 (fr) | 2009-04-22 |
GB0901092D0 (en) | 2009-03-11 |
WO2008009609A3 (fr) | 2008-03-27 |
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