WO2008005622A8 - Methods and systems for placement and routing - Google Patents

Methods and systems for placement and routing Download PDF

Info

Publication number
WO2008005622A8
WO2008005622A8 PCT/US2007/069214 US2007069214W WO2008005622A8 WO 2008005622 A8 WO2008005622 A8 WO 2008005622A8 US 2007069214 W US2007069214 W US 2007069214W WO 2008005622 A8 WO2008005622 A8 WO 2008005622A8
Authority
WO
WIPO (PCT)
Prior art keywords
routing
placement
systems
methods
Prior art date
Application number
PCT/US2007/069214
Other languages
French (fr)
Other versions
WO2008005622A2 (en
Inventor
Subhasis Bose
Original Assignee
Lightspeed Logic Inc
Subhasis Bose
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from PCT/US2006/025294 external-priority patent/WO2007002799A1/en
Application filed by Lightspeed Logic Inc, Subhasis Bose filed Critical Lightspeed Logic Inc
Priority to US12/301,456 priority Critical patent/US8332793B2/en
Priority to PCT/US2007/071050 priority patent/WO2007146966A2/en
Priority to PCT/US2007/071262 priority patent/WO2007147084A2/en
Priority to PCT/US2007/071406 priority patent/WO2007147150A2/en
Priority to US11/967,184 priority patent/US7921392B2/en
Priority to US11/967,180 priority patent/US7752588B2/en
Priority to US11/967,179 priority patent/US7814451B2/en
Priority to US11/967,185 priority patent/US7921393B2/en
Publication of WO2008005622A2 publication Critical patent/WO2008005622A2/en
Publication of WO2008005622A8 publication Critical patent/WO2008005622A8/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/3312—Timing analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00—Details relating to the type of the circuit
    • G06F2115/06—Structured ASICs

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
PCT/US2007/069214 2005-06-29 2007-05-18 Methods and systems for placement and routing WO2008005622A2 (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
US12/301,456 US8332793B2 (en) 2006-05-18 2007-05-18 Methods and systems for placement and routing
PCT/US2007/071050 WO2007146966A2 (en) 2006-06-12 2007-06-12 Methods and systems for placement
PCT/US2007/071262 WO2007147084A2 (en) 2006-06-14 2007-06-14 Generalized clock tree synthesis
PCT/US2007/071406 WO2007147150A2 (en) 2006-06-15 2007-06-15 Simultaneous dynamical integration applied to detailed placement
US11/967,184 US7921392B2 (en) 2005-06-29 2007-12-29 Node spreading via artificial density enhancement to reduce routing congestion
US11/967,180 US7752588B2 (en) 2005-06-29 2007-12-29 Timing driven force directed placement flow
US11/967,179 US7814451B2 (en) 2005-06-29 2007-12-29 Incremental relative slack timing force model
US11/967,185 US7921393B2 (en) 2005-06-29 2007-12-29 Tunneling as a boundary congestion relief mechanism

Applications Claiming Priority (16)

Application Number Priority Date Filing Date Title
US74765106P 2006-05-18 2006-05-18
US60/747,651 2006-05-18
US80303206P 2006-05-24 2006-05-24
US60/803,032 2006-05-24
US80444806P 2006-06-12 2006-06-12
US60/804,448 2006-06-12
US80464306P 2006-06-13 2006-06-13
US80457406P 2006-06-13 2006-06-13
US60/804,574 2006-06-13
US60/804,643 2006-06-13
US80469006P 2006-06-14 2006-06-14
US60/804,690 2006-06-14
US80482606P 2006-06-15 2006-06-15
US60/804,826 2006-06-15
USPCT/US2006/025294 2006-06-28
PCT/US2006/025294 WO2007002799A1 (en) 2005-06-29 2006-06-28 Methods and systems for placement

Related Parent Applications (3)

Application Number Title Priority Date Filing Date
PCT/US2006/025294 Continuation WO2007002799A1 (en) 2005-06-29 2006-06-28 Methods and systems for placement
PCT/US2007/070814 Continuation WO2007149717A2 (en) 2005-06-29 2007-06-08 Morphing for global placement using integer linear programming
PCT/US2007/071050 Continuation WO2007146966A2 (en) 2005-06-29 2007-06-12 Methods and systems for placement

Related Child Applications (3)

Application Number Title Priority Date Filing Date
PCT/US2006/025294 Continuation WO2007002799A1 (en) 2005-06-29 2006-06-28 Methods and systems for placement
PCT/US2007/070814 Continuation WO2007149717A2 (en) 2005-06-29 2007-06-08 Morphing for global placement using integer linear programming
PCT/US2007/071050 Continuation WO2007146966A2 (en) 2005-06-29 2007-06-12 Methods and systems for placement

Publications (2)

Publication Number Publication Date
WO2008005622A2 WO2008005622A2 (en) 2008-01-10
WO2008005622A8 true WO2008005622A8 (en) 2009-08-20

Family

ID=38895275

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/069214 WO2008005622A2 (en) 2005-06-29 2007-05-18 Methods and systems for placement and routing

Country Status (1)

Country Link
WO (1) WO2008005622A2 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1907957A4 (en) 2005-06-29 2013-03-20 Otrsotech Ltd Liability Company Methods and systems for placement
US8332793B2 (en) 2006-05-18 2012-12-11 Otrsotech, Llc Methods and systems for placement and routing
US7840927B1 (en) 2006-12-08 2010-11-23 Harold Wallace Dozier Mutable cells for use in integrated circuits
US9235673B2 (en) 2014-05-28 2016-01-12 Freescale Semiconductor, Inc. Apparatus for and a method of making a hierarchical integrated circuit design of an integrated circuit design, a computer program product and a non-transitory tangible computer readable storage medium
US9836571B2 (en) 2015-06-23 2017-12-05 International Business Machines Corporation Applying random nets credit in an efficient static timing analysis
US10558775B2 (en) 2017-12-20 2020-02-11 International Business Machines Corporation Memory element graph-based placement in integrated circuit design
US11030367B2 (en) 2019-09-11 2021-06-08 International Business Machines Corporation Out-of-context feedback hierarchical large block synthesis (HLBS) optimization

Also Published As

Publication number Publication date
WO2008005622A2 (en) 2008-01-10

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