WO2008002832A3 - Method for programming non-volatile memory using variable amplitude programming pulses - Google Patents

Method for programming non-volatile memory using variable amplitude programming pulses Download PDF

Info

Publication number
WO2008002832A3
WO2008002832A3 PCT/US2007/071859 US2007071859W WO2008002832A3 WO 2008002832 A3 WO2008002832 A3 WO 2008002832A3 US 2007071859 W US2007071859 W US 2007071859W WO 2008002832 A3 WO2008002832 A3 WO 2008002832A3
Authority
WO
WIPO (PCT)
Prior art keywords
programmed
waveform
storage elements
programming
volatile memory
Prior art date
Application number
PCT/US2007/071859
Other languages
French (fr)
Other versions
WO2008002832A2 (en
Inventor
Gerrit Jan Hemink
Original Assignee
Sandisk Corp
Gerrit Jan Hemink
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/426,475 external-priority patent/US20070297247A1/en
Application filed by Sandisk Corp, Gerrit Jan Hemink filed Critical Sandisk Corp
Publication of WO2008002832A2 publication Critical patent/WO2008002832A2/en
Publication of WO2008002832A3 publication Critical patent/WO2008002832A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/562—Multilevel memory programming aspects
    • G11C2211/5621—Multilevel programming verification

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)

Abstract

Non-volatile storage elements are programmed using a series of voltage waveforms, where each waveform includes different portions with different amplitudes. For example, the amplitudes can vary as a decreasing staircase or ramp. Storage elements which are to be programmed to the highest level are programmed using the entire waveform, while storage elements which are to be programmed to intermediate and lower levels are programmed using different portions of the waveform. For example, the storage elements to be programmed to the intermediate level are programmed using the last two-thirds of each waveform, while the storage elements to be programmed to the lower level are programmed using the last one-third of each waveform. For these storage elements, programming is inhibited for a portion of the waveform by applying an inhibit voltage to an associated bit line. Higher programming speeds and narrower threshold voltage distributions can be achieved.
PCT/US2007/071859 2006-06-26 2007-06-22 Method for programming non-volatile memory using variable amplitude programming pulses WO2008002832A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US42648706A 2006-06-26 2006-06-26
US11/426,475 2006-06-26
US11/426,487 2006-06-26
US11/426,475 US20070297247A1 (en) 2006-06-26 2006-06-26 Method for programming non-volatile memory using variable amplitude programming pulses

Publications (2)

Publication Number Publication Date
WO2008002832A2 WO2008002832A2 (en) 2008-01-03
WO2008002832A3 true WO2008002832A3 (en) 2008-02-28

Family

ID=38740276

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/071859 WO2008002832A2 (en) 2006-06-26 2007-06-22 Method for programming non-volatile memory using variable amplitude programming pulses

Country Status (2)

Country Link
TW (1) TW200807421A (en)
WO (1) WO2008002832A2 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7643348B2 (en) 2007-04-10 2010-01-05 Sandisk Corporation Predictive programming in non-volatile memory
US7826271B2 (en) 2008-06-12 2010-11-02 Sandisk Corporation Nonvolatile memory with index programming and reduced verify
US7813172B2 (en) 2008-06-12 2010-10-12 Sandisk Corporation Nonvolatile memory with correlated multiple pass programming
US7796435B2 (en) 2008-06-12 2010-09-14 Sandisk Corporation Method for correlated multiple pass programming in nonvolatile memory
US7800945B2 (en) 2008-06-12 2010-09-21 Sandisk Corporation Method for index programming and reduced verify in nonvolatile memory
US7715235B2 (en) 2008-08-25 2010-05-11 Sandisk Corporation Non-volatile memory and method for ramp-down programming
JP2011040135A (en) 2009-08-13 2011-02-24 Toshiba Corp Nonvolatile semiconductor memory device
US8526233B2 (en) 2011-05-23 2013-09-03 Sandisk Technologies Inc. Ramping pass voltage to enhance channel boost in memory device, with optional temperature compensation
FR3039921B1 (en) * 2015-08-06 2018-02-16 Stmicroelectronics (Rousset) Sas METHOD AND SYSTEM FOR CONTROLLING A DATA WRITE OPERATION IN A MEMORY CELL OF THE EEPROM TYPE

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6243290B1 (en) * 1999-08-31 2001-06-05 Hitachi, Ltd. Nonvolatile semiconductor memory device
US6282119B1 (en) * 2000-06-02 2001-08-28 Winbond Electronics Corporation Mixed program and sense architecture using dual-step voltage scheme in multi-level data storage in flash memories
WO2002063630A1 (en) * 2001-02-08 2002-08-15 Advanced Micro Devices, Inc. Programming method using voltage pulse with stepped portions for multi-level cell flash memories
US6538923B1 (en) * 2001-02-26 2003-03-25 Advanced Micro Devices, Inc. Staircase program verify for multi-level cell flash memory designs
US20040190337A1 (en) * 2001-09-17 2004-09-30 Jian Chen Selective operation of a multi-state non-volatile memory system in a binary mode
US20050083735A1 (en) * 2003-10-20 2005-04-21 Jian Chen Behavior based programming of non-volatile memory

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6243290B1 (en) * 1999-08-31 2001-06-05 Hitachi, Ltd. Nonvolatile semiconductor memory device
US6282119B1 (en) * 2000-06-02 2001-08-28 Winbond Electronics Corporation Mixed program and sense architecture using dual-step voltage scheme in multi-level data storage in flash memories
WO2002063630A1 (en) * 2001-02-08 2002-08-15 Advanced Micro Devices, Inc. Programming method using voltage pulse with stepped portions for multi-level cell flash memories
US6538923B1 (en) * 2001-02-26 2003-03-25 Advanced Micro Devices, Inc. Staircase program verify for multi-level cell flash memory designs
US20040190337A1 (en) * 2001-09-17 2004-09-30 Jian Chen Selective operation of a multi-state non-volatile memory system in a binary mode
US20050083735A1 (en) * 2003-10-20 2005-04-21 Jian Chen Behavior based programming of non-volatile memory

Also Published As

Publication number Publication date
TW200807421A (en) 2008-02-01
WO2008002832A2 (en) 2008-01-03

Similar Documents

Publication Publication Date Title
WO2008002832A3 (en) Method for programming non-volatile memory using variable amplitude programming pulses
ATE492883T1 (en) PROGRAMMING A NON-VOLATILE MEMORY
ATE422701T1 (en) SELECTIVE SLOW PROGRAMMABLE CONVERGENCE IN A FLASH MEMORY DEVICE
ATE521972T1 (en) PROGRAMMING A NON-VOLATILE MEMORY WITH SELF-REGULATING MAXIMUM PROGRAM LOOP
WO2009009076A3 (en) Error correction for memory
WO2008033693A3 (en) Non-volatile memory and method for linear estimation of initial programming voltage
WO2008157037A3 (en) Coarse and fine programming in a solid state memory
WO2009111158A3 (en) Charge loss compensation during programming of a memory device
ATE496373T1 (en) PROGRAMMING METHOD BASED ON THE BEHAVIOR OF NON-VOLATILE MEMORY CELLS
WO2011037703A3 (en) Methods of reading and using memory cells
ATE518229T1 (en) METHOD FOR PROGRAMMING A MULTI-STATE NON-VOLATILE MEMORY USING INTELLIGENT VERIFICATION
EP2487688A3 (en) Erase ramp pulse width control for non-volatile memory
WO2010045481A3 (en) Methods, devices and systems for programming neurostimulation
DE602005025323D1 (en) A method of programming phase-change memory cells with multiple memory levels using a percolation algorithm
WO2010117807A3 (en) Two pass erase for non-volatile storage
JP2012142067A5 (en)
WO2007076512A3 (en) Methods and device for improved program-verify operations in non-volatile memories
ATE382183T1 (en) NON-VOLATILE MEMORY SYSTEM WITH PROGRAM TIME CONTROL
WO2005067901A3 (en) Methods for treating and preventing hypertension and hypertension-related disorders
WO2008057822A3 (en) Nonvolatile memory with variable read threshold
TWI410973B (en) Memory device program window adjustment
WO2006122148A3 (en) Neural stimulation system controlling autonomic balance
WO2009037691A3 (en) Programming orders for reducing distortion in arrays of multi-level analog memory cells
WO2006029257A3 (en) Neurostimulation methods and systems
WO2009152037A3 (en) Nonvolatile memory and method for correlated multiple pass programming

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07798919

Country of ref document: EP

Kind code of ref document: A2

NENP Non-entry into the national phase

Ref country code: DE

NENP Non-entry into the national phase

Ref country code: RU

122 Ep: pct application non-entry in european phase

Ref document number: 07798919

Country of ref document: EP

Kind code of ref document: A2