WO2007148401A1

WO2007148401A1 - Rectification circuit and radio communication device using the same

Info

Publication number: WO2007148401A1
Application number: PCT/JP2006/312530
Authority: WO
Inventors: Takashi Ogawa; Kumiko Takikawa; Satoshi Tanaka; Takashi Oshima; Minoru Ashizawa
Original assignee: Hitachi, Ltd.
Priority date: 2006-06-22
Filing date: 2006-06-22
Publication date: 2007-12-27
Also published as: JPWO2007148401A1

Abstract

When a demodulation circuit is connected in parallel to the input of a radio tag multi-stage rectification circuit, the rectification circuit is affected by the impedance of the demodulation circuit to increase the minimum input power for generating a predetermined power voltage and the communication distance between a radio tag and a reader/writer device is shortened. In order to solve this problem, the demodulation circuit is connected at an intermediate stage of the multi-stage rectification circuit so as to reduce the affect of the impedance of the demodulation circuit and enable generation of a predetermined power supply voltage even if the communication distance between the radio tag and the reader/writer device is large and the input power to the radio tag is small.

Description

Specification

Rectifier circuit and wireless communication device using the same

Technical field

TECHNICAL FIELD [0001] The present invention relates to a rectifier circuit and a wireless communication device using the same, and more particularly to a wireless tag circuit of a wireless communication system that performs non-contact data communication.

Background art

As an example of a wireless tag circuit of a wireless communication system that performs non-contact data communication, for example, the one shown in Patent Document 1 is known. This RFID circuit includes an antenna, a rectifier circuit, a modulation circuit, a node, a bypass filter, a regulator, a demodulation circuit, a sequencer, and a memory. Among these, the rectifier circuit rectifies the AC voltage generated by electromagnetically inductively coupling the antenna coil of the RFID tag inside the reader / writer with a diode, converts it to DC, and stores the electric charge in a capacitor.

Further, a configuration example of a wireless tag different from such a circuit is shown in Non-Patent Document 1. The RFID tag shown in Fig. 1 is ant (antenna), demodulator (demodulator), volute ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ (voltage multiplier; The voltage multiplier also converts the AC voltage generated by electromagnetically inductively coupling the antenna with the antenna inside the reader / writer to DC, and the demodulator, Supplying power supply voltage to the modulator and control logic The demodulator demodulates the pulse width modulation signal (PWM: £ ulse-Width Modulation) input from the antenna into a clock and signal (command, data) and outputs it to the control logic The control logic analyzes the demodulator signal (command) and Then, the data stored in the IIPM is read and written to the IIPM, and the control logic generates the data required for the signal (command) and supplies it to the module. The charge pump modulates the impedance of the antenna in response to the signal from the control logic, and the charge pump uses the voltage multiplier as the control voltage required to write the power supply. Boost to.

[0004] Patent Document 1: JP-A-2005-92352

Non-Patent Document 1: "Fully Integrated Passive UHF RFID Transponder IC With 16.7- W Minimum RF Input Power", IEEE Journal of Solid—State Circuits, vol. 38, No. 10, Oct. 2003

Disclosure of the invention

Problems to be solved by the invention

[0005] In recent years, non-contact IC cards, wireless tags (collectively referred to as wireless tags), etc. for automatic ticket gates, entrance / exit management of buildings and rooms, entrance management for exhibitions, collection management of luggage, etc. Wireless data communication systems that perform non-contact data communication using electromagnetic induction are beginning to spread. This system consists of a wireless tag and a reader / writer device that is arranged in the vicinity to read and write data, and extending the communication distance between them is an issue. In addition, because it aims to manage a large number of people and things, it is required to reduce the cost and size of wireless tags.

[0006] The data communication device disclosed in Patent Document 1 is provided with means for suppressing the operation of the filter means to suppress power loss.

FIG. 16 corresponds to a circuit diagram of the non-contact type IC card shown in FIG. 5 of Patent Document 1.

The rectifier circuit 235 rectifies the AC voltage generated by the antenna coil 224 in the ANT (antenna) 223 of the wireless tag with the diode 242 and stores the electric charge in the capacitor 244. The regulator 236 supplies a stable power supply voltage to the sequencer 239 while suppressing fluctuations in the DC voltage. The demodulating circuit 238 receives the AC signal detected by the envelope detection by the diode 242 of the rectifying circuit 235, demodulates it through the high-pass filter F 237, and outputs the demodulated signal to the sequencer 239. The sequencer 239 analyzes the signal of the demodulation circuit 238, and reads or writes data stored in the memory 240 according to the result. The sequencer 239 generates the required data and supplies it to the modulation circuit 241. The modulation circuit 241 includes an impedance 247 and a F ET248 force, and the FET 248 is switched in response to a signal from the sequencer 239, and the load of the impedance 247 on the antenna coil 224 is changed to perform modulation.

[0008] In the wireless tag disclosed in Patent Document 1, the rectifier circuit 235 corresponds to the magnitude of the input amplitude. Current flows through the resistor 243, and a voltage drop occurs in the rectifier circuit 235. For this reason, the power supply output supplied from the regulator 236 connected to the subsequent stage of the rectifier circuit 235 becomes a low voltage. In addition, the low voltage lost by the rectifier circuit 235 must be input to the high-pass filter F 237 and the demodulator 238 at the subsequent stage for demodulation, resulting in unstable operation. In order to prevent this, the wireless tag and the reader / writer device must be used at a very short distance so that the electromagnetic induction necessary for the wireless tag to obtain a desired power supply voltage and signal level is performed.

On the other hand, the wireless tag of Non-Patent Document 1 has a rectifier circuit diode and capacitors connected in multiple stages as a method for ensuring a desired power supply voltage and signal level. In Fig. 2 of Non-Patent Document 1, the voltage multiplier is a voltage doubling circuit that connects diodes and capacitors in multiple stages and connects them to supply a high power supply voltage. In Fig. 4, the demodulator is provided with the same rectifier circuit as the voltage multiplier in the previous stage to detect the envelope of the received signal, and the pulse width modulation signal (PWM: £ ulse-Width Modulation) in the subsequent circuit. The demodulator is demodulated.

[0010] In the wireless tag having such a configuration, since a voltage multiplier, a demodulator, and a modulator are connected in parallel to the antenna, all the received power of the antenna is not input to the voltage multiplier and is converted into an AC-DC converter. Reduce efficiency! In other words, it is necessary to increase the minimum antenna input power when the output voltage of the voltage multiplier reaches a desired voltage for operating each internal circuit, which is one reason for reducing the communication distance between the reader / writer device and the RFID tag device. Become. In addition, the voltage multiplier and part of the demodulator have redundant configurations that use the same circuit topology, which increases the circuit scale and hinders the miniaturization and low cost of wireless tags.

[0011] The problem to be solved by the present invention is to improve the AC-DC conversion efficiency of the rectifier circuit. For example, the output of the rectifier circuit can reach a desired voltage even when the antenna input power of the radio tag is small. It is an object of the present invention to provide a rectifier circuit capable of extending the communication distance of a writer device and a wireless communication device using the rectifier circuit.

Means for solving the problem

[0012] An example of a representative one of the present invention is as follows. That is, the wireless communication of the present invention. Rectifier circuit for communication devices, antenna power A rectifier circuit for wireless communication devices that rectifies received high-frequency signals to generate a DC voltage for power supply, and has multiple stages of detector circuits connected in cascade via connection terminals And an antenna signal input first terminal provided in each stage of the detector circuit constituting the rectifier circuit, and the first stage detector circuit and the final stage detector circuit of the rectifier circuit. And a terminal for connecting the demodulator circuit and an output terminal for the DC voltage for power supply provided in the detector circuit at the final stage of the rectifier circuit.

The invention's effect

[0013] According to the present invention, since the demodulation circuit is connected to the middle stage of the rectifier circuit, the antenna received power is not distributed to the demodulator circuit, and a decrease in the antenna received power input to the rectifier circuit can be prevented. For this reason, AC-DC conversion efficiency is improved. Therefore, a sufficient power supply voltage can be maintained, and when the present invention is applied to a wireless tag, the communication distance between the wireless tag and the reader / writer device can be extended.

BEST MODE FOR CARRYING OUT THE INVENTION

First, a basic configuration example of the present invention will be described using the circuit block diagram of FIG. In FIG. 1, the rectifier circuit 20 is a multi-stage circuit in which n detection circuits (22 to 25) having the same circuit configuration power are connected in cascade to the first stage force to the Nth stage. 21 is a demodulation circuit. The terminal of the rectifier circuit 20 is commonly connected to the terminal TN2 of each detector circuit, the terminal TN3 is connected to the terminal TN1 of the subsequent detector circuit, and the first detector terminal TN1 is connected to the grounded half-wave rectifier circuit. It has a configuration. A circuit example is a half-wave rectifier circuit in which two diodes and two capacitors (CO, C1) are connected, as described in the frame of the first detection circuit (22). The DC capacitor of (2n-l) (| Vin I —VD is held in the nth stage floating capacitor CO of the detection circuit. Vin is the amplitude value of the input signal, Vf is the forward voltage drop of the diode, and is Schottky. Noria diode is about 0.3 V. Vin is added to the above DC voltage at terminal TN0, which is the component of the nth stage detection circuit, and (2n-l) (| Vin | —Vi) + Finally, the DC voltage of 2n (| Vin | —VI) is held in the capacitor C1 of the nth detection circuit, which is the output of the power supply voltage.The limiter 28 is excessive, such as antenna When voltage is input, each circuit must be protected against damage caused by overvoltage. It is provided for the purpose of suppressing the power supply voltage to a predetermined level.

[0015] This rectifier circuit 20 has a circuit configuration in which an input signal of an antenna signal is received by the rectifier circuit from the antenna terminal TN2, and the input of the demodulator circuit 21 is connected to the output terminal TNB in the middle of the rectifier circuit. The demodulator circuit 21 receives the rectified signal from the rectifier circuit 20, performs envelope detection, amplifies the signal to a predetermined signal level, and outputs a demodulated signal.

In FIG. 1, the connection point TNB force between the n-1 stage detection circuit 24 and the nth detection circuit 25 is also connected to the demodulation circuit 21, and this connection point TNB is Output terminal of the number of stages of the detection circuit between the first stage and n stage (final stage) and the obtained terminal voltage exceeds the logic threshold required for demodulation (or connection of two diodes constituting the detection circuit) Set to point TNO).

According to the configuration of the circuit block diagram of FIG. 1, the demodulation circuit is connected to the middle stage of the rectifier circuit, and the antenna reception power is not distributed to the demodulation circuit. Therefore, the rectifier circuit is not affected by the impedance of the demodulator circuit, and there is no reduction in AC-DC conversion efficiency. Therefore, a sufficient power supply voltage can be maintained, and the communication distance between the wireless tag and the reader / writer device can be extended.

Example 1

Next, an example of a more specific wireless tag circuit to which the present invention is applied will be described with reference to FIG. 2 or FIG.

First, FIG. 3 shows an example of a block circuit of a wireless tag to which the present invention is applied. The wireless tag includes an antenna 130, a rectifier circuit 131, a demodulation circuit 132, a modulation circuit 133, a limiter 134, a logic control circuit 135, and a memory 136. The thick line in the figure indicates the supply line for the power supply voltage generated by the rectifier circuit, and the others indicate the signal lines. Further, in FIG. 3, the wireless tag circuit in the region indicated by the broken line excluding the antenna is formed on a common substrate as a CMOS circuit, for example.

Here, the characteristically related parts of the present invention are a rectifier circuit 131 and a demodulator circuit 132.

The rectifier circuit 131 is a rectifier circuit 20 having a configuration in which detector circuits as shown in FIG. 1 are cascaded in multiple stages, and a demodulator circuit 132 corresponding to the demodulator circuit 21 in FIG. It is. In such a configuration, the AC voltage generated when the antenna 130 is electromagnetically coupled to the antenna of the reader / writer (not shown) is converted to DC by the rectifier circuit 131, and this DC voltage is converted to the demodulator circuit 132. , And supplied to the modulation circuit 133 and the logic control circuit 135 as a power supply voltage. In addition, the rectifier circuit 131 also outputs a rectified detection signal to the demodulation circuit 132 in the middle stage force of the multi-stage connection of the detection circuit. The demodulation circuit 132 amplifies the detection signal, demodulates it into a signal including a clock and data, and outputs the signal to the logic control circuit 135. The logic control circuit 135 analyzes the command included in the demodulated signal, and reads or writes the data stored in the memory 136 according to the result. Further, the logic control circuit 135 creates data required for the signal (command) and supplies it to the modulation circuit 133. The modulation circuit 133 performs modulation by varying the impedance with respect to the antenna 130 in response to the control signal from the logic control circuit 135. The limiter 134 is provided to suppress the power supply voltage to a predetermined level and to protect the RFID tag circuit 10 from the destructive force caused by the overvoltage even when an excessive voltage is input from the antenna 130.

FIG. 2 is a circuit diagram showing a first embodiment of the rectifier circuit 131 and the demodulator circuit 132 in the wireless tag as described above. The circuit of this embodiment shows a specific circuit configuration of the rectifier circuit 20 and the demodulator circuit 21 in the block diagram of FIG. The rectifier circuit 20 has a configuration in which the detection circuits of the first detection circuit 23, the second detection circuit 24, and the third detection circuit 25 are connected in three stages in cascade. Each detection circuit has the same circuit configuration. Since the signal input from the antenna to terminal TN2 has a modulated signal, the signal difference between when there is a signal and when there is no signal is large. For this reason, the capacitor C3 has a larger capacitance value than the capacitors Cl and C2 in order to suppress fluctuations in the power supply voltage when there is no signal.

[0023] Fig. 4 conceptually shows the state of boosting by the capacitors (Cl, C2, C3) of each detection circuit when there is a signal. As shown in Fig. 4, the DC voltage boosted to Vcl = 2 (I Vinl-Vf) is held by the capacitor C1 at the terminal TN3 of the first detection circuit 23, and the terminal of the second detection circuit 24 In TN3, the DC voltage boosted to Vc2 = 4 (| Vin | -Vf) is held by the capacitor C2, and in the terminal TN3 of the third detection circuit 25, Vc3 = 6 (| Vin | -Vf) The boosted DC voltage is held by capacitor C3.

[0024] AC power generated by electromagnetically inductively coupling the antenna 130 to the reader / writer antenna. The pressure is rectified by the diodes (D2, D4, D6) of each detector circuit and converted to direct current, and the charge is stored in capacitors (Cl, C2, C3) connected to the terminal TN3 of each detector circuit. The AC voltage is a modulated signal and has a wide amplitude. When the amplitude of the AC voltage is large, the capacitor (Cl, C2, C3) is charged and boosted.

[0025] On the other hand, when the amplitude force S is small, the diodes D1, D2, D3, D4, D5, and D6 do not operate, and the diodes are turned off and no rectification operation is performed by the diodes. The capacitors Cl, C2, and C3 are charged. Discharge the charged charge. At this time, the capacitor C3 has a large capacitance value V, so it takes a long time to discharge. Capacitor C1 also has a high load impedance as seen from capacitor C1 because diode D3 etc. are off. Capacitor C2 has a low load impedance due to resistor 26 and amplifier 27, and so discharges faster than capacitors Cl and C3, and a signal faithful to the modulation signal is input to demodulation circuit 27. This enables faithful demodulation while maintaining a stable power supply voltage for the modulation signal. Since only the rectifier circuit 20 is connected to the antenna terminal, a high power supply voltage can be obtained because the load impedance is higher than that of a conventional circuit configuration in which multiple circuits are connected to the antenna terminal. Reduces power consumption.

[0026] Thus, according to the present embodiment, the voltage boosted by each detection circuit is held without being substantially affected by the demodulation circuit, and a stable high power supply voltage Vdd is held. That is, the rectifier circuit 20 holds a DC voltage Vdd of 6 (I Vin | -Vf), for example, a stable voltage of 1.6 V, at the final output terminal TN3. The rectifier circuit 133, the demodulator circuit 132, the modulator circuit 133, the logic control circuit 135, and the like shown in FIG.

On the other hand, the power sword of the diode D4 that is the second-stage output of the rectifier circuit 20, in other words, the terminal TN3 of the second detection circuit 24 is connected to the terminal TM1 of the demodulation circuit 21. The demodulator circuit 21 is composed of a resistor 26 and a limiter amplifier 27, and charges the capacitor C2 with the voltage level Vc2 of the received signal, discharges it, and detects the envelope by rectifying the detector circuit. Provided. The voltage level Vc2 '(= Vc2) input to the demodulator circuit 21 is a force that makes the voltage lower than the DC voltage Vdd.If this Vc2' exceeds the logic threshold required for demodulation, there is no problem with the demodulation operation. There is no. Detected The envelope is amplified by the amplifier 27 of the demodulation circuit 21 and demodulated as a signal of a desired level. As described above, the limiter 28 is provided for protecting each circuit.

Here, the rectifier circuit 20 has a three-stage configuration, but the actual number of stages is determined by the required power supply voltage and the allowable circuit scale. The number of detector circuits connected to the demodulator circuit is selected so that it exceeds the logic threshold required for demodulation and lower than the final stage. In this example, if the power logic threshold level connected to the output of the detection circuit 24, which is the second stage, is exceeded, even if it is connected to the output terminal TN3 of the first stage, it does not matter.

FIG. 5 shows an example of the result of analyzing the power supply voltage and the demodulation operation by the circuit of FIG. In Fig. 5, (A) is an antenna input, and (B) is an enlarged view of the antenna input (A). (C) shows the output voltage of the final stage of the rectifier circuit, which is the power supply voltage, and (D) shows the output signal of the demodulator circuit.

[0030] As a condition for analysis, as shown in FIG. 5B, an ASK modulation signal that is low level with a width of several μsec in a period of several tens of μsec for a high-frequency signal of 2 GHz operating frequency band. The waveform of the power supply voltage Vdd at the VDD terminal, which was input to the antenna and converted into a DC signal, and the waveform at the output terminal of the demodulator circuit were graphed. As shown in (C), the high-frequency signal is rectified and the DC power supply voltage Vdd is output. Although the power supply voltage Vdd slightly fluctuates (decreases) during the period when the antenna input becomes low level, the fluctuation of the power supply voltage Vdd is very small compared to the absolute value of the power supply voltage Vdd. Can do. Also, as shown in (D), the low level is detected every several tens of microseconds for several microseconds, and the high level is detected for other periods, demodulated according to the input signal, and the clock signal is also extracted accurately. The child is understood.

[0031] According to the present embodiment, the demodulator circuit 21 is connected to the middle stage of the rectifier circuit 20, so that the load impedance to the antenna can be increased, and the reduction of the antenna received power input to the rectifier circuit can be prevented. For this reason, AC-DC conversion efficiency is improved. Therefore, a sufficient power supply voltage can be maintained for the circuit 10 of the wireless tag, the output of the rectifier circuit can reach the desired voltage even when the antenna input power is small, and the communication distance between the wireless tag and the reader / writer device can be extended. .

[0032] According to the present embodiment, the rectification action necessary for the demodulation envelope detection is further performed by the rectifier circuit. Therefore, it is possible to share a part of the rectifier circuit and the demodulator circuit, which is effective in reducing the circuit size and cost.

Example 2

[0033] Next, a second embodiment of the present invention will be described with reference to Figs. First, the concept of the second embodiment will be described with reference to FIG. In contrast to the block diagram shown in Fig. 1, a demodulating detector circuit 42 is provided in front of the demodulating circuit 43 to hold the DC voltage of the demodulating circuit, and the connection point is the connecting point of the two diodes of the detecting circuit (internal Terminal) What is taken from TNO is different. With this configuration, the capacitor C3 of the detection circuit n-1 (40) can hold the voltage boosted by each detection circuit without being affected by the demodulation circuit 43 and supply the DC voltage Vdd. . In Fig. 6, the power of the n-1 stage detector circuit and the power connected to the demodulator circuit should be selected so that they exceed the logical threshold required for demodulation. However, if a high-stage detector circuit is connected to the demodulator circuit (for example, the n-th stage), when a voltage with a high antenna force is input, the overvoltage boosted by the multi-stage detector circuit is applied to the demodulator circuit. It is better to avoid it as it may destroy the circuit. The limiter 46 is provided for protecting each circuit as described above.

FIG. 7 shows an example of a specific circuit configuration of the block diagram shown in FIG. The circuit configuration of the rectifier circuit 20 is the same three-stage cascade connection as the circuit configuration shown in FIG. 2, and a demodulating detector circuit 42 is newly provided between the rectifier circuit 20 and the demodulator circuit 43. Connection point (internal terminal) of diodes D3 and D4 in one-stage detection circuit 40 Connect to detection circuit 42 for demodulation from TNO. The demodulating detection circuit 42 includes a diode 44 and a capacitor 45, which detects with the diode 44 and holds the DC voltage input to the demodulation circuit 43 with the capacitor 45. The demodulator circuit 43 has the same configuration as the demodulator circuit 21 described in FIG. 2, and performs the same demodulation operation. The limiter 46 is provided for protecting each circuit as described above.

Also in this embodiment, the demodulator circuit 43 is connected to the intermediate stage of the rectifier circuit 20 via the demodulator detection circuit 42, so that the load impedance to the antenna can be increased, and the antenna received power input to the rectifier circuit can be increased. Decrease can be prevented. Further, a stable DC voltage Vdd can be supplied without being affected by the demodulation circuit 43.

[0036] According to the present embodiment, since the rectification required for the envelope detection of demodulation is performed by the rectifier circuit, it is possible to share a part of the rectifier circuit and the demodulator circuit, thereby reducing the size of the circuit. , Effective for cost reduction.

Example 3

Next, a third embodiment of the present invention will be described with reference to FIGS. First, the concept of the third embodiment will be described with reference to FIG. 1 differs from the block diagram shown in FIG. 1 in that a demodulating detector circuit 62 is provided in front of the demodulating circuit 63 and an antenna input signal is input to the demodulating detector circuit 62. By capturing the antenna input signal with this configuration, the detection voltage level for demodulation can be kept high. In Fig. 8, the n-1 stage detector circuit is also connected to the demodulator circuit, but the connection point should be selected so that the number of detector circuit stages connected to the demodulator circuit exceeds the logic threshold required for demodulation. . However, if a high-stage detector circuit is connected to the demodulator circuit (for example, the n-th stage), when a voltage with a high antenna force is input, the overvoltage boosted by the multi-stage detector circuit is applied to the demodulator circuit. It is better to avoid it as it may destroy the circuit. The limiter 68 is provided for protecting each circuit as described above.

FIG. 9 shows an example of a specific circuit configuration of the block diagram shown in FIG. A demodulation circuit 62 is newly provided between the rectifier circuit 20 and the demodulation circuit 63, and the demodulation detection circuit 62 is connected to the connection point TN3 of the diodes D4 and D5 of the n-1 stage detection circuit 60 of the rectification circuit 20. .

That is, in each detection circuit 60 constituting the rectifier circuit 20, one end of the first capacitor CO is connected to the transmission / reception antenna terminal TN2 to serve as an input terminal for the high-frequency signal Vin. The terminal is connected to the power sword of the first diode D3 and the anode of the second diode D4 at the connection point TN0, and the anode of the first diode D3 becomes the input terminal of the detection circuit, and the force of the second diode D4 The sword is connected to one end of the second capacitor C2 and serves as the output terminal TN3 of the detection circuit, and the other terminal of the second capacitor C2 is grounded.

The demodulating detection circuit 62 is composed of diodes 64 and 65 and capacitors 66 and 67. The detection is performed by the diodes 64 and 65, and the DC voltage input to the demodulation circuit is held by the capacitor 67. In other words, the demodulating detector circuit 62 connected to the intermediate stage of the multistage detecting circuit is composed of two diodes 64 and 65 and two capacitors 66 and 67, and the first diode 64 node is Connected to the output terminal TN3 of the detector circuit in the middle stage, the force sword is connected to the second die. Connected to the anode of Ode 65 and the first terminal of first capacitor 66. The second terminal of the first capacitor is connected to the transmitting / receiving antenna end terminal TN2, the force sword of the second diode 65 is connected to the first terminal of the second capacitor 67, and the second terminal of the second capacitor The terminal is grounded.

In addition, the demodulation circuit 63 has the same configuration as the demodulation circuit 21 described in FIG. 2, and performs the same demodulation operation. That is, the demodulation circuit 63 also has an amplifier power to amplify the signal detected by the resistor and the rectifier circuit, and is connected to the first terminal of the second capacitor 67 of the demodulation detection circuit 62 different from the detection circuit 20 connected in multiple stages. One terminal of the resistor and the input terminal of the amplifier are connected, and the other terminal of the resistor and the other terminal of the amplifier are grounded. The limiter 68 is provided for protecting each circuit as described above.

[0042] According to the present embodiment, the demodulation circuit 63 is connected to the intermediate stage of the rectifier circuit 20 via the demodulation detector circuit 62, so that the load impedance to the antenna can be increased, and the antenna reception input to the rectifier circuit can be achieved. A reduction in power can be prevented. In addition, the detection voltage level for demodulation can be kept high by taking the antenna input signal into the demodulation circuit 62 for demodulation.

Example 4

[0043] Next, a fourth embodiment of the present invention will be described with reference to Figs. First, Fig. 10 shows the concept of the fourth embodiment. The block diagram shown in FIG. 1 has a configuration with half-wave rectification detection circuit power and supplies a positive voltage, but in the fourth embodiment, the configuration also has full-wave rectification circuit power with positive and negative voltages. Can supply different. In FIG. 10, the detection circuit 71 in the first detection circuit unit 81 has the same configuration as the detection circuit 1 in FIG. 1, and the current flows through the diode and the capacitor C71 when the antenna force has a positive amplitude of the input high-frequency signal. Is charged with a positive charge. On the other hand, when the detection circuit 72 has a negative amplitude, a current flows through the diode and charges the capacitor C73 with a negative charge.

[0044] By connecting such detection circuit units in multiple stages (81, 83 to 84), the charge charge increases, and the floating capacitor C72 of the nth detection circuit n has (2n-l) (| Vin | — Vf) is held, and another floating capacitor C74 holds-(2n-l) (| V in I —VI). Terminal TN of the detection circuit n, which is the output point of the power supply voltage In 4, the DC voltage of 2n (| Vin | — Vl) and -2n (| Vin | —VI) is held at terminal TN5 and supplied to each circuit.

[0045] An intermediate stage of the rectifier circuit 80 having such a configuration power is connected to the demodulator circuit 82. The demodulation circuit 82 inputs the signal rectified by the rectifier circuit 80 and performs envelope detection, and then amplifies the signal to a predetermined signal level and outputs a demodulated signal. In the example of Fig. 10, the n-1 stage detector circuit is also connected to the demodulator, but the connection point is not limited to this. In other words, the number of detection circuit stages connected to the demodulation circuit may be selected so as to exceed the logic threshold necessary for demodulation. The limiter 87 is provided for protecting each circuit as described above.

Next, FIG. 11 shows a specific circuit example of the block diagram shown in FIG. Here, the rectifier circuit is configured as a cascade connection of two stages, and portions 83 and 84 indicated by broken lines are the first-stage detection circuit and the final-stage detection circuit 84.

That is, in the first-stage detection circuit 83, one terminal of the first capacitor C72 is connected to the first terminal TN3 of the transmission / reception antenna to serve as an input terminal for the high-frequency signal Vin. The other terminal TN10 is connected to the power sword of the first diode D1 and the anode of the second diode D2, and the anode of the first diode D1 becomes the positive input terminal of the detection circuit, and the power of the second diode D2 The sword is connected to one terminal of the second capacitor C71 and becomes the positive output terminal TN4 of the parenthesis detection circuit, and the other terminal of the second capacitor C71 is grounded (TNI, TN2). Also, one terminal of the third capacitor C74 is connected to the second terminal of the antenna to become the input terminal TN3 of the high frequency signal Vin, and the other terminal of the third capacitor C74 is connected to the power sword of the third diode D6 and the second sword. The anode of the fourth diode D5 is connected, and the anode of the third diode D6 is the negative input terminal TN5 of this detection circuit, and is further connected to one terminal of the fourth capacitor C73. The negative output terminal of the circuit, and the other terminal of the fourth capacitor C73 is grounded.

[0048] As described above, the rectifier circuit 80 holds the DC voltage of 2 (| Vin | -Vf) with the capacitor C71 and the DC voltage of -2 (I Vinl-Vf) with the capacitor C73. Supply voltage is supplied to the circuit. The output of the first stage of the rectifier circuit 80 is input to the demodulator circuit 82. The demodulator circuit 82 is composed of a resistor 85 and a limiter amplifier 86, and depends on the voltage level of the received modulation signal. The charge of capacitors C71 and C73 is charged and discharged, and the rectifying power of rectifier circuit 80 is also provided to detect the envelope. The detected envelope is amplified by the limiter amplifier 86 of the demodulation circuit 82 and demodulated as a signal of a desired level. The limiter 87 is provided for protecting each circuit as described above.

[0049] The actual number of rectifier circuits is determined by the required power supply voltage, the allowable circuit scale and cost. The number of stages of the detection circuit to which the demodulation circuit is connected exceeds the logical threshold necessary for demodulation and is lower than the final stage. Select the number of stages.

[0050] The full-wave rectifier circuit system of the present embodiment also has the same effect as the embodiment described above. Embodiment 5

Next, a fifth embodiment of the present invention will be described with reference to FIGS. First, the concept of the fifth embodiment will be described with reference to FIG. In this embodiment, in contrast to the block diagram of the fourth embodiment shown in FIG. 10, a demodulating detector circuit 102 for holding the DC voltage of the demodulating circuit is provided in front of the demodulating circuit 103, and its connection is made. The difference is that the point is taken from the connection point TN11 of the two diodes of the detection circuit.

[0052] With this configuration, the capacitor C71 of the detection circuit n-1 can hold the voltage boosted by each detection circuit without being affected by the demodulation circuit and supply the power supply voltage. In Fig. 12, the detection circuit power at the n-1 stage is also connected to the demodulation circuit, but the connection point should be selected so that the number of detection circuit stages to which the demodulation circuit is connected exceeds the logic threshold required for demodulation. However, if a high-level detector circuit is connected to the demodulator circuit (for example, the n-th stage), when an antenna high voltage is input, the overvoltage boosted by the multi-stage detector circuit is applied to the demodulator circuit. It is better to avoid it as it can be destroyed. A limiter is provided to protect each circuit as described above.

FIG. 13 shows an example of a specific circuit configuration of the block diagram shown in FIG. The circuit configuration of the rectifier circuit 101 is the same two-stage cascade connection as the circuit configuration shown in FIG. 11. A demodulating detector circuit 102 is newly provided between the rectifier circuit 101 and the demodulator circuit 103, and the rectifier circuit 101 has a diode configuration. The connection point force between the nodes D1 and D2 is also connected to the detection circuit 102 for demodulation.

That is, in the detection circuit 101, one terminal of the first capacitor C72 is connected to the transmission / reception amplifier. Connected to the first terminal TN3 of the tenor and becomes the input terminal for the high frequency signal Vin, and the other terminal TN11 of the first capacitor C72 is connected to the power sword of the first diode D3 and the anode of the second diode D4 The anode of the first diode D3 becomes the positive input terminal of the detection circuit, the force sword of the second diode D4 is connected to one terminal of the second capacitor C71, and the positive output of the parenthesis detection circuit Terminal TN4, the other terminal of the second capacitor C71 is grounded (TNI, TN2). Also, one terminal of the third capacitor C74 is connected to the second terminal of the antenna to become the input terminal TN3 of the high frequency signal Vin, and the other terminal of the third capacitor C74 is the power sword of the third diode D8. Is connected to the anode of the fourth diode D7, the anode of the third diode D8 is the negative input terminal T N5 of the detection circuit, and the power sword of the fourth diode D7 is the fourth capacitor C73. It is connected to one terminal and becomes the negative output terminal of the detection circuit, and the other terminal of the fourth capacitor is grounded.

[0055] The demodulation detection circuit 102 includes a diode 104 and a capacitor 105. The detection is performed by the diode 104, and the capacitor 105 holds a DC voltage input to the demodulation circuit. The connection terminal TN10 of the first diode D1 and the second diode D2 of the detection circuit in the middle stage is connected to the anode of the diode 104 of the demodulation circuit for demodulation provided separately from the detection circuit connected in multiple stages. The force sword is connected to the first terminal of the capacitor C105, and the second terminal of the capacitor is connected to the negative terminal. The demodulator circuit 103 is an amplifier circuit that amplifies the signal detected by the resistor and the rectifier circuit. One terminal of the resistor and the input terminal of the amplifier are connected to the positive output terminal of the detector circuit, and the other resistor is connected. The terminal and the other terminal of the amplifier are connected to the negative terminal of the detection circuit.

The demodulation circuit 103 performs the same demodulation operation as the demodulation circuit 82 described in FIG. The limiter 106 is provided for protecting each circuit as described above.

[0057] The full-wave rectifier circuit system of the present embodiment also has the same effect as the previously described embodiment. Embodiment 6

Next, a sixth embodiment of the present invention will be described with reference to FIGS. First, the concept of the sixth embodiment will be described with reference to FIG. The sixth embodiment is different from the block diagram of the fourth embodiment shown in FIG. However, the demodulating circuit 123 is provided with a demodulating detection circuit 122, and an antenna input signal is input to the demodulating detecting circuit 122. By capturing the antenna input signal with this configuration, the detection voltage level for demodulation can be kept high. In Fig. 14, the detection circuit power at the n-1 stage is also connected to the demodulation circuit, but the connection point should be selected so that the number of detection circuit stages connected to the demodulation circuit exceeds the logic threshold required for demodulation. However, if a high-level detector circuit (for example, the n-th stage) is connected to the demodulator circuit, if a high voltage is input from the antenna, the overvoltage boosted by the multi-stage detector circuit is applied to the demodulator circuit. It is better to avoid it because it may destroy it. The limiter is provided to protect each circuit as described above.

FIG. 15 shows an example of a specific circuit configuration of the block diagram shown in FIG. A demodulation circuit 122 is newly provided between the rectification circuit 121 and the demodulation circuit 123, and the demodulation detection circuit 122 is connected from the connection point between the diodes D2 and D3 of the rectification circuit 121.

That is, in the rectifier circuit 110, one terminal of the first capacitor C72 is connected to the first terminal TN3 of the transmission / reception antenna to serve as an input terminal for the high-frequency signal Vin, and the other terminal of the first capacitor C72. TN 11 is connected to the power sword of the first diode D3 and the anode of the second diode D4, the anode of the first diode D3 is the positive input terminal of the detector circuit, and the power sword of the second diode D4 is It is connected to one terminal of the second capacitor C71 and becomes the positive output terminal TN4 of the parenthesis detection circuit, and the other terminal of the second capacitor C71 is grounded (TNI, TN2). Also, one terminal of the third capacitor C74 is connected to the second terminal of the antenna to become the input terminal TN3 of the high frequency signal Vin, and the other terminal of the third capacitor C74 is the power sword of the third diode D8. Is connected to the anode of the fourth diode D7, the anode of the third diode D8 is the negative input terminal T N5 of the detection circuit, and the power sword of the fourth diode D7 is the fourth capacitor C3. It is connected to one terminal and becomes the negative output terminal of the detection circuit, and the other terminal of the fourth capacitor is grounded.

[0061] Further, the demodulation detection circuit 122 connected in the middle of the detection circuits connected in multiple stages also includes diodes 124 and 125, capacitors C126 and C127, and is detected by the diodes 124 and 125 and demodulated by the capacitor C127. Holds the DC voltage input to the circuit. That is, the middle stage The connection terminal TN10 of the diodes D2 and D3 of the detection circuit in FIG. 3 is connected to the anode of the diode 124 of the detection circuit 122 for demodulation, and the force sword is connected to the first terminal of the capacitor C 127 via the diode 125. The second terminal of capacitor 127 is connected to the negative terminal. One terminal of the capacitor 126 is connected to the second terminal of the antenna and connected to the input terminal TN3 of the high frequency signal Vin, and the other terminal is connected between the two diodes 124 and 125.

[0062] The demodulator circuit 123 is composed of an amplifier circuit that amplifies the signal detected by the resistor and the rectifier circuit. One terminal of the resistor and the input terminal of the amplifier are connected to the positive output terminal of the detector circuit. The other terminal and the other terminal of the amplifier are connected to the negative terminal of the detection circuit. The demodulating circuit 123 has the same configuration as the demodulating circuit 103 described with reference to FIG. 13 and performs the same demodulating action. The limiter 128 is provided for protecting each circuit as described above.

[0063] The full-wave rectifier circuit system of the present embodiment also has the same effect as the embodiments described above. Industrial applicability

[0064] According to the present invention, it is possible to supply a wireless tag with a small size, low cost, and long communication distance without increasing the circuit scale. As a result, when entering or leaving a building or room, it becomes easier to manage the entry and exit of people and objects even if they are far away from each other. In addition, for systems such as package collection management, the interval between reader / writer devices can be increased. Alternatively, if the communication distance remains unchanged, the output level of the reader / writer can be reduced, and the reader / writer device can be reduced in size and power consumption can be reduced. In the case of deviation, a low-cost system can be provided.

Brief Description of Drawings

FIG. 1 is a circuit block diagram showing a basic configuration of the present invention.

FIG. 2 is a specific circuit configuration diagram showing a first embodiment of the present invention.

FIG. 3 is a circuit block diagram of a wireless tag to which the present invention is applied.

FIG. 4 is an operation explanatory diagram of the first embodiment of the present invention.

FIG. 5 is a diagram showing an operation analysis result of the circuit according to the first example of the present invention.

FIG. 6 is a circuit block diagram showing a second embodiment of the present invention. FIG. 7 is a specific circuit configuration diagram showing a second embodiment of the present invention.

FIG. 8 is a circuit block diagram showing a third embodiment of the present invention.

FIG. 9 is a specific circuit configuration diagram showing a third embodiment of the present invention.

FIG. 10 is a circuit block diagram showing a fourth embodiment of the present invention.

FIG. 11 is a specific circuit configuration diagram showing a fourth embodiment of the present invention.

FIG. 12 is a circuit block diagram showing a fifth embodiment of the present invention.

FIG. 13 is a specific circuit configuration diagram showing a fifth embodiment of the present invention.

FIG. 14 is a circuit block diagram showing a sixth embodiment of the present invention.

FIG. 15 is a specific circuit configuration diagram showing a sixth embodiment of the present invention.

FIG. 16 is a circuit diagram of a conventional non-contact type IC card.

Explanation of symbols

20, 41, 61, 81, 101, 121 ... Rectifier circuit, 21, 43, 63, 82, 103, 123 ... Demodulator circuit, 42, 62, 102, 122 ... Demodulator detector circuit, 22, 23, 24, 25, 71, 72, 83, 84… detection circuit, 28, 46, 68, 87, 106, 123 ... limiter, 130 ... antenna, 131 ... rectifier circuit, 132 ... Demodulator circuit 133 ... Modulator circuit 134 ... Limiter 135 ... Logic control circuit 136 ... Memory TN0, TN1, TN2, TN3, TN4, TN5, TN11 ... terminals.

Claims

The scope of the claims

[1] A rectifier circuit for a radio communication device that rectifies a high-frequency signal received from an antenna and generates a DC voltage for a power supply,

A plurality of stages of detection circuits connected in cascade via the connection terminals;

A first terminal for antenna signal input provided in the detection circuit of each stage constituting the rectifier circuit;

A demodulation circuit connection terminal provided between the first-stage detection circuit and the final-stage detection circuit of the rectifier circuit;

A rectifier circuit for a radio communication device, comprising: a DC voltage output terminal for supplying power, which is provided in a detector circuit at a final stage of the rectifier circuit.

[2] In claim 1,

A rectifier circuit for a radio communication apparatus, wherein an input terminal of the demodulation circuit is connected to a connection terminal between adjacent detection circuits connected in cascade.

[3] In claim 1,

Rectification for a radio communication device, characterized in that an internal terminal of any of the detection circuits connected in cascade between the first-stage detection circuit and the final-stage detection circuit is used as the demodulation circuit connection terminal. circuit.

[4] A demodulation circuit that demodulates a high-frequency signal received by an antenna, a logic control circuit that processes the demodulated signal, and a DC voltage as a power source by rectifying the high-frequency signal received by the antenna force A wireless communication device including a rectifier circuit, wherein the rectifier circuit is formed by cascading a plurality of stages of detector circuits,

A wireless communication apparatus, wherein a terminal between a first-stage detection circuit and a final-stage detection circuit of the rectifier circuit is connected to an input terminal of the demodulation circuit.

[5] In claim 4,

A radio communication apparatus, wherein an input terminal of the demodulation circuit is connected to a connection terminal between adjacent detection circuits connected in cascade.

[6] In claim 4,

Each detector circuit constituting the rectifier circuit has half-wave rectifiers having first to third terminals. Circuit,

The first terminal is connected to the transmission / reception antenna terminal, the second terminal is connected to the output terminal of the preceding detection circuit, and the third terminal is connected to the input terminal of the detection circuit in the next stage. The detector circuit is connected in multiple stages,

The wireless communication device, wherein the second terminal of the first-stage detection circuit is grounded.

[7] In claim 4,

A radio communication device characterized in that an internal terminal of one of the detection circuits connected in cascade between the first detection circuit and the final detection circuit of the rectifier circuit is connected to an input terminal of the demodulation circuit. .

[8] In claim 4,

A connection terminal between any of the detection circuits connected in cascade between the first detection circuit and the final detection circuit of the rectifier circuit and the transmission / reception antenna terminal are connected to the input of the demodulation detection circuit, A radio communication apparatus, wherein an output terminal of the demodulation detection circuit is connected to an input terminal of the demodulation circuit.

[9] In claim 4,

Each detection circuit constituting the rectifier circuit is a full-wave rectifier circuit having first to third terminals,

The first terminal of each detection circuit is connected to a transmission / reception antenna terminal, the second terminal is connected to an output terminal of the detection circuit in the previous stage,

The third terminal is connected to the input terminal of the detection circuit at the next stage,

The wireless communication device, wherein the second terminal of the first detection circuit is grounded.

[10] A transmission / reception antenna and an external force, a demodulation circuit that demodulates a high-frequency signal transmitted and received by the antenna, a logic control circuit that processes information indicated by the demodulation signal, a storage circuit, and the processed signal In a wireless communication device comprising: a circuit that modulates a high-frequency signal to be transmitted by an antenna; and a rectifier circuit that rectifies the high-frequency signal received from the antenna and generates a DC power supply voltage that is supplied to each circuit; The rectifier circuit is configured by cascading multiple stages of detector circuits, and a terminal between the first stage detector circuit and the final stage detector circuit of the rectifier circuit is connected to the input terminal of the demodulation circuit. A radio communication apparatus characterized in that a rectification operation necessary for envelope detection of demodulation in the demodulation circuit is performed by the rectification circuit, and a part of the rectification circuit and the demodulation circuit are shared.

[11] In claim 10,

The detector circuit constituting the rectifier circuit is a half-wave rectifier circuit, the first terminal of each detector circuit is connected to the transmitting / receiving antenna terminal, the second terminal is connected to the output terminal of the preceding detector circuit, The third terminal is connected to the input terminal of the next-stage detection circuit, and the detection circuit is connected in multiple stages.

A radio communication apparatus characterized in that a second terminal of the first detection circuit is grounded, and an input terminal of the demodulation circuit is connected to a connection terminal between the detection circuits in the middle stage connected in multiple stages. .

[12] In claim 10,

The detection circuit constituting the rectification circuit is a half-wave rectification circuit, the first terminal of each detection circuit is connected to a transmission / reception antenna terminal, and the second terminal is connected to the output terminal of the detection circuit in the previous stage, The third terminal is connected to an input terminal of a next-stage detection circuit, and the detection circuit is connected in multiple stages.

The second terminal of the first detection circuit is grounded, and an input of a detection circuit for demodulation different from the detection circuit connected in multiple stages from the internal terminal of the detection circuit in the middle stage connected in multiple stages And an input terminal of the demodulation circuit is connected to an output terminal of the demodulation circuit for demodulation.

[13] In claim 10,

The second terminal of the first detection circuit is grounded, and the intermediate stage connected to the multistage A connection terminal between the detection circuits and the transmission / reception antenna terminal are connected to an input of a detection circuit for demodulation different from the detection circuits connected in multiple stages, and an output terminal of the demodulation circuit is connected to an output terminal of the demodulation circuit for demodulation. A wireless communication apparatus to which an input terminal is connected.

[14] In claim 10,

The detector circuit constituting the rectifier circuit is a full-wave rectifier circuit, the first terminal of each detector circuit in the previous period is connected to the transmission / reception antenna terminal, and the second terminal is connected to the output terminal of the detector circuit in the previous stage, The third terminal is connected to an input terminal of a next-stage detection circuit, and the detection circuit is connected in multiple stages.

The wireless communication apparatus, wherein a second terminal of the first detection circuit is grounded, and an input terminal of the demodulation circuit is connected to a connection terminal between the detection circuits in the middle stage connected in multiple stages.

[15] In claim 10,

The detector circuit constituting the rectifier circuit is a full-wave rectifier circuit, the first terminal of each detector circuit is connected to the transmission / reception antenna terminal, and the second terminal is connected to the output terminal of the detector circuit in the previous stage. The third terminal is connected to the input terminal of the next-stage detection circuit, and the detection circuit is connected in multiple stages.

The second terminal of the first detection circuit is grounded, and the internal terminal of the intermediate detection circuit connected in multiple stages is connected to the input of the demodulation detection circuit, and the output of the demodulation detection circuit A radio communication apparatus, wherein an input terminal of the demodulation circuit is connected to a terminal.

[16] In claim 10,

The detector circuit constituting the rectifier circuit is a full-wave rectifier circuit, the first terminal of each detector circuit is connected to a transmission / reception antenna terminal, and the second terminal is connected to the output terminal of the preceding detector circuit, The third terminal is connected to an input terminal of a next-stage detection circuit, and the detection circuit is connected in multiple stages.

A second terminal of the first detection circuit is grounded, and a connection terminal between the detection circuits in the middle stage connected in multiple stages and the transmission / reception antenna terminal are connected to an input of the detection circuit for demodulation, and the demodulation The input terminal of the demodulation circuit is connected to the output terminal of the detection circuit for A wireless communication device.

[17] In claim 11,

In the detection circuit constituting the rectifier circuit, one terminal of a first capacitor is connected to a transmission / reception antenna terminal to serve as an input terminal for a high-frequency signal, and the other terminal of the first capacitor is a first diode force sword. And the anode of the first diode serves as an input terminal of the detection circuit, the force sword of the second diode is connected to one terminal of a second capacitor, and the detection circuit is connected to the anode of the second diode. The output terminal of the circuit, the other terminal of the second capacitor is grounded,

The demodulator circuit includes an amplifier circuit that amplifies the signal detected by the resistor and the rectifier circuit. One terminal of the resistor and the input terminal of the amplifier are connected to the output terminal of the detector circuit, and the other terminal of the resistor and the amplifier Radio communication apparatus characterized in that other terminals are grounded

[18] In claim 12,

In the detection circuit constituting the rectifier circuit, one terminal of the first capacitor is connected to a transmitting / receiving antenna terminal to serve as an input terminal for a high-frequency signal, and the other terminal of the first capacitor is connected to the first diode force sword and the first diode. Connected to the anode of the second diode, the anode of the first diode is the input terminal of the detector circuit, the force sword of the second diode is connected to one terminal of the second capacitor,

The detection circuit for demodulation connected to the middle stage of the detection circuit connected in multiple stages has one diode and one capacitor,

The connection terminals of the first diode and the second diode of the detection circuit in the middle stage and the anode of the diode of the detection circuit for demodulation different from the detection circuit connected in multi-stage are connected, and the force sword is Connected to the first terminal of the capacitor, the second terminal of the capacitor is grounded,

The demodulator circuit includes an amplifier circuit that amplifies the signal detected by the resistor and the rectifier circuit, and a resistor is connected to the first terminal of the capacitor of the demodulator detector circuit different from the multistage detector circuit. One terminal and an input terminal of an amplifier are connected, and the other terminal of the resistor and the other terminal of the amplifier are grounded.

[19] In claim 10,

The wireless communication apparatus, wherein the wireless communication apparatus is a wireless tag that performs non-contact data communication using electromagnetic induction by the antenna.

[20] In claim 19,

The rectifier circuit power is also provided with a limiter that suppresses the power supply voltage supplied to a predetermined level,

The wireless communication device, wherein the rectifier circuit, the demodulation circuit, the modulation circuit, the limiter, the logic control circuit, and the memory are formed as a CMOS circuit on a common substrate.