WO2007147048A3 - Protocol manager for massive multi-site test - Google Patents

Protocol manager for massive multi-site test Download PDF

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Publication number
WO2007147048A3
WO2007147048A3 PCT/US2007/071207 US2007071207W WO2007147048A3 WO 2007147048 A3 WO2007147048 A3 WO 2007147048A3 US 2007071207 W US2007071207 W US 2007071207W WO 2007147048 A3 WO2007147048 A3 WO 2007147048A3
Authority
WO
WIPO (PCT)
Prior art keywords
test
comparisons
protocol manager
device under
mms
Prior art date
Application number
PCT/US2007/071207
Other languages
French (fr)
Other versions
WO2007147048A2 (en
Inventor
Jayashree Saxena
Alessandro Paglieri
Matthew Craig Bullock
Original Assignee
Texas Instruments Inc
Jayashree Saxena
Alessandro Paglieri
Matthew Craig Bullock
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/761,440 external-priority patent/US7580807B2/en
Application filed by Texas Instruments Inc, Jayashree Saxena, Alessandro Paglieri, Matthew Craig Bullock filed Critical Texas Instruments Inc
Publication of WO2007147048A2 publication Critical patent/WO2007147048A2/en
Publication of WO2007147048A3 publication Critical patent/WO2007147048A3/en

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31907—Modular tester, e.g. controlling and coordinating instruments in a bus based architecture

Abstract

Disclosed herein is a massive multi-site (MMS) testing architecture (100) The MMS architecture includes a MMS interface (116) on each of a plurality of devices under test (106) The MMS interface includes a test protocol manager that may receive test stimulus and send the test stimulus to cores of the device under test The test protocol manager may receive test responses from cores of the device under test and generate test comparisons based on comparisons between the test responses and expected responses The test protocol manager may store the test comparisons on the device under test and communicate the stored test comparisons to automated test equipment (ATE) upon being queried by the ATE The device under test may send the test comparisons to the ATE over a low-bandwidth communication
PCT/US2007/071207 2006-06-15 2007-06-14 Protocol manager for massive multi-site test WO2007147048A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US80491006P 2006-06-15 2006-06-15
US60/804,910 2006-06-15
US11/761,440 2007-06-12
US11/761,440 US7580807B2 (en) 2006-06-15 2007-06-12 Test protocol manager for massive multi-site test

Publications (2)

Publication Number Publication Date
WO2007147048A2 WO2007147048A2 (en) 2007-12-21
WO2007147048A3 true WO2007147048A3 (en) 2008-10-02

Family

ID=38832848

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/071207 WO2007147048A2 (en) 2006-06-15 2007-06-14 Protocol manager for massive multi-site test

Country Status (1)

Country Link
WO (1) WO2007147048A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI459008B (en) * 2012-05-30 2014-11-01 Ind Tech Res Inst 3d memory and built-in self test circuit thereof
US11170675B2 (en) * 2020-03-19 2021-11-09 Himax Technologies Limited Method for performing hybrid over-current protection detection in a display module, and associated timing controller

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5592493A (en) * 1994-09-13 1997-01-07 Motorola Inc. Serial scan chain architecture for a data processing system and method of operation
US6125464A (en) * 1997-10-16 2000-09-26 Adaptec, Inc. High speed boundary scan design
US6836865B2 (en) * 2001-10-09 2004-12-28 International Business Machines Corporation Method and apparatus for facilitating random pattern testing of logic structures
US7036060B2 (en) * 1998-09-22 2006-04-25 Hitachi, Ltd. Semiconductor integrated circuit and its analyzing method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5592493A (en) * 1994-09-13 1997-01-07 Motorola Inc. Serial scan chain architecture for a data processing system and method of operation
US6125464A (en) * 1997-10-16 2000-09-26 Adaptec, Inc. High speed boundary scan design
US7036060B2 (en) * 1998-09-22 2006-04-25 Hitachi, Ltd. Semiconductor integrated circuit and its analyzing method
US6836865B2 (en) * 2001-10-09 2004-12-28 International Business Machines Corporation Method and apparatus for facilitating random pattern testing of logic structures

Also Published As

Publication number Publication date
WO2007147048A2 (en) 2007-12-21

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