WO2007138512A2

WO2007138512A2 - Flash analogue to digital converter

Info

Publication number: WO2007138512A2
Application number: PCT/IB2007/051839
Authority: WO
Inventors: Peter C. S. Scholtens
Original assignee: Nxp B.V.
Priority date: 2006-05-30
Filing date: 2007-05-15
Publication date: 2007-12-06
Also published as: WO2007138512A3

Abstract

The invention relates to a flash analogue to digital converter comprising a first analogue input (150) and a plurality of series connected first resistive elements (110) forming a resistor ladder (170), the resistor ladder (170) having a first ladder terminal (105), a second ladder terminal (106) and a plurality of ladder nodes (101). With the resistor ladder (170) coupled with the first ladder terminal (105) to a reference voltage and with the second ladder terminal (106) coupled to ground the maximal input voltage coupled to the first analogue input (150) exceeds the reference voltage and the minimal input voltage coupled to the first analogue input (150) is lower than the ground potential, thereby realizing an enlarged input voltage range. The first resistive elements (110) have not all an equal resistance.

Description

FLASH ANALOGUE TO DIGITAL CONVERTER

The invention relates to a flash analogue to digital converter.

The publication ISLPED'04, August 9-11 2004 titled 'A Low-Power Rail-to- Rail 6-bit Flash ADC Based on a Novel Complementary Average- Value approach', (herein after referred to as Hui-Chin Tseng et. al.) discloses a flash analogue to digital converter in which the input signal is pre-processed and then steered to be compared with a fixed reference voltage level. This greatly simplifies the comparator design and thus power consumption is reduced. In addition a rail-to-rail input voltage range is achieved.

In recent years the CMOS technology is continuously evolving into deep sub- micron. The supply voltage is decreased with the technology to maintain the same electrical field inside the transistors. As a major building block, analogue to digital converters are widely used in mixed signal systems. For analogue to digital converters besides the improvement in speed the impact of the deep sub-micron technology is a decreased signal swing.

It is an object of the invention to provide a flash analogue to digital converter in which the input voltage range is enlarged thereby allowing a larger signal swing.

This object is achieved with the flash analogue to digital converter as defined in claim 1.

With the resistor ladder coupled with the first ladder terminal to a reference voltage and with the second ladder terminal coupled to ground the maximal input voltage coupled to the first analogue input ranges from approximately ground to approximately the reference voltage. Thus the input voltage range is enlarged, thereby achieving the object of the invention.

The embodiment of the converter as defined in claim 2 has the advantage that the input voltage range is further enlarged. With the resistor ladder coupled with the first ladder terminal to a reference voltage and with the second ladder terminal coupled to ground the maximal input voltage coupled to the first analogue input exceeds the reference voltage and the minimal input voltage coupled to the first analogue input is lower than the ground potential. Thereby an enlarged input voltage range is realized. A further embodiment of a flash analogue to digital converter as defined in claim 3 and 4 has the advantage that the total resistor ladder resistance is increased, thereby reducing the contribution of the current through the resistor ladder to the power consumption.

A further embodiment of a flash analogue to digital converter as defined in claim 5 has the advantage of reduced distortion at high signal frequencies. The distortion reduction is achieved by a matching bandwidth of the signal transfers from the analogue input to each one of the first comparator inputs.

A further embodiment of the flash analogue to digital converter as defined in claim 6 has the advantage that the input impedance of the first analogue input matches the cable impedance. This prevents echoing of high signal frequencies coupled to the first analogue input.

Further embodiments of the flash analogue to digital converter as defined in claims 7 and 9 respectively have the advantage that the converter further comprises a second analogue input enabling the analogue input signal to be a differential signal coupled to the first analogue input and to the second analogue input.

The invention will be explained in more detail with reference to the accompanying drawing in which: Fig. 1 schematically shows a prior art ADC.

Fig. 2 schematically shows an embodiment of an ADC according to the invention.

Fig. 3 schematically shows an embodiment of an ADC according to the invention. Fig. 4 schematically shows an embodiment of an ADC according to the invention comprising three comparators

Fig. 5 shows an electrical equivalent schematic of the embodiment of fig. 4.

Fig. 6 schematically shows a further embodiment of an ADC according to the invention having a first analogue input and a second analogue input. Fig. 7 schematically shows an embodiment according to fig. 9 comprising three comparators.

Fig. 8 shows an electrical equivalent schematic of the embodiment of fig. 7.

Fig. 9 schematically shows another embodiment of an ADC according to the invention having a first analogue input and a second analogue input. Identical components have been given the same reference signs in these figures. In fig. 1 a prior art flash analogue converter is shown comprising a first analogue input 150 and series connected first resistive elements 110 forming a resistor ladder 170. The resistor ladder 170 has a first ladder terminal 105 and a second ladder terminal 106. A first voltage source 180 with a voltage of Vref is coupled to the first ladder terminal 105. A second voltage source 190 is coupled to the second ladder terminal 106. In Hui-Chin Tseng et. al. the value of the second voltage source is zero volts. The resistor ladder 170 further comprises a plurality of ladder nodes 101 located at the connections between the first resistive elements 110. The converter further comprises a plurality of comparators 100, each one of the comparators comprising a first comparator input 104, a second comparator 107 and a comparator output 103. The comparator outputs 103 are arranged for providing a digital output code 300. A plurality of the second resistive elements 160 is coupled between each one of the ladder nodes 101 and each one of the first comparator inputs 104 and a plurality of third resistive elements 240 is coupled between the first analogue input 150 and each one of the first comparator inputs 104. Each one of the first resistive elements 110 in the resistor ladder 170 has a resistance value Rs Ohm. This results in a plurality of equidistant reference voltage levels at the ladder nodes 101. Each one of the second comparator inputs 107 is coupled to a third voltage source 140 with value Vref/2. In Hui-Chin Tseng et. al. a flash analogue to digital converter with m comparators 100 comprises m+1 first resistive elements 110. The voltage difference between each two consecutive ladder 101 nodes has the value of Vref / (m+1) V. To compare an input voltage coupled to the first analogue input 150 with the reference voltage levels an input resistive divider comprising of a series connection of a second resistive element 160 with value R_L Ohm and a third resistive element 240 with value R_L Ohm is connected between each one of the ladder nodes 101 and the first analogue input 150. In Hui-Chin Tseng et. al. is stated the value of (R_L/RS) should be as large as possible to make all the tap voltages of the resistor ladder 170 more accurate. Hui-Chin Tseng et. al. discloses a minimum ratio (R_L/RS) of 1000.

To calculate the input voltage range of an analogue to digital converter according to fig. 1 it is assumed that the second ladder terminal 106 is coupled to ground and the first ladder terminal 105 is coupled to a first voltage source 180 with a value of Vref Volt. The ladder nodes 101 are numbered starting with ladder node Ln_l connected at the first ladder terminal 105 up to ladder node Ln_(m+2) at the second ladder terminal 106. The comparators 100 are numbered from A_l up to A_m, the converter having the first comparator input 104 of comparator Aj coupled through a second resistive element 160 to the ladder node Ln_(j+1) and through a third resistive element 240 to the first analogue input 150 and whereby j is an integer ranging from 1 to m, and m is an integer larger than 1.

The voltage at the first comparator input of comparator A_l, coupled to ladder node Ln_2, is referred to as V_A__I__IO4- The voltage at the first comparator input of comparator A_m coupled to ladder node Ln_(m+1) is referred to as VA__m_io4- An input voltage coupled to the first analogue input 150 is referred to as V_1n. The equations for the voltage at the first comparator input 104 coupled to node 1 and node m are given:

V_A_i_io4 = (l/2)*V_in + (l/2)*m*Vref/(m+l)

V_A_m_io4= (l/2)*V_in + (l/2)*Vref/(m+l)

The maximal voltage in the input voltage range is the input voltage that will result in a voltage at the first comparator input 104 of each one of the comparators being larger than Vref/2. The minimal voltage in the input voltage range is the input voltage that will result in a voltage at the first comparator input 104 of each one of the comparators being smaller than Vref/2. Using the above listed equations for V_A__I__IO4 and VA__m_io4 the minimal input voltage and maximal input voltage in the input voltage range are calculated to be Vref/(m+l) and m*Vref/(m+l) respectively. Hui-Chin Tseng et. al. discloses a flash analogue to digital converter wherein m+l=64. Consequently an approximately rail-to-rail input voltage range is achieved.

When m, m being the number of comparators, is reduced from 63 used by Hui-Chin Tseng et. al to for example 6 the input voltage range of an analogue to digital converter according to fig. 1 also reduces. For example with a Vref=2.5V the maximal input voltage reduces from (63/64)*2.5V = 2.46 V to (6/7)*2.5V=2.14V whereas the minimal voltage increases from 2.5V/64 = 0.04V to 2.5V/7 = 0.36V.

To enlarge the input voltage range while having a small number of comparators the resistor ladder 170 must provide a plurality of voltages wherein the voltage difference between the ladder nodes Ln_l and Ln_2 and the voltage difference between the ladder nodes Ln_(m+1) and Ln_(m+2) is smaller than the voltage difference between each two consecutive ladder nodes in the range from Ln_2 up to and including Ln_(m+1). Suppose the resistance of the of the first resistive elements 110 between ladder node Ln_l and Ln_2 and between ladder node Ln_(m+1) and Ln_(m+2) is α.Rs Ohm, α being a scaling number, whereas all other first resistive elements 110 in the resistor ladder 170 have a resistance value of Rs Ohm. The equations for the voltage at the first comparator input 104 coupled to node

1 and node m are given:

V_A_i_io4 = (l/2)*V_in + (l/2)*Vref *(m-l+α)/(m-l+2α)

(l/2)*V_m + (l/2)*Vref* α/(m-l+2α)

Using the above listed equations for V_A__I__IO4 and VA__m_io4 the minimal input voltage and maximal input voltage in the input voltage range are calculated to be Vref*α /(m- l+2α) and Vref*(m-l+α)/(m-l+2α) respectively.

When m, m being the number of comparators, is reduced from 63 used by Hui-Chin Tseng et. al to for example 6 without changing the input voltage range of the analogue to digital converter the value of α is calculated as follows:

(l/2)*Vref *α /(6-l+2α) = (l/2)*Vref/(63+l) or α /(6-l+2α) = l/64 or α = 5/62

Consequently the resistance of the first resistive elements 110 between ladder node Ln_l and Ln_2 and between ladder node Ln_7 and Ln_8 should be chosen (5/62)*Rs to keep the input voltage range unchanged. The resulting analogue to digital converter is shown in fig. 2.

The conclusion is that with the second ladder terminal 106 coupled to a second voltage source 190 with value of V2 Volt and the first ladder terminal 105 coupled to a first voltage source 180 with value Vl Volt the input voltage range is enlarged when

V_A__m_io₄ - V2 < (l/2)*(Vl-V2)/(m+l) O

V_A__m_io4 < (Vl+V2(l+2m)) / (2m+2) and Vl - VA_IJO4 < (l/2)*m*(Vl-V2) /(m+1) O V_A_i_io4 > ((m+2)Vl + mV2) / (2m+2)

A flash analogue to digital converter with an enlarged input voltage range comprises a first analogue input 150 for receiving an analogue input signal and a plurality of m comparators 100, m being an integer larger than 1. Each one of the comparators 100 comprises a first comparator input 104 and a comparator output 103. The converter further comprises a plurality of series connected first resistive elements 110 forming a resistor ladder 170. The resistor ladder 170 has a first ladder terminal 105, a second ladder terminal 106, and a plurality of ladder nodes 101 located at the connections between the first resistive elements 110. The converter further comprises a first voltage source 180 coupled to the first ladder terminal 105 and a second voltage source 190 coupled to the second ladder terminal 106. The converter further comprises a plurality of second resistive elements 160 and a plurality of third resistive elements 240. The ladder nodes 101 are numbered starting with ladder node Ln_l connected at the first ladder terminal 105 up to ladder node Ln_(m+2) at the second ladder terminal 106, and the comparators 100 numbered from A_l up to A_m. The converter has the first comparator input 104 of comparator Aj coupled through one of the second resistive elements 160 to the ladder node Ln_(j+1) and through one of the third resistive elements 240 to the first analogue input 150, whereby j is an integer ranging from 1 to m, and m is an integer larger than 1. The converter is characterised in that the resistance values of the first resistive elements 110, the second resistive elements 160 and the third resistive elements 240 are chosen such that in the absence of the analogue input signal the voltage at the first comparator input 104 of comparator A_l is larger than ((m+2)Vl + mV2) / (2m+2) and the voltage at the first comparator input 104 of comparator A_m is smaller than (Vl+V2(l+2m)) / (2m+2). Typically each comparator 100 is implemented as a complementary metal oxide semiconductor (CMOS) device. Comparison of the voltage coupled to the first comparator input 104 and the value of the third voltage source 140 coupled to the second comparator input 107 is typically done using conventional circuits comprising a NMOS or PMOS differential pair. To each one of the first comparator inputs 104 and to each one of the second comparator inputs 107 capacitance is coupled comprising of gate-source capacitance and gate-drain capacitance of the NMOS or PMOS differential pair. This capacitance is modelled as a capacitor 270 coupled between each one of the first comparator inputs 104 and ground and between each one of the second comparator inputs 107 and ground. In fig. 1 only the capacitor 270 with capacitance value C coupled to each one of the first comparator inputs

104 is shown.

The bandwidth of the signal transfer from the first analogue input 150 to each one of the first comparator inputs 104 is limited by a low pass filter comprising of a third resistive element 240, a second resistive element 160 and a capacitor 270 to approximately l/(2πR_L.C). An increase of the bandwidth requires a decrease of R_L. Since the value of

(R_L/RS) should be as large as possible a decrease of R_L is accompanied by a decrease in Rs.

Consequently an increase in bandwidth results in an increase of the contribution of the current through the resistor ladder 170 to the power consumption. Fig. 3 shows the analogue to digital converter wherein the resistance value of the first resistive elements between ladder node Ln_l and Ln_2 and between ladder nodes

Ln_(m+1) and Ln_(m+2) has been chosen equal to zero Ohm. The consequence of this for the operation of the analogue to digital converter is explained using fig. 4 where m=3 is used.

In fig. 4 the first ladder terminal 105 is coupled to a first voltage source 180 with value Vref, the second ladder terminal 106 is connected to a second voltage source with value of zero

Volt and each one of the second comparator inputs 107 is coupled to a third voltage source

140 with value Vref/2. The m-l=2 first resistive elements 110 have a value Rs Ohm, and the resistance of the second resistive element 160 and the third resistive element 240 is R_L Ohm.

An input voltage coupled to the first analogue input 150 is referred to as V_1n. First as in Hui- Chin Tseng et. al. it is assumed that Rs « R_L resulting in the following equations describing the voltage at each one of the three first comparator inputs VA_I_IO4, VA_2_IO4 and VA_3_IO4:

V_A_i_io4 = (l/2)*V_in + (l/2)*Vref

V_A_2_io4 = (l/2)*V_in + (l/4)*Vref

For input voltages below 0 Volt the voltage at each one of the first comparator inputs 104 is lower than Vref/2 and consequently each one of the comparator outputs 103 has a low output voltage equivalent with a digital 0. An input voltage larger than 0 Volt results in a voltage at the first comparator input 104 of comparator A_l larger than Vref/2 and consequently the comparator output 103 of said comparator has a high output voltage equivalent with a digital 1. To change the voltage at the comparator output 103 of comparator A_2 to a high output voltage an input voltage larger than Vref/2 is required and to change the voltage at the output of comparator A_3 an input voltage larger than Vref is required. A first advantage of a converter according to the embodiment of claim 2 is that a large input voltage range is achieved irrespective of the value of m, m being the number of comparators. A second advantage is that the input voltage range now exceeds the supply rails. The input voltage range to change the digital code 300 provided at the comparator outputs 103 from digital code 000 to digital code 111 is from below 0 Volt to larger than Vref.

A flash analogue to digital converter according to the embodiment of claim 2 comprises a plurality of m comparators 100 and m-1 first resistive elements 110 with a resistance value different from zero, m being an integer larger than 1. The resistance values of these m-1 first resistive elements 110 are not necessarily equal. Nor are the resistance values of the second resistive elements 160 and the third resistive elements 240 necessarily equal. Also it is not required that the resistance value of the first resistive element 110 is much smaller than the resistance value of the second resistive elements 160.

Fig. 5 shows a simplified schematic derived from fig. 4 and is used to determine the consequence of dropping the condition that the value of (R_L/RS) should be as large as possible. The resistor ladder 170 of fig. 4 is replaced with the Thevenin electrical equivalent comprising a fourth voltage source 130 with a value of Vref/2 in series with an output resistance 111 of value Rs/2. The resistance value of the second resistive elements 160 and the third resistive elements 240 that are coupled to the first comparator input 104 of comparators A_l and A_3 is R_L Ohm. The resistance value of the second resistive element 160 coupled to the first comparator input of A_2 is R_x2 and the resistance value of the third resistive element 240 coupled to the first comparator input of A_2 is R_y2. The voltages at each one of the first comparator inputs is given by:

V_A_i_io4 = (1/2)* V_1n + (1/2)* Vref

(R_x2+Rs/2) / (R_x2+R_y2+Rs/2)*V_m + R_y2/ (R_x2+R_y2+Rs/2)* Vref/2

For unchanged operation of the converter of fig. 5 in comparison with the converter of fig. 4 the resistance values for R_x2 and R_y2 are chosen such that:

(R_x2+Rs/2) / (R_x2+R_y2+Rs/2) =1/2 and R_y2/ (R_x2+R_y2+Rs/2) = 1/2 There is a large degree of freedom in choice for the values for R_x2 and R_y2 given a value for Rs. As an example is chosen to have R_x2+R_y2 = 2*R_L. The values for R_x2 and R_y2 are given by:

R_x2 = R_L - Rs/4 and R_y2 = R_L + Rs/4.

In another example it is chosen to have

R_x2 = 0 and R_y2 = Rs/2.

In a further example it is chosen to have the impedance at each one of the first comparator inputs 104 equal. An advantage of having equal impedance is that the bandwidth of the signal transfers from the first analogue input 150 to each one of the first comparator inputs 104 matches. A non-matching bandwidth results in amplitude dependency of the signal transfer, which is a source of distortion at high signal frequencies.

To have an equal impedance of R_L/2 at each one of the first comparator inputs 104:

R_x2 = R_L-RS/2 and R_y2 = R_L.

In this example the value of R_L is still free to choose. A criterion for choosing the value of R_L is to match the input impedance of the analogue to digital converter to the characteristic impedance of a cable that may be coupled to the first analogue input 150. The characteristic impedance of a cable is independent of the length of the cable and is specified in Ohms. For a cable it can be shown that for high frequencies the characteristic impedance is given by V (L/C), L being the inductance and C being the capacitance of the cable. Most coaxial cables used will range from 50 Ohm to 95 Ohm. A converter input impedance with an impedance value that is substantially equal to the characteristic impedance of the cable that is coupled to the input will prevent high signal frequencies from echoing. It is clear from the examples given that it is unnecessary to choose the resistance value of each one of the first resistive elements 110 much smaller than the resistance value of the second resistive elements 160. Consequently it is possible to increase the resistance value of the resistor ladder 170 without decreasing the bandwidth of the signal transfer from the first analogue input 150 to each one of the first comparator inputs 104. In an analogue to digital converter as defined in claim 1 comprising m comparators a network comprising the first resistive elements 110 with value Rsj connected in series forming a resistor ladder 170 with a first ladder terminal 105 and a second ladder terminal 106, the second resistive elements 160 with value R_XJ coupled between ladder node Ln_(j+1) and a first comparator input 104 of comparator Aj and the third resistive elements 240 with value R_yj coupled between a first comparator input 104 of comparator Aj and the first analogue input 150 realizes three transfer functions: a transfer function G_j(V_1n) from the first analogue input 150 to a first comparator input 104 of comparator Aj; - a transfer function H_j(Vl) from the first voltage source 180 coupled to the first ladder terminal 105 to the first comparator input 104 of comparator Aj; a transfer function J_j(V2) from the second voltage source 190 coupled to the second ladder terminal 106 to the first comparator input 104 of comparator Aj;

Herein is j an integer in the range from 1 to m, Vl is the value of the first voltage source 180 coupled to the first ladder terminal 105, V2 the value of the second voltage source 190 coupled to the second ladder terminal 106 and V_1n the input voltage coupled to the first analogue input 150.

Suppose the ladder nodes 101 are numbered starting with ladder node Ln_l connected at the first ladder terminal 105 up to ladder node Ln_(m+2) at the second ladder terminal 106, and the comparators 100 are numbered from A_l up to A_m. The converter has the first comparator input 104 of comparator Aj coupled through a second resistive element 160 with resistance value R_XJ to the ladder node Ln_(j+1). Said first comparator input 104 of comparator Aj is also coupled through a third resistive element 240 with value R_yi to the first analogue input 150. Hereby is j ranging from 1 to m, and is m an integer larger than 2. A first resistive element 110 with value R_skis coupled between ladder node Ln_k and ladder node Ln_(k+1), whereby k in an integer ranging from 1 to m+1. Each one of the m comparators 100 in this range is coupled through a second resistive element 160 to a ladder node 101 and through a third resistive element 240 to the first analogue input 150.

The voltages at each one of the first comparator inputs, V_AJ__IO4 is given by:

V_Aj_io4 = G_j(V_1n) + H_j(Vl) +J_j(V2) (1) Since the analogue to digital conversion is done with equidistant voltage steps the resistance values of the first resistive elements 110, the second resistive elements 160 and the third resistive elements 240 are chosen such that

G_j(V_1n) - G_J+1(V_in) + H_j(Vl) - H_j+1(Vl) + J_j(V2) - J_J+1(V2) = (Vl-V2)/(m-l) (2)

for j e { 1,...m} and m being an integer larger than 1 and Rsl=Rs(m+l) = 0Ω, wherein RsI is the value of the first resistive element between ladder node Ln_l and Ln_2 and Rs(m+1) is the valueof the first resistive element between ladder node Ln_(m+1) and Ln_(m+2). In case both RsI and Rs(m+1) are chosen different from zero Ohm the resistance values of the first resistive elements 110, the second resistive elements 160 and the third resistive elements 240 are chosen such that:

G_j(V_1n) - G_j+I(V_1n) + H_j(Vl) - H_j+1(Vl) + J_j(V2) - J_J+1(V2) = (Vl-V2)/(m+l)

for j e { 1 , ...m} and m being an integer larger than 1. For an enlarged input voltage range the resistance values of the first resistive elements 110, second resistive elements 160 and third resistive elements 240 are chosen such that with no analogue input signal the voltage at the first comparator input 104 of comparator A_l is larger than ((m+2)Vl + mV2) / (2m+2) and the voltage at the first comparator input 104 of comparator A_m is smaller than (Vl+V2(l+2m)) / (2m+2).

Equation (2) is used to calculate values for R_XJ and R_yj for j=l up to j=m and for R_S(k+i₎ for k=l up to k=m-l under the condition that Rsl=Rs(m+l) = 0Ω. The results are shown in table 1 and 2.

Table 1 shows an example with the calculated resistance values for the first resistive elements 110, second resistive elements 160 and third resistive elements 240 for m=6 whereby the sum of the resistance values of the second resistive element 160 and third resistive element 240 that are coupled to a first comparator input 104 has been kept constant and the value of RsI and Rs7 are equal to zero.

Table 1

Table 2 shows an example with the calculated resistance values for the first resistive elements 110, second resistive elements 160 and third resistive elements 240 for m= 9 whereby resistance values are chosen such that the impedance at each one of the first comparator inputs 104 is substantially equal. The value of RsI and RsIO are equal to zero.

Table 2

The calculated resistance values in table 1 and 2 show that in case the resistance values of the first resistive elements 110 is not chosen much smaller than the resistance value of the second resistive elements 160 as in Hui-Chin Tseng et. al. the resistance values of the first resistive elements will not be all equal to each other. In case there is an even number of comparators 100 as in table 1 each two consecutive first resistive elements 110 in the resistor ladder 170 have different resistance values. In case there is an odd number m of comparators 100 as in table 2 (m-l)/2 pairs of first resistive elements 110 have a substantially equal resistance and the resistance values of first resistive elements 110 of different pairs are different, m being an integer larger than 1. Fig. 6 schematically shows an embodiment according to claim 9 wherein the analogue to digital converter described in claim 1 further comprises a second analogue input 151 and the converter is arranged for receiving a differential analogue input signal coupled to the first analogue input 150 and to the second analogue input 151. The converter further comprises a further resistor ladder 171 having a plurality of series connected first resistive elements 110. The further resistor ladder 171 has a third ladder terminal 109 and a fourth ladder terminal 108, the fourth ladder terminal 108 being coupled to the second voltage source 190 and the third ladder terminal 109 being coupled to the first voltage source 180. The further resistor ladder 171 has a plurality of further ladder nodes 102 located at the connections between the first resistive elements 110 and at the third and fourth ladder terminals 109, 108. The converter further comprises a plurality of fourth resistive elements 260 and a plurality of fifth resistive elements 340. Each one of the comparators 100 in the converter further comprises a second comparator input 107. The converter has the further ladder nodes 102 numbered starting with ladder node Ln_(m+3) connected at the third ladder terminal 109 up to ladder node Ln_(2m+4) at the fourth ladder terminal 108. The converter further has the second input 107 of comparator A_J coupled through one of the fourth resistive elements 260 to the ladder node Ln_(2m+4-j) and through one of the fifth resistive elements 340 to the second analogue input 151. The converter is characterised in that the resistance values of the first resistive elements 110, the second resistive elements 160, the third resistive elements 240, the fourth resistive elements 260 and the fifth resistive elements 340 are chosen such that in the absence of the differential analogue input signal the voltage at the first comparator input 104 of comparator A_l and the second comparator input 107 of comparator A_m is larger than ((m+2)Vl + mV2) / (2m+2) and the voltage at the first comparator input (104) of comparator A_m and the second comparator input of comparator A_l is smaller than (Vl+V2(l+2m)) / (2m+2).

A flash analogue to digital converter according to the embodiment of fig. 6 having m comparators 100 comprises 2m+2 first resistive elements 110. The resistance values of the first resistive elements 110 are not necessarily equal. Nor are the resistance values of the second resistive elements 160, the third resistive elements 240, the fourth resistive elements 260 and the fifth resistive elements 340 necessarily equal. Also it is not required that the resistance value of the first resistive element 110 is much smaller than the resistance value of the second resistive elements 160 or fourth resistive elements 260. For considerations on the resistance value of the first resistive elements 110, the second resistive elements 160, the third resistive elements 240 and the fourth resistive elements 260 is referred to the discussion of fig. 2, 3, 4 and 5.

Fig. 9 schematically shows an embodiment according to claim 1 wherein the analogue to digital converter according to claim 1 further comprises a second analogue input 151 and the converter is arranged for receiving a differential analogue input signal coupled to the first analogue input 150 and to the second analogue input 151. Each one of the comparators 100 in the converter further comprises a second comparator input 107. The converter further comprises a plurality of fourth resistive elements 260 and a plurality of fifth resistive elements 340. The converter has the second comparator input 107 of comparator Aj coupled through one of the fourth resistive elements 260 to the ladder node Ln_(m-j+2) and through one of the fifth resistive elements 340 to the second analogue input 151. The converter is characterised in that the resistance values of the first resistive elements 110, the second resistive elements 160, the third resistive elements 240, the fourth resistive elements 260 and the fifth resistive elements 340 are chosen such that in the absence of the differential analogue input signal the voltage at the first comparator input 104 of comparator A_l and the second comparator input 107 of comparator A_m is larger than ((m+2)Vl + mV2) / (2m+2) and the voltage at the first comparator input (104) of comparator A_m and the second comparator input of comparator A_l is smaller than (Vl+V2(l+2m)) / (2m+2).

The operation of this analogue to digital converter is explained using fig. 7 where m=3 and the value of RsI and Rs4 have been chosen equal to zero Ohm. The resistance value of the first resistive elements 110 between ladder node Ln_2 and Ln_3 and between Ln_3 and Ln_4 is Rs Ohm. In fig. 8 the ladder node Ln_3 coupled to the second resistive element 160 with value R_x2 and fourth resistive element 260 with value R_x2 is replaced with the Thevenin electrical equivalent of a fourth voltage source 130 with a value of Vref/2 in series with an output resistance 111 of value Rs/2. The resistance value of the second resistive elements 160, the third resistive elements 240, fourth resistive elements 260 and fifth resistive element 340 that are coupled to the comparators A_l and A_3 is R_L Ohm. A set of three equations describing the voltage difference of the voltage at the first comparator input 104 V_AJ__IO4 and the voltage at the second comparator input 107 V_AJ__IO7, j being 1,2 or 3, is given by:

V_A_i_io4 - V_A_i_io7 =(1/2)* Vd + Vref/2

VA_₂_104 - VA_₂_107 / (Rχ₂+Ry₂)*Vd

VA_3_IO4 - V_A_3_IO7 =(1/2)* V_d - Vref/2 The resistance values for R_x2 and R_y2 are chosen such that:

or:

The choice for the resistance value of R_x2 = R_y2 is not dependent on the value for Rs and can be chosen freely. As an example it is possible to choose the resistance value of R_x2 and R_y2 such that the bandwidth of the signal transfers from the first analogue input 150 to each one of the first comparator inputs 104 and from the second analogue input 151 to each one of the second comparator inputs 107 matches.

As a further example a criterion for choosing the value of R_x2= R_y2 and R_L is to match the input impedance of the first analogue input 150 and second analogue input 151 to the characteristic impedance of a cable that may be coupled to it.

In the embodiment of fig. 9 one resistor ladder 170 is used to create the plurality of reference voltage levels. Therefore in comparison with the embodiment of fig. 5 the contribution of the current to the power consumption is further reduced. For an enlarged input voltage range the resistance values of the first resistive elements 110, second resistive elements 160, third resistive elements 240, the fourth resistive elements 260 and the fifth resistive elements 340 are chosen such that in the absence of the differential analogue input signal the voltage at the first comparator input 104 of comparator A_l and the second comparator input 107 of comparator A_m is larger than ((m+2)Vl + mV2) / (2m+2) and the voltage at the first comparator input 104 of comparator A_m and the second comparator input of comparator A_l is smaller than (Vl+V2(l+2m)) / (2m+2).

The resistance value of the first resistive elements 110 is dependent on the chosen resistance value of the fourth resistive elements 260, the second resistive elements 160, the fifth resistive element 340 and the third resistive element 240.

As an example the resistance value of a fourth resistive element 260, of a second resistive element 160, of a fifth resistive element 340 and of a third resistive element 240 are chosen equal to R_L and both RsI and Rs(m+1) equal zero Ohm. To calculate the resistance value of the first resistive elements 110 it is assumed that the differential input voltage is zero Volt and that the first analogue input 150 and the second analogue input 151 are coupled to a reference voltage with the value of Vref/2 Volt. Further is assumed that the first ladder terminal 105 is coupled to a first voltage source 180 with the value of Vref Volt and the second ladder terminal 106 is coupled to a second voltage source 190 with the value of zero Volt. The resistance value of the first resistive elements 110 is chosen such that the m ladder nodes 101 provide m equidistant reference voltages: ladder node Ln_k provides (m- k)*Vref/(m-l) Volt, whereby k is an integer in the range of 1 up to m, and m is an integer larger than 1.

First the condition that m is an even number is considered. A ladder node Ln_k with k in the range of (m/2) +1 up to m has a lower voltage than Vref/2. For said ladder node Ln_k the Kirchoff current law equation is stated:

I_Rsk = 2*lRL_k + I_Rsk_i (3)

In this equation I_Rsk refers to the current through the first resistive element 110 coupled between ladder node Ln_k and Ln_k+1, l_RSk-i to the current through the first resistive element 110 coupled between ladder node Ln_k and Ln_k-1 and I_RI^ to the current through a series coupling of a second resistive element 160 and a third resistive element 240 or the current through a series coupling of a fourth resistive element 260 and fifth resistive element 340, both series couplings coupled to node Ln_k.

Since the voltage between two consecutive ladder nodes 101 Ln_k and Ln_k-1 is Vref/(m-l) the relation between the resistance values Rsk and R_L for k in the range of (m/2 +1) up to m, resulting from equation (3) is given by:

(Vref/(m-l))/Rs_k = (Vref/(m-l))/Rs_k-1 + (Vref/2 - (m-k)*Vref/(m-l))/R_L

or after rearranging:

1/Rs_k= (k-(l+m)/2)/R_L +1/Rs_k_i (4)

with k in the range of (m/2) +1 up to m. Because of symmetry in the resistor ladder 170 for the resistance value of the first resistive element 110 coupled to ladder nodes 101 Ln_k with k in the range of 1 up to (m/2) -1 it is found that Rs_k = Rs_(m__k). The resistance value of the first resistive element 110 between ladder nodes Ln_(m/2) and Ln_(m/2)+l is simply chosen. To minimize the current through the resistor ladder the value of Rs(m/2) must be chosen as large as possible, and even a value of infinity, that is omitting this first resistor, is a valid solution.

When m is an odd number there is one ladder node 101, Ln_(m-l)/2, with a node voltage that equals Vref/2 and the resistance value of the first resistive elements 110 Rs_(m_i_)/2 and Rs_(m+i_)/2 are both simply chosen. For first resistive elements 110 coupled to the ladder nodes 101 Ln_k with k in the range of (m+l)/2 up to m the resistance value is given by equation (4). For first resistive elements 110 coupled to the ladder nodes 101 Ln_k with k in the range from 1 to (m-l)/2 the resistance value is given by Rsk = Rs(_m_k).

Each one of the resistive elements used in the embodiments of fig. 1 up to 9 and referred to in the claims may comprise one or more resistors.

Due to spread in a production process the actual realized resistance values will deviate from the intended resistance values. Therefore resistance values that were meant to be equal will have small differences, and the realized resistance values will be substantially equal. Another cause of difference between the actual and intended resistance value is that the calculated resistance values may result in a number that is rounded to an integer value. This rounded resistance value will deviate slightly from the exact calculated resistance value. Impedances that are substantially equal may not have exactly equal resistance value, but might be slightly different. A resistive element of which the resistance is chosen to be zero Ohm will result in a resistive element having a resistance that is substantially equal to zero Ohm. The resistance will not be exactly equal to zero Ohm as the minimal resistance that can be obtained will be the resistance of the metal tracks to the resistive element.

The first voltage source 180, the second voltage source 190, the third voltage source 140, the fourth voltage source 130, the voltage source coupled to the first analogue input 150 and the voltage source coupled to the second analogue input 151 are referred to ground.

Each one of the embodiments of fig. 1 up to 9 may be realized in an integrated circuit implementation as well as by using discrete components, or a combination of discrete components and integrated circuits.

The invention relates to a flash analogue to digital converter comprising a first analogue input 150 and a plurality of series connected first resistive elements 110 forming a resistor ladder 170, the resistor ladder 170 having a first ladder terminal 105, a second ladder terminal 106 and a plurality of ladder nodes 101. With the resistor ladder 170 coupled with the first ladder terminal 105 to a reference voltage and with the second ladder terminal 106 coupled to ground the maximal input voltage coupled to the first analogue input 150 exceeds the reference voltage and the minimal input voltage coupled to the first analogue input 150 is lower than the ground potential, thereby realizing an enlarged input voltage range. The first resistive elements 110 have not all an equal resistance.

Claims

CLAIMS:

1. A flash analogue to digital converter for conversion of an analogue input signal into a digital output code (300), the converter comprising m comparators (100), m being an integer larger than 1, each one of the comparators (100) comprising a first comparator input (104) and a comparator output (103), the comparator outputs (103) being arranged for providing the digital output code (300), a first analogue input (150) for receiving the analogue input signal, a plurality of series connected first resistive elements (110) forming a resistor ladder (170), the resistor ladder (170) having a first ladder terminal (105) and a second ladder terminal (106), the resistor ladder (170) having a plurality of ladder nodes (101) located at the connections between the first resistive elements (110) and at the first and second ladder terminal (105, 106), a first voltage source (180) coupled to the first ladder terminal (105), a second voltage source (190) coupled to the second ladder terminal (106), a plurality of second resistive elements (160), - a plurality of third resistive elements (240), the converter having the ladder nodes (101) numbered starting with ladder node Ln_l connected at the first ladder terminal (105) up to ladder node Ln_(m+2) connected at the second ladder terminal (106), and the comparators (100) numbered from A_l up to A_m, the converter having the first comparator input (104) of comparator Aj coupled through one of the second resistive elements (160) to the ladder node Ln_(j+1) and through one of the third resistive elements (240) to the first analogue input (150) and whereby j is an integer ranging from 1 to m, characterised in that the resistance value of the first resistive elements (110), the second resistive elements (160) and the third resistive elements (240) is chosen such that in the absence of the analogue input signal the voltage at the first comparator input (104) of comparator A_l is larger than ((m+2)Vl + mV2) / (2m+2) and the voltage at the first comparator input (104) of comparator A_m is smaller than (Vl+V2(l+2m)) / (2m+2).

2. A flash analogue to digital converter according to claim 1 wherein the resistance value of the first resistive element (110) between the ladder node Ln_l and the ladder node Ln_2 and the resistance value of the first resistive element (110) between the ladder node Ln_(m+1) and the ladder node Ln_(m+2) is substantially equal to zero Ohm.

3. An analogue to digital converter according to claim 1 or 2 wherein m is an even number and each two consecutive first resistive elements (110) in the resistor ladder

(170) have different resistance values.

4. An analogue to digital converter according to claim 1 or 2 wherein m is an odd number and wherein (m-l)/2 pairs of first resistive elements (110) have a substantially equal resistance and the resistance values of the first resistive elements (110) of different pairs are different.

5. An analogue to digital converter according to claim 1 or 2 wherein the value of the first resistive elements (110), the second resistive elements (160) and the third (240) resistive elements is chosen such that the impedance at each one of the first comparator inputs (104) is substantially equal.

6. An analogue to digital converter according to claim 1 or 2 wherein the converter further comprises a cable with a characteristic impedance coupled to the first analogue input (150) and wherein the value of the first (110), the second (160) and the third (240) resistive elements is chosen such that the input impedance of the first analogue input (150) matches the characteristic cable impedance.

7. An analogue to digital converter according to claim 1 wherein the converter further comprises a second analogue input (151) and the converter is arranged for receiving a differential analogue input signal coupled to the first analogue input (150) and to the second analogue input (151), the converter further comprising a plurality of fourth resistive elements (260) and a plurality of fifth resistive elements (340), each one of the comparators (100) further comprising a second comparator input (107), the converter having the second comparator input (107) of comparator Aj coupled through one of the fourth resistive elements (260) to the ladder node Ln_(m-j+2) and through one of the fifth resistive elements (340) to the second analogue input (151) whereby the resistance values of the first resistive elements (110), the second resistive elements (160), the third resistive elements (240), the fourth resistive elements (260) and the fifth resistive elements (340) are chosen such that in the absence of the differential analogue input signal the voltage at the first comparator input (104) of comparator A_l and the second comparator input (107) of comparator A_m is larger than ((m+2)Vl + mV2) / (2m+2) and the voltage at the first comparator input (104) of comparator A_m and the second comparator input of comparator A_l is smaller than (Vl+V2(l+2m)) / (2m+2).

8. A flash analogue to digital converter according to claim 1 wherein the resistance value of the first resistive element (110) between the ladder node Ln_l and the ladder node Ln_2 and the resistance value of the first resistive element (110) between the ladder node Ln_(m+1) and the ladder node Ln_(m+2) is substantially equal to zero Ohm.

9. An analogue to digital converter according to claim 1 wherein the converter further comprises a second analogue input (151) and the converter is arranged for receiving a differential analogue input signal coupled to the first analogue input (150) and to the second analogue input (151), the converter further comprising a plurality of fourth resistive elements (260), a plurality of fifth resistive elements (340) and a further resistor ladder (171), the further resistor ladder (171) having a plurality of series connected first resistive elements (110), a third ladder terminal (109) and a fourth ladder terminal (108), the fourth ladder terminal (108) being coupled to the second voltage source (190) and the third ladder terminal (109) being coupled to the first voltage source (180), the further resistor ladder (171) having a plurality of further ladder nodes (102) located at the connections between the first resistive elements (110) and at the third and fourth ladder terminals (109, 108), each one of the comparators (100) further comprising a second comparator input (107), the converter having the further ladder nodes (102) numbered starting with ladder node Ln_(m+3) connected at the third ladder terminal (109) up to ladder node Ln_(2m+4) at the fourth ladder terminal (108), the converter further having the second input (107) of comparator Aj coupled through one of the fourth resistive elements (260) to the ladder node Ln_(2m+4-j) and through one of the fifth resistive element (340) to the second analogue input (151), whereby the resistance values of the first resistive elements (110), the second resistive elements (160), the third resistive elements (240), the fourth resistive elements (260) and the fifth resistive elements (340) are chosen such that in the absence of the differential analogue input signal the voltage at the first comparator input (104) of comparator A_l and the second comparator input (107) of comparator A_m is larger than ((m+2)Vl + mV2) / (2m+2) and the voltage at the first comparator input (104) of comparator A_m and the second comparator input of comparator A_l is smaller than (Vl+V2(l+2m)) / (2m+2).

10. A flash analogue to digital converter according to claim 9 wherein the resistance value of the first resistive element (110) between the ladder node Ln_l and the ladder node Ln_2, the resistance value of the first resistive element (110) between the ladder node Ln_(m+1) and the ladder node Ln_(m+2), the resistance value of the first resistive element (110) between the ladder node Ln_(m+3) and the ladder node Ln_(m+4), the resistance value of the first resistive element (110) between the ladder node Ln_(2m+3) and the ladder node Ln_(2m+4) is substantially equal to zero Ohm.

11. An analogue to digital converter according to claim 7, 8, 9 or 10 wherein the value of the first (110), second (160), third (240), fourth (260) and fifth (340) resistive elements is chosen such that the impedance at each one of the first comparator inputs (104) and at each one of the second comparator inputs (107) is substantially equal.

12. An analogue to digital converter according to claim 7, 8, 9 or 10 wherein m is an even number and each two consecutive first resistive elements (110) in the resistor ladder (170) have different resistance and each two consecutive first resistive elements (110) in the further resistor ladder (171) have different resistance values.

13. An analogue to digital converter according to claim 7, 8, 9 or 10 wherein m is an odd number and wherein (m-1) pairs of first resistive elements (110) have a substantially equal resistance and the resistance values of the first resistive elements (110) of different pairs are different, m being an integer larger than 1.

14. An analogue to digital converter according to claim 7, 8, 9 or 10 wherein the converter further comprises a first cable with a first characteristic impedance coupled to the first analogue input (150) and a second cable with a second characteristic impedance coupled to the second analogue input (151) and wherein the value of the first (110), second (160), third (240), fourth (260) and fifth (340) resistive elements is chosen such that the input impedance of the first analogue input (150) of the converter matches the first cable impedance and the input impedance of the second analogue input (151) matches the second cable impedance.