WO2007132741A1

WO2007132741A1 - Dma control device

Info

Publication number: WO2007132741A1
Application number: PCT/JP2007/059691
Authority: WO
Inventors: Masaaki Harada
Original assignee: Panasonic Corporation
Priority date: 2006-05-11
Filing date: 2007-05-10
Publication date: 2007-11-22
Also published as: JP2009175774A

Abstract

It is possible to solve the problem that when start registers are integrated into one register in order to reduce the number of software processing steps, it is impossible to limit a start of each master by an address. Provided is a DMA control device in which when controlling start of DMA having a plurality of channels by one start control register, the channels are divided into some groups and upon a start request, a group ID for identifying a group and a channel ID in the group are specified. An access control management table (310) contains a processor operation mode whose start can be controlled for each of groups. A control register management unit (311) performs control to permit or inhibit access to the start control register from a CPU (302) according to a group ID (119) specified upon access to a register from the CPU (302), a processor operation mode (322), a value of control setting (118), and information in an access control management table (310).

Description

Specification

DMA controller

Technical field

[0001] The present invention relates to a DMA control device, and more particularly to the realization of a secure mechanism in a system LSI for digital AV equipment.

Background art

[0002] Currently, as LSI (Large Scale Integrated circuit) is becoming more advanced and highly integrated, multiprocessor systems composed of multiple processors are becoming common. In the field of digital AV home appliances, etc., various applications are executed, and in order to protect the copyright of content and personal information, encryption and decryption processing of confidential data is secured. It is essential to do it.

[0003] Therefore, in order to reduce the CPU load, data transfer is generally performed using a direct memory access (DMA) control device in order to encrypt and decrypt secret data. In that case, it is necessary to prevent unauthorized transfer of confidential data.

[0004] In Patent Document 1, by limiting the accessible processors to a plurality of control registers mapped to different addresses, if a DMA activation register is provided for each channel, activation is performed for each channel. A mechanism is disclosed that allows the possible masters to be restricted. In other words, by restricting the masters that can be accessed for each address, it is possible to limit access to DMA controller resources.

FIG. 12 shows a DMA control device described in Patent Document 1. First, the general operation of the DMA controller 805 will be described. The DMA control device 805 controls data transfer between the peripheral circuit 123 and the memory 122 and data transfer between the cryptographic engine 121 and the memory 122 according to an instruction from the CPU 302.

[0006] The CPU 302 sets DMA control parameters such as a transfer source, a transfer destination, and a transfer size in each channel (ch) control register 812b in the control register 812, and then instructs the start register 812a to start DMA, that is, transfer start To do. [0007] The DMA controller 805 selects which channel to perform transfer from among the activated multiple channels by the arbitration unit 113, and the execution unit 107 selects the channel based on the DMA control parameter of the selected channel. Perform data transfer.

[0008] Further, when performing highly confidential processing such as content copyright protection processing, the CPU 302 performs processing by transitioning to the secure mode. Programs executed in the secure mode are protected from being tampered with or seen by malicious persons. When the CPU 302 operates in the secure mode, unauthorized processing is prevented. Access to the registers of the DMA controller 805 When this is done, the processor operating mode 322 is output to notify that the register access is in the secure mode.

Next, features of the DMA control device 805 of Patent Document 1 will be described. Here, of the DMA channels from channels 0 to 16, channel 16 (chl6) is a dedicated DMA channel for secure use, and transfer between the cryptographic engine 121 and the memory 122 is possible. It is assumed that data transfer cannot be performed.

[0010] The activation registers 812a of each channel are mapped to different addresses, and the access enable / disable information holding unit 810 holds the processor operation mode as master attribute information accessible to each of the activation registers. Based on the access request to the activation register 812a issued by the CPU 302 and the processor operation mode 322 at that time, the access determination unit 811 determines whether or not the CPU 302 can access the activation register of the access request destination.

[0011] Channel activation register 812a is accessed only when the determination result indicates that access is permitted. In the example shown in Fig. 12, the CPU 302 can only access 0x00 (chO start register) to 0x3c (chl5 start register) in normal mode and cannot access 0x40 (chl6 start register).

On the other hand, the CPU 302 can access all 0x00 to 0x40 in the secure mode! Therefore, the CPU 302 cannot start data transfer with the cryptographic engine 121 in the normal mode, but can start only in the secure mode.

FIG. 13 is a flowchart showing an example of the process of Patent Document 1.

Step S901: The CPU 302 transfers the transfer source address and transfer destination to the channel control register 812b. Set various DMA control parameters such as address and transfer size.

Step S902: For a channel for which a DMA control parameter has been set, a start request is set to instruct the start register 812a to start transfer. If there are multiple channels to be activated here, multiple activation registers will be set.

[0015] Step S903: The access permission determination unit 811 holds the access permission information holding unit 810 and requests access based on the master attribute information accessible to each address! It is determined whether or not access to the activation register 812a is permitted.

[0016] Step S904: When there are a plurality of activated channels with access permission, the arbitration unit 1

13! Decide which of the channels you want to transfer.

Step S905: Based on the DMA control parameter of the channel that has acquired the right by arbitration, the execution unit 107 controls data transfer to the transfer source and transfer destination.

[0018] Step S906: It is determined whether there is still data to be transferred! /, And if it is not completed, it becomes the object of arbitration again and S904 and subsequent steps are repeated. If completed, perform a specified completion process such as asserting a transfer completion interrupt request.

[0019] In Patent Document 1, when it is determined in S903 in the DMA control device 805 that the permission is not permitted, the above description is omitted.

[0020] Here, the channel in the DMA controller refers to the hardware resources necessary to hold the DMA parameter. If there are multiple channels, multiple DMA parameters can be set and started. As a software, it is possible to execute multiple types of transfers simultaneously.

[0021] In general, a DMA control device includes a plurality of channels, and software activates a plurality of DMA transfers according to the execution status of an application, and hardware performs data transfer control in time division or in parallel. Do.

[0022] Patent Document 1: Pamphlet of International Publication No. 05/121979

Disclosure of the invention

Problems to be solved by the invention

[0023] However, in the mechanism of Patent Document 1, if a large number of channels are required, the activation register for each channel must be set individually at the time of activation request! /, And the software processing step is required. It becomes an increase factor. In addition, the number of activation registers increases in proportion to the increase in the number of channels, which increases the circuit scale.

[0024] Therefore, if the start register is integrated into a single register in order to reduce software processing steps and suppress an increase in circuit scale, it becomes impossible to restrict access for each master by address.

[0025] If it is necessary to increase the number of secure DMA channels during system expansion, the mechanism of Patent Document 1 requires that all secure DMA channels be mapped to secure IO space addresses. It is necessary to expand the secure IO space, which may cause incompatibility with the conventional system.

[0026] The present invention has been made in view of the above-described conventional circumstances, and provides a DMA control device that can reduce software processing steps, suppress an increase in circuit scale, and maintain security. For the purpose of doing.

Means for solving the problem

[0027] A DMA control device according to the present invention is a DMA (Direct Memory Access) control device that controls data transfer between a peripheral circuit and a memory in accordance with an instruction of processor power, and is a single mapped to one address. A channel control register that controls multiple DMA channels using the start control register, and an access that stores the channel ID of the start DMA channel and controllable processor information that indicates whether the processor can start the DMA channel in association with each other. Based on a comparison between the control management table, the processor operation mode notified to the processor power and the setting value in the activation control register, and the channel ID and controllable processor information held in the access control management table. Then, the determination of whether to prohibit the force to permit access to the start control register is performed V, And a control register management unit that notifies a control request to the activation control register when to allow access.

[0028] According to the above configuration, access control is possible with one activation control register, so that it is possible to reduce software processing steps, suppress an increase in circuit scale, and maintain security.

[0029] Further, the DMA control device according to the present invention has a plurality of the channel control register powers. The access control management table 1S holds the channel ID of the DMA channel included in the group for each group ID that identifies the group, and the control register management unit Based on the group ID to which the DMA channel belongs and the controllable processor information for each of the loop IDs held in the access control management table, access to the activation control register is permitted. Whether to do or not.

[0030] According to the above configuration, since a plurality of channels can be classified into groups and access can be restricted for each group, it is possible to cope with an increase in the number of channels without increasing the number of bits of the activation control register.

The invention's effect

[0031] According to the DMA control device of the present invention, since access restriction can be realized with a small number of registers, it is possible to maintain security while reducing software processing steps at the time of DMA activation request.

Brief Description of Drawings

FIG. 1 is a configuration diagram of a DMA control circuit according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing a processing example of the DMA control circuit according to the first embodiment of the present invention.

FIG. 3 is a diagram showing an example of an access control management table according to the first embodiment of the present invention (1)

FIG. 4 is a configuration diagram of a DMA control circuit according to a second embodiment of the present invention.

FIG. 5 is a configuration diagram of a DMA control circuit according to a third embodiment of the present invention.

FIG. 6 is a diagram showing an example of an access control management table according to the third embodiment of the present invention (

2)

FIG. 7 is a diagram showing an example of an access control management table in the third embodiment of the present invention (3)

FIG. 8 is a diagram showing an example of a start control register according to the third embodiment of the present invention.

FIG. 9 is a configuration diagram of a DMA control circuit according to a fourth embodiment of the present invention.

FIG. 10 is a configuration diagram of a DMA control circuit according to a fifth embodiment of the present invention. FIG. 11 is a flowchart showing a processing example of the DMA control circuit according to the fourth and fifth embodiments of the present invention.

[Figure 12] Configuration of conventional DMA control circuit

FIG. 13 is a flowchart showing a processing example of a conventional DMA control circuit.

Explanation of symbols

22 Processor operating modes

32, 32a, 32b Register access

102 CPU

105 DMA controller

106 Channel controller

107 execution unit

108 Host IF

110 Access control management table

111 Control register management

112 Channel control register

112a Startup control register

112b Channel control register

113 Mediation Department

115 Processor identification information

116 Control request

118 Control setpoint

119 Group ID

121 Engine # 12

122 memory

123 Peripheral circuit

302 CPU

305 DMA controller

306 Channel controller 310 Access control management table

315 Processor identification information

322 Processor operating mode

403 CPU1

405 DMA controller

406 Channel controller

410 Access control management table

415 Processor identification information

505 DMA controller

506 channel controller

512b chl6 control register

523 Transfer completion notification means

524 judgment result

525 Transfer completion interrupt

526 chl6 transfer size

605 DMA controller

606 channel controller

624 judgment result

625 error interrupt

805 DMA controller

806 Channel controller

810 Access control management table

812 Channel control register

BEST MODE FOR CARRYING OUT THE INVENTION

[0034] Hereinafter, embodiments of the invention according to each claim will be described with reference to the drawings.

[Embodiment 1]

The operation of the DMA control apparatus according to the first embodiment of the present invention will be described with reference to FIGS. [0036] The DMA control apparatus 105 according to the first embodiment includes one activation control register 112a as the channel control register 112, and is mapped to one address. Also, multiple DMA channels are controlled by classifying them into multiple groups.

[0037] In the example of FIG. 1, the DMA channels (chO to chl5) classified into group 0 and group 1 can be activated in the normal mode by the CPU 102, and the DMA channels belonging to group 1 (chl6, chl7) can be started only when CPU102 is in secure mode.

[0038] The CPU 102 has a secure mode for performing confidential processing. When accessing the activation control register 112a, the CPU 102 sets the group ID 119 and the activated channel information as the control setting value 118, The CPU 102 outputs the processor operating mode 22 indicating whether the CPU 102 is in the secure mode or the normal mode.

[0039] The host IF 108 receives the register access 32 and the processor operation mode 22 from the CPU 102, and notifies the control register management unit 111 of the operation mode as the processor identification information 115.

[0040] The access control management table 110 holds processor information accessible to the activation control register 112a for each group ID, and the control register management unit 111 uses the group HD information 119 of the access request destination channel from the CPU 102, Access to the start control register 112a is based on the processor identification information 115 from the host IF 108 and the control information that can be controlled (startable) for each group ID held in the access control management table 110. Judgment of whether to prohibit the force.

[0041] In the access control management table 110 of FIG. 1, the DMA transfer of channels 0 to 15 can be started only when the group ID 119 is 0 and the processor identification information 115 is only allowed in the normal mode, and the channel 16 17 means that access is permitted only when the group ID 119 is 1 and the processor identification information 115 is in the secure mode. As a result of the determination, the control request management unit 111 notifies the control request 116 to the channel control register 112 only when access is permitted.

Next, register access restriction processing in the DMA control apparatus 105 in the present embodiment will be described. FIG. 2 is a flowchart showing an example. The difference from Figure 9 is S Only 202 and S203.

Step S202: For the channel for which the DMA control parameter is set, a start request is set to instruct the start control register 112a to start transfer. Even when there are multiple channels to be activated here, only one activation control register is set, and the group ID 119 and the activated channel information are set as the control setting value 118.

[0044] Step S203: The control register management unit 111 holds the request in the access control management table 110 based on the processor information that can be activated for each group ID! It is determined whether or not access to the start control register 112a is permitted.

[0045] As described above, it is possible to limit the activation of channels belonging to a specific group among a plurality of channels only from processors that satisfy the conditions.

Here, the control register for restricting access has been described as the activation control register 112a. However, other channel control registers such as a register for requesting interruption or restart may be used. Further, various settings such as a transfer source address, a transfer destination address, and a transfer size for the channel control register 112b are not necessarily required and may be fixed in hardware.

[0047] In addition, Fig. 1 shows an example in which channels belonging to group 0 and group 1 have consecutive channel numbers from chO to chl5, chl6, and chl 7, respectively. , Chl 7 may be non-contiguous channel numbers.

FIG. 3 shows table information of the access control management table 110 when access is restricted for each group. In the example of Fig. 3 (a), a DMA channel whose group ID belongs to 0 can be activated in CPU normal mode, and a DMA channel whose group ID belongs to 1 can only be activated in CPU secure mode. It means that it is possible.

In FIG. 3 (b), the channel for secure data transfer is arranged at the end (16, 17) of the serial number of the channel ID (0, 1, 2,... • 16, 17). Fig. 3 (c) shows a case where channels for secure data transfer are selected by non-consecutive numbers (0, 17) and the channels are grouped into a secure gnole (gnole ID 1).

As described above, the DMA control device 105 according to the embodiment of the present invention transfers data between the cryptographic engine 121 and the peripheral circuit 123 and the memory 122 in accordance with an instruction from the processor 102. The DMA controller 105 that controls the channel control register 1 12 that controls a plurality of DMA channels by one start control register 112a mapped to one address, and the channel ID of the DMA channel to be started and the processor 102 Access control management table 110 that stores the controllable processor information that indicates whether the DMA channel can be activated or not, and the setting value in the processor operation mode 22 and the activation control register 112a notified from the processor 102 And whether access to the boot control register 112a is permitted or prohibited based on the comparison between the channel ID and the controllable processor information held in the access control management table 110, Control register management unit 11 1 for notifying control request 116 to start control register 112a when Therefore, access restriction can be realized by one activation control register 112a, and security can be maintained while reducing software processing steps at the time of DMA activation request.

[0051] In the DMA control device 105 of the present embodiment, the channel control register 112 controls a plurality of DMA channels by classifying them into a plurality of groups, and the access control management table 110 includes a group ID for identifying the group. Each channel holds the channel ID of the DMA channel included in the group, and the control register management unit 111 holds the group ID to which the DMA channel belongs and the access control management table 110 to control each group ID. Based on the available processor information, it is determined whether access to the start control register 112a is permitted or prohibited. Therefore, a plurality of DMA channels can be classified into a plurality of groups and controlled. Among them, the activation of channels belonging to a specific group can be limited to only those processor powers that satisfy the conditions.

In addition, the DMA control device 105 of the present embodiment accepts the register access 32 and the processor operation mode 22 notified from the processor 102, and performs control setting including the group ID 119 to which the DMA channel to be activated belongs, and the channel information to be activated. Since it has the host IF108 that notifies the control register management unit 111 of the value 118, it is possible to manage the channel information to be activated in groups, and to maintain security while reducing the software processing steps when DMA activation is requested. it can.

[0053] Also, in the DMA control device 105 of the present embodiment,! / Since 102 includes the first group that can be activated in the normal mode and the second group that can be activated in the secure mode for the processor 102 to perform confidential processing, the normal mode and the secure mode must be managed as a group. Security can be maintained while reducing software processing steps when DMA activation is requested.

[0054] Further, in the DMA control device 105 of the present embodiment, the numbers of the DMA channels belonging to the group include a continuous number and a non-consecutive number. It can be managed by number, and the burden of software processing can be reduced.

[Embodiment 2]

The operation of the DMA control apparatus according to the second embodiment of the present invention will be described with reference to FIG. Here, the description will focus on differences from the operation of the DMA control apparatus according to the first embodiment.

[0056] In this embodiment, the CPU 302 notifies the processor operation mode including the security level corresponding to the processing content in the secure mode, in addition to notifying whether the mode is the secure mode or the normal mode. For example, it may be considered that the encryption processing of billing information for paid services is positioned at a higher security level than the decryption processing of the program processed by the processor.

The host IF 308 notifies the control register management unit 311 of the processor operation mode 322 notified from the CPU 302 as the processor identification information 315. Group 0 (chO to chl 5) is used for normal use, Group 1 (chl6) is used for security level 0, Group 2 (chl7) is used for security level 1, and security level 1 is more confidential than security level 0. To do. For example, a case where accounting information data transfer is possible only in chl7 belonging to group 2 can be considered.

[0058] The access control management table 310 stores, as processor information that can be activated for each group ID, whether the mode is the normal mode or the secure mode (security level 0) and the secure mode (security level 1).

[0059] Here, the gnole IDO DMA channel can be activated in normal mode, and the gnole 1 DMA channel can only be activated in secure mode (security level 0). It is assumed that the loop 2 DMA channel can only be activated in secure mode (security level 1).

[0060] The control register management unit 311 includes group I and f blueprint 119 of the access request destination channel from the CPU 302, processor identification information 315 indicating the operation mode (including the security level) of the processor from the host IF 308, access control management Based on the information of the bootable processor information for each group ID held in the table 310, it is determined whether or not to allow access to the boot control register 112a.

As described above, the DMA transfer with the cryptographic engine 121 that handles the billing information can be activated only when the CPU 302 is performing security level 1 processing in the secure mode.

As described above, according to the DMA control device 305 of the present embodiment, the processor 302 notifies the host IF 308 of the security level corresponding to the processing content in the secure mode, and the access control management table 310 Since the security level is stored for each group ID, DMA transfer with the cryptographic engine 121 that handles accounting information can be activated only when the processor 302 is processing security level 1 in secure mode. The security level can be improved.

[0063] (Embodiment 3)

The operation of the DMA control apparatus according to the third embodiment of the present invention will be described with reference to FIG. Here, the description will focus on differences from the operation of the DMA control device according to the first and second embodiments.

[0064] DMA controller 405 in the present embodiment is controlled by a plurality of processors.

Here, it is assumed that control is performed by CPUO 102 and CPU1 403, and data transfer with cryptographic engine 121 is possible only by CPUO. Also, this embodiment differs from the first and second embodiments in that access is restricted for each channel rather than for each group.

[0065] The host IF 408 identifies whether the access is from CPUO 102 or CPU1 403 (whether it is the register access 32a from CPUO 102 or the register access 32b from CPU1 403), and the identification result is sent to the processor. Control register management as identification information 415 Notification to Part 411.

[0066] The access control management table 410 stores whether the processor that can be activated for each channel is only the CP UO, the power of only the CPU 1, or both of the CPU O and 1. Here, chO and 17 can be started only by CPUO, and the other channels can be started by both CPU0 and 1.

[0067] The control register management unit 411 includes the group ID information 119 of the access request destination channel from the CPU 102 or the CPU 403, the processor identification information 415 indicating which processor the host IF 408 is accessing from, and the host IF 408 Based on the information of the control setting 118 and the startable processor information for each channel held in the access control management table 410, it is determined whether or not to permit access to the start control register 112a. As described above, DMA transfer with the cryptographic engine 121 can be activated only by the CPUO.

FIG. 6 shows an access control management table 11 when access is restricted for each channel.

Indicates 0 table information. In the example in the figure, it means that channel ID 0 and channel ID 17 can be activated only in CPU secure mode.

[0069] FIG. 7 shows table information in the case of managing access permitting activation according to the secure level of the CPU secure mode. In the example in the figure, the concept of secure level is introduced based on Fig. 6. Security level

Secure (Level 1)> Secure (Level 0)> Normal

Then, it becomes possible to transfer data with higher secrecy only with channel ID17.

[0070] In addition, the DMA control device according to the present embodiment specifies a field for specifying a loop ID as the specification of the start control register and which channel to start from among the channels belonging to the specified group. Have a field to do. For example, as shown in Figure 8, there may be a form in which the upper 4 bits of the 32-bit start control register are used as a group ID designation field and the lower 16 bits are used as a channel designation field.

Note that CPU0 and CPU1 have a secure mode as in the first embodiment, and the access control management table 410 has the operation mode of CPU0 and CPU1 as controllable processor information. There may be a form of managing the mode.

As described above, according to the DMA control device 405 of the present embodiment, the host IF 408 identifies from which of the plurality of CPUs 102 and 403 the access is made, and the identification result is used as the processor identification information 415. The control register management unit 411 holds controllable processor information for each channel ID, and the control register management unit 411 holds for each channel ID held in the access control management table 410. Based on the controllable processor information, it is determined whether access to the activation control register 112a is permitted or prohibited. For example, only the CPU 102 can activate DMA transfer with the cryptographic engine 121. it can.

[0073] (Embodiment 4)

The operation of the DMA control apparatus according to the fourth embodiment of the present invention will be described with reference to FIGS. Here, the description will focus on the differences from the operation of the DMA controller according to the first to third embodiments.

[0074] If the determination result in the control register management unit 111 is that the access to the channel control register 112 is prohibited, the DMA controller 505 in the present embodiment, for example, the channel 16 (chl6) belonging to the group 1 in the normal mode. ), The control register management unit 111 notifies the determination result 524 to the transfer completion notification means 523, and the chl6 control register 512b notifies the transfer completion notification means 523 of the transfer size 526 set by the CPU 102. When the determination result 524 indicates that access is prohibited, the transfer completion notification means 523 waits for the time required for actual data transfer based on the size indicated by the transfer size 526, and then transfers the transfer completion interrupt 525 to the CPU 102. Notify

[0075] As a method of determining the waiting time, a method may be considered in which the waiting time per unit size is determined in advance and the waiting time corresponding to the size indicated by the transfer size 526 is calculated based on the waiting time. .

FIG. 11 is a flowchart showing an example thereof. The only difference from Figure 2 is S707.

[0077] Step S707: If it is determined that access is not permitted based on the determination in step S203, the CPU 102 is notified that the transfer has been completed. As a result, malicious DM It becomes possible for the person who started A to realize that he / she was unable to transfer.

As described above, according to the DMA control device 505 of the present embodiment, when the determination result 524 in the control register management unit 111 indicates that access to the channel control register 112 is prohibited, the transfer set by the processor 102 is performed. Based on the size 526, it has a transfer completion notification means 523 that notifies the processor 102 of a transfer completion interrupt 525 after waiting for an amount of time required for actual data transfer. It is possible to realize that the person who has been able to transfer can realize it.

[0079] (Embodiment 5)

The operation of the DMA control apparatus according to the fifth embodiment of the present invention will be described with reference to FIG. Here, the description will focus on differences from the operation of the DMA control apparatus according to the first to fourth embodiments.

If the determination result in the control register management unit 111 does not permit access to the register, the DMA control device 605 in the present embodiment receives the determination result 624 in the abnormality processing unit 623 and sends it to the CPU 102. In response, an error interrupt 625 is generated to notify that an illegal DMA activation has occurred. As described above, it is possible to detect that a malicious program is mixed and attempts to start an illegal DMA.

As described above, according to the DMA control device 605 of the present embodiment, when the determination result 624 in the control register management unit 111 indicates that access to the channel control register 112 is prohibited, the determination result 624 is received. Since it has an error processing unit 623 that generates an error interrupt 625 that notifies the processor 102 that an illegal DMA activation has occurred, it means that a malicious program was mixed in and attempted to activate the illegal DMA. It can be detected.

In the third embodiment, the example of the activation control register described with reference to FIG. 8 is the same as the example of the activation control register shown in FIG. , 4, 5, 6).

[0083] What has been described in the above embodiments is the matter included in the following technical idea.

[0084] Upon receiving a bus access from the processor, the DMA control device according to the present invention identifies processor information, outputs the identification result as processor identification information, Processor power Host IF that outputs DMA channel activation request, transfer source, transfer destination, transfer size, and other control settings corresponding to the activation request, and channel control that retains and updates the control settings as necessary A DMA (Direct Memory Access) control device that has a register and sequentially selects and executes one of the requested DMA channels as required. The DMA control device is controlled by control settings. An access control management table that stores control setting values and processor information that can be controlled using the setting values, and the control setting values and controllable processor information in the access control management table. Based on the processor identification information from the host IF and the control settings, the processor requesting control of the DMA channel requested to be controlled can be controlled. It has a control register management unit that determines whether it is capable or not, and transmits an access request to the channel control register only when it is determined that control is possible.

[0085] Further, the DMA control device according to the present invention is the DMA control device described above, wherein the host IF receives access requests from a plurality of processors and indicates which processor the access request is from. The ID is output as the processor identification information, and the access control management table manages the DMA activation request setting value of the processor power as the control setting value, and the DMA activation request setting as the controllable processor information The processor that allows DMA activation by setting a value is managed as a bootable processor ID, and the control register management unit receives the processor ID and the control setting from the host IF, and the control setting contents Is a DMA channel activation request, based on the activation request setting value in the access control management table and the processor ID that can be activated. Determining access permission.

[0086] Further, the DMA control device according to the present invention is the DMA control device described above, wherein the host IF accepts an access request from a processor having a plurality of operation modes, and the access request in any operation mode. A processor operation mode indicating whether or not there is output as the processor identification information, and the access control management table manages the DMA activation request setting value of the processor power as the control setting value, and as the controllable processor information By setting the DMA activation request setting value, a processor that allows DMA activation is managed as an activatable processor operation mode, and the control register management unit In response to the processor operation mode and the control setting from the list IF, and the control setting content ΜΑ Channel activation request, based on the activation request setting value in the access control management table and the processor operation mode that can be activated Determine whether access is possible.

[0087] Also, the DMA control device according to the present invention is the above-described DMA control device, which controls a plurality of DMA channels classified into a plurality of groups, and the processor requests DMA activation by an access request. In this case, a control target channel is specified by a group ID that specifies the group and an intra-group channel ID that specifies a DMA channel in the group, and the access control management table uses the group as the DMA activation request setting value. Manage IDs.

[0088] Further, the DMA control device according to the present invention is the above-described DMA control device, wherein the access control management table manages the group ID and the intra-group channel ID as the DMA activation request setting value. .

[0089] Also, the DMA control device according to the present invention is the above-described DMA control device, and when the processor requests DMA activation by an access request, which of the plurality of channels is activated. The channel to be controlled is specified by the channel ID that identifies the channel ID, and the access control management table manages the channel ID as the DMA activation request setting value.

Further, the DMA control device according to the present invention is the above-described DMA control device, comprising transfer completion notification means for notifying the processor that the transfer has been completed when all the designated transfers have been completed. If the determination result of the control register management unit is uncontrollable, the transfer completion is notified to the processor without performing the data transfer.

[0091] Also, the DMA control device according to the present invention is the DMA control device described above, and when the determination result of the control register management unit is uncontrollable, the data transfer is not performed and the transfer described above is performed. The completion notification means controls the timing for notifying the completion of transfer according to the set transfer size.

Further, the DMA control device according to the present invention is the above-described DMA control device, and when the determination result of the control register management unit is uncontrollable, notifies the processor of an error interrupt at that time. An abnormality processing unit. [0093] Although the invention has been described in detail and with reference to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. is there.

This application is based on a Japanese patent application filed on May 11, 2006 (Japanese Patent Application No. 2006-132162), the contents of which are incorporated herein by reference.

Industrial applicability

By using the DMA controller according to the present invention, it is possible to reliably prevent illegal DMA transfer at startup without depending on the implementation of the startup register of the DMA controller. Therefore, it can be used to improve the security of all digital devices that perform confidential processing, and to reduce software processing steps by integrating start-up registers.

Claims

The scope of the claims

[1] A DMA (Direct Memory Access) control device that controls data transfer between a peripheral circuit and a memory according to instructions from a processor,

A channel control register for controlling a plurality of DMA channels by one start control register mapped to one address;

An access control management table for storing a channel ID of a DMA channel to be activated and controllable processor information indicating whether the processor can activate the DMA channel;

The processor control is based on the processor operation mode notified and the setting value in the activation control register, and the channel ID and controllable processor information held in the access control management table. And a control register management unit that determines whether or not to prohibit access to the register and notifies the start control register of a control request when access is permitted.

[2] The DMA control device according to claim 1,

The channel control register classifies and controls a plurality of DMA channels into a plurality of groups,

The access control management table holds a channel ID of a DMA channel included in the group for each group ID for identifying the group,

The control register management unit accesses the activation control register based on the group ID to which the DMA channel belongs and the controllable processor information for each group ID held in the access control management table. DMA controller that determines whether or not the force to allow is prohibited.

[3] The DMA control device according to claim 2,

A DMA having a host IF that accepts a register access and a processor operation mode notified from the processor and notifies a control setting value including a group ID to which the DMA channel belongs and channel information to be activated to the control register management unit Control device.

[4] The DMA control device according to claim 2, The plurality of groups includes a first group in which the processor can be started in a normal mode;

And a second loop that can be activated in a secure mode for performing confidential processing by the processor.

[5] The DMA control device according to claim 2,

The number of DMA channels belonging to the group includes a continuous number and a non-consecutive number.

[6] The DMA control device according to claim 4,

The processor notifies the control register management unit of a security level corresponding to the processing content in the secure mode,

The access control management table is a DMA control device that stores the security level for each group ID.

[7] The DMA control device according to claim 2,

A host IF is provided for identifying whether the access is from one of a plurality of processors and notifying the identification result as processor identification information to the control register management unit, and the control register management unit A DMA control device for determining whether to prohibit access permission to the start control register based on controllable processor information for each group ID held in the access control management table.

[8] The DMA control device according to claim 1,

The control register management unit determines whether to prohibit the force to permit access to the activation control register based on the controllable processor information for each channel ID held in the access control management table. DMA controller.

[9] The DMA control device according to claim 8,

A DMA control device having a host IF that accepts register access and processor operation mode notified from the processor and notifies the control register management unit of control setting values including channel information to be activated.

[10] The DMA control device according to claim 8,

The plurality of channels are channels that the processor can start up in a normal mode; And a channel that can be activated in a secure mode for performing confidential processing by the processor.

[11] The DMA control device according to claim 10,

The DMA control apparatus, wherein the access control management table stores the security level for each channel ID.

[12] The DMA control device according to claim 8,

The access control management table includes a host IF that identifies whether the access is from any of a plurality of processors, and notifies the control register management unit of the identification result as processor identification information. Holds controllable processor information for each channel ID,

The control register management unit determines whether to prohibit access permission to the start control register based on the controllable processor information for each channel ID held in the access control management table. DMA controller to judge.

[13] The DMA control device according to claim 1,

When the determination result in the control register management unit indicates that access to the channel control register is prohibited, the processor waits for the time required for actual data transfer based on the transfer size set by the processor. A DMA control device having transfer completion notification means for notifying the processor of a transfer completion interrupt later.

[14] The DMA control device according to claim 1,

If the determination result in the control register management unit indicates that access to the channel control register is prohibited, an error interrupt that notifies the processor that an illegal DMA activation has occurred in response to the determination result A DMA control device having an abnormality processing unit that generates a fault.