WO2007130832A3 - Boosting voltage technique fpr programming nand flash memory devices - Google Patents

Boosting voltage technique fpr programming nand flash memory devices Download PDF

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Publication number
WO2007130832A3
WO2007130832A3 PCT/US2007/067429 US2007067429W WO2007130832A3 WO 2007130832 A3 WO2007130832 A3 WO 2007130832A3 US 2007067429 W US2007067429 W US 2007067429W WO 2007130832 A3 WO2007130832 A3 WO 2007130832A3
Authority
WO
WIPO (PCT)
Prior art keywords
fpr
flash memory
memory devices
nand flash
boosting voltage
Prior art date
Application number
PCT/US2007/067429
Other languages
French (fr)
Other versions
WO2007130832A2 (en
Inventor
Masaaki Higashitani
Original Assignee
Sandisk Corp
Masaaki Higashitani
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/381,874 external-priority patent/US7286408B1/en
Priority claimed from US11/381,865 external-priority patent/US7436709B2/en
Application filed by Sandisk Corp, Masaaki Higashitani filed Critical Sandisk Corp
Publication of WO2007130832A2 publication Critical patent/WO2007130832A2/en
Publication of WO2007130832A3 publication Critical patent/WO2007130832A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

A floating gate memory array includes row control circuits that provide a programming voltage to a selected word line and provide a stair-like pattern of boosting voltages to unselected word lines. Boosting voltages descend with increased distance from the selected word line. Boosting voltages are increased in small increments up to their final values.
PCT/US2007/067429 2006-05-05 2007-04-25 Boosting voltage technique fpr programming nand flash memory devices WO2007130832A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/381,874 US7286408B1 (en) 2006-05-05 2006-05-05 Boosting methods for NAND flash memory
US11/381,874 2006-05-05
US11/381,865 2006-05-05
US11/381,865 US7436709B2 (en) 2006-05-05 2006-05-05 NAND flash memory with boosting

Publications (2)

Publication Number Publication Date
WO2007130832A2 WO2007130832A2 (en) 2007-11-15
WO2007130832A3 true WO2007130832A3 (en) 2008-01-03

Family

ID=38566883

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/067429 WO2007130832A2 (en) 2006-05-05 2007-04-25 Boosting voltage technique fpr programming nand flash memory devices

Country Status (2)

Country Link
TW (1) TWI350541B (en)
WO (1) WO2007130832A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI750026B (en) * 2021-02-04 2021-12-11 力晶積成電子製造股份有限公司 Flash memory storage apparatus and a biasing method thereof
EP4177891A1 (en) * 2021-11-04 2023-05-10 Samsung Electronics Co., Ltd. Memory device and operation method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5715194A (en) * 1996-07-24 1998-02-03 Advanced Micro Devices, Inc. Bias scheme of program inhibit for random programming in a nand flash memory
US6061270A (en) * 1997-12-31 2000-05-09 Samsung Electronics Co., Ltd. Method for programming a non-volatile memory device with program disturb control
US20020126532A1 (en) * 2001-03-06 2002-09-12 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device
US20040080980A1 (en) * 2002-10-23 2004-04-29 Chang-Hyun Lee Methods of programming non-volatile semiconductor memory devices including coupling voltages and related devices
US20060002167A1 (en) * 2004-06-30 2006-01-05 Micron Technology, Inc. Minimizing adjacent wordline disturb in a memory device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5715194A (en) * 1996-07-24 1998-02-03 Advanced Micro Devices, Inc. Bias scheme of program inhibit for random programming in a nand flash memory
US6061270A (en) * 1997-12-31 2000-05-09 Samsung Electronics Co., Ltd. Method for programming a non-volatile memory device with program disturb control
US20020126532A1 (en) * 2001-03-06 2002-09-12 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device
US20040080980A1 (en) * 2002-10-23 2004-04-29 Chang-Hyun Lee Methods of programming non-volatile semiconductor memory devices including coupling voltages and related devices
US20060002167A1 (en) * 2004-06-30 2006-01-05 Micron Technology, Inc. Minimizing adjacent wordline disturb in a memory device

Also Published As

Publication number Publication date
WO2007130832A2 (en) 2007-11-15
TW200811867A (en) 2008-03-01
TWI350541B (en) 2011-10-11

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