WO2007126495A1 - Technique permettant d'obtenir des sources de stress dans les transistors très rapprochés d'une région canal par l'encastrement des régions de drain et de source - Google Patents

Technique permettant d'obtenir des sources de stress dans les transistors très rapprochés d'une région canal par l'encastrement des régions de drain et de source Download PDF

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Publication number
WO2007126495A1
WO2007126495A1 PCT/US2007/004689 US2007004689W WO2007126495A1 WO 2007126495 A1 WO2007126495 A1 WO 2007126495A1 US 2007004689 W US2007004689 W US 2007004689W WO 2007126495 A1 WO2007126495 A1 WO 2007126495A1
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WIPO (PCT)
Prior art keywords
drain
layer
gate electrode
source regions
channel region
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PCT/US2007/004689
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English (en)
Inventor
Andy Wei
Thorsten Kammler
Jan Hoentschel
Manfred Horstmann
Peter Javorka
Joe Bloomquist
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Advanced Micro Devices, Inc.
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Priority claimed from DE102006015077A external-priority patent/DE102006015077B4/de
Application filed by Advanced Micro Devices, Inc. filed Critical Advanced Micro Devices, Inc.
Priority to CN2007800114369A priority Critical patent/CN101416287B/zh
Priority to JP2009502792A priority patent/JP5576655B2/ja
Priority to KR1020087026877A priority patent/KR101430703B1/ko
Priority to GB0817592A priority patent/GB2449824B/en
Publication of WO2007126495A1 publication Critical patent/WO2007126495A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology

Definitions

  • the present invention relates to the formation of integrated circuits, and, more particularly, to the formation of transistors having strained channel regions by using stress sources, such embedded strained layers, stressed overlayers and the like, to enhance charge carrier mobility in the channel region of a MOS transistor.
  • CMOS complementary metal-oxide-semiconductor
  • N-channel transistors and P-channel transistors are formed on a substrate including a crystalline semiconductor layer.
  • a MOS transistor irrespective of whether an N- channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely doped channel region disposed between the drain region and the source region.
  • the conductivity of the channel region i.e., the drive current capability of the conductive channel
  • the conductivity of the channel region is controlled by a gate electrode formed near the channel region and separated therefrom by a thin insulating layer.
  • the conductivity of the channel region upon formation of a conductive channel, due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the majority charge carriers, and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length.
  • the overall conductivity of the channel region substantially determines the performance of the MOS transistors.
  • the reduction of the channel length, and associated therewith the reduction of the channel resistivity renders the channel length a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
  • One efficient mechanism for increasing the charge carrier mobility is the modification of the lattice structure in the channel region, for instance by creating tensile or compressive stress in the vicinity of the channel region to produce a corresponding strain in the channel region, which results in a modified mobility for electrons and holes, respectively.
  • creating tensile strain in the channel region increases the mobility of electrons, which in turn may directly translate into a corresponding increase in the conductivity.
  • compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors.
  • strained silicon may be considered as a "new" type of semiconductor material, which may enable the fabrication of fast powerful semiconductor devices without requiring expensive semiconductor materials, while many of the well-established manufacturing techniques may still be used.
  • the hole mobility of PMOS transistors is enhanced by forming an embedded strained silicon/germanium layer in the drain and source regions of the transistors, wherein the compressively strained drain and source regions create uniaxial strain in the adjacent silicon channel region.
  • the drain and source regions of the PMOS transistors are selectively recessed, while the NMOS transistors are masked and subsequently the silicon/germanium layer is selectively formed in the PMOS transistor by epitaxial growth.
  • the strained silicon/germanium is provided with a certain degree of "overfill" during the epitaxial growth in order to reduce the consumption of "precious" strained silicon/germanium material during a silicidation process for forming a metal silicide in the drain and source regions for obtaining a reduced contact resistance.
  • this raising of the drain and source regions may reduce the efficiency of the stress transfer of any overlaying layers, if such layers are provided in combination with the embedded strain layer.
  • the present invention is directed to a technique that provides enhanced transistor performance by significantly increasing the strain in the channel region by more efficiently transferring stress from one or more stress sources into the channel region.
  • a stressed dielectric layer may be positioned more closely to the channel region in order to significantly enhance the stress transfer.
  • the stress transfer mechanism for instance obtained on the basis of an overlying dielectric stressed layer, may be significantly increased by recessing the respective drain and source regions in order to form the stressed dielectric layer at a lower depth relative to the gate insulation layer, thereby significantly enhancing the stress transfer, since the stressed dielectric layer may now transfer the respective stress more directly to the channel region.
  • the recessed drain and source regions may, in some embodiments, also comprise a strained semiconductor material to enhance even more the resulting strain in the channel region.
  • a semiconductor device comprises a first transistor of a first conductivity type comprising a first gate electrode formed above a first channel region and a first gate insulation layer formed between the first gate electrode and the first channel region. Furthermore, the first transistor comprises first drain and source regions formed adjacent to the first channel region, wherein the first drain and source regions are recessed with respect to the first gate insulation layer. Finally, the first transistor comprises a first stressed layer formed above the first drain and source regions, wherein the first stress layer extends into a recess formed by the recessed first drain and source regions.
  • a semiconductor device comprises a buried insulating layer formed above a substrate and a semiconductor layer formed on the buried insulating layer.
  • the semiconductor device further comprises a gate electrode formed above the semiconductor layer and separated therefrom by a gate insulation layer.
  • a strained semiconductor material is formed in the semiconductor layer, wherein the strained semiconductor material extends above the gate insulation layer.
  • a drain region and a source region are formed partially within the strained semiconductor material and a sidewall spacer is formed at a sidewall pf the gate electrode and above the strained semiconductor material.
  • the semiconductor device further comprises a metal suicide region formed in the drain and source regions adjacent to the sidewall spacer.
  • a method comprises forming a recess adjacent to a gate electrode structure in a semiconductor layer, wherein the gate electrode structure comprises a first sidewall spacer having a first width. Moreover, a strained semiconductor material is formed in the recess, and drain and source regions are formed at least in the strained semiconductor material on the basis of a second sidewall spacer having a second width greater than the first width.
  • a method comprises forming a first recess adjacent to a gate electrode of a first field effect transistor, wherein the gate electrode is located above a semiconductor layer and has formed on sidewalls thereof a sidewall spacer. Moreover, the method comprises forming a drain region and a source region adjacent to the sidewall spacer. Finally, the method comprises forming a first dielectric stressed layer above the first field effect transistor, wherein the first dielectric stressed layer is formed in the recess so as to extend below a gate insulation layer located between the gate electrode and the semiconductor layer.
  • Figures Ia-Ie schematically show cross-sectional views of a transistor during various manufacturing stages in forming recessed drain and source regions for receiving a recessed stressed layer according to illustrative embodiments of the present invention
  • Figures If-Ig schematically illustrate cross-sectional views of a transistor during the formation of recessed drain and source regions, in which the etch process for recessing the drain and source regions is performed after ion implantation in accordance with yet other illustrative embodiments;
  • Figure Ih schematically illustrates a cross-sectional view of a transistor during the formation of metal silicides in the drain and source regions and the gate electrode in a highly decoupled fashion according to yet other illustrative embodiments;
  • Figure Ii schematically illustrates a cross-sectional view of a semiconductor device including two different types of transistors receiving differently stressed overlaying layers in accordance with other illustrative embodiments of the present invention
  • Figures 2a-2e schematically illustrate cross-sectional views of a transistor device during the formation of an embedded strained semiconductor material having an increased offset to a metal suicide according to illustrative embodiments of the present invention
  • Figures 2f-2g schematically illustrate cross-sectional views of a transistor element having an embedded strained semiconductor material and recessed drain and source regions for enhancing the stress transfer from an overlaying layer;
  • Figure 2h schematically illustrates in cross-sectional view a semiconductor device having two different types of transistors, each having a strained semiconductor material in combination with a recessed drain/source architecture according to still other illustrative embodiments of the present invention.
  • the present invention relates to a technique for enhancing the stress transfer into the channel region of respective transistors by increasing the efficiency of stress transfer of an overlaying material layer, such as a contact etch stop layer and/or of a strained semiconductor material formed in the drain and source regions of the respective transistors.
  • an overlaying material layer such as a contact etch stop layer and/or of a strained semiconductor material formed in the drain and source regions of the respective transistors.
  • stress transfer may be significantly enhanced by using a different transistor architecture compared to conventional approaches.
  • a stress transfer and thus strain generation in the channel region may be achieved by the contact etch stop layer, which is typically provided above the transistor with high tensile or compressive stress, wherein the respective stress is transferred into the channel region through sidewall spacers of the gate electrode.
  • raised drain and source regions are frequently provided, for instance in order to reduce the drain and source resistance by providing an enhanced depth of metal suicide, or in order to accommodate a strained semiconductor material, such as silicon/germanium, which may then be provided in excess in order to reduce the consumption of strained semiconductor material during the metal silicide formation at a height that substantially corresponds to the channel region.
  • stress created by the overlaying contact etch stop layer is transferred via the upper portion of the spacers, due to the raised drain and source regions, thereby requiring the stress to act through an increased amount of material, thereby significantly reducing the finally obtained strain in the channel region.
  • the stress transfer into the channel region created by an overlaying stressed layer may be significantly enhanced by recessing the drain and source regions, since in this case the mechanisms of a substantially flush and a raised drain and source architecture are still effective, while additionally a high "direct” component of the stress is obtained, since components of the overlaying stressed layer located a height level below the gate insulation layer may laterally "push” on the channel region and thus effectively generate strain in the neighboring channel region.
  • an overlaying stressed layer such as a contact etch stop layer
  • the strain transfer obtained by strained semiconductor material in the drain and source regions may be enhanced in efficiency by more closely positioning the strained material to the channel region wherein, in some illustrative embodiments, this technique may be combined with the above-described technique using a recessed stressed overlayer.
  • This may be accomplished by means of "disposable" spacers, wherein first spacers may be used for defining a cavity next to the channel regions, and subsequently, after removal of these spacers, the actual device spacers may be formed with increased width so that, after the formation of metal suicide in the strained semiconductor material on the basis of the device spacer, a portion of the strained semiconductor material laterally remains between the metal suicide and the channel region.
  • the disposable spacer approach enables an efficient combination with the approach of the recessed stressed overlayer, since the offset provided by the disposable spacer approach provides strained semiconductor material close to the channel region, which is even maintained after silicidation, while the recessed stress layer may act more directly, as is explained above.
  • the various aspects for enhancing the stress transfer mechanism may be appropriately combined and may also be used to produce different types of strain in the respective channel regions, thereby providing the potential for individually enhancing the performance of N-channel transistors and P-channel transistors, wherein also in some aspects an enhanced stress transfer mechanism is provided for SOI-like transistor architectures, even though a stress transfer by a strained semiconductor material is restricted to the available thickness of the corresponding active semiconductor layer, contrary to bulk devices, in which strained semiconductor material may be provided down to a significant depth of the drain and source regions.
  • Figure Ia schematically illustrates a cross-sectional view of a semiconductor device 150 comprising a transistor element 100.
  • the transistor 100 may represent a field effect transistor of a specific conductivity type, such as a P-channel transistor or an N-channel transistor.
  • the transistor 100 may, in some illustrative embodiments, be formed above a substrate 101, which may represent any appropriate substrate, such as a bulk silicon substrate, a silicon-on-insulator (SOI) substrate or any other appropriate carrier material.
  • SOI silicon-on-insulator
  • the transistor 100 may represent an SOI-like transistor and thus the substrate 101 may have formed thereon a buried insulating layer 102, which may be comprised of any appropriate insulating material, such as silicon dioxide, silicon nitride and the like.
  • a semiconductor layer 103 is formed above the substrate 101 and may be comprised of a substantially crystalline semiconductor material, wherein, in some illustrative embodiments, the semiconductor layer 103 may comprise a significant amount of silicon, as the vast majority of complex integrated circuits are currently manufactured from silicon- based semiconductor material. It should be appreciated, however, that the principles of the present invention may also be applied to any other appropriate semiconductor material in which a generation of strain may significantly affect the device performance of the transistor 100.
  • the transistor 100 may further comprise a gate electrode 105, which may be comprised in this manufacturing stage of any appropriate material, such as polysilicon and the like, wherein it should be appreciated that, according to other process strategies, the gate electrode 105 may represent a material that may be converted into a conductive material of enhanced conductivity at a later stage, at least partially, or which may represent a place holder material that may be substantially completely replaced by other conductive materials, such as metals, metal compounds and the like, in a later stage.
  • the gate electrode 105 is separated from the semiconductor layer 103 by a gate insulation layer 104, thereby defining a channel region 106 located below the gate insulation layer 104.
  • any position information is to be regarded as "relative" position information and is to be considered with respect to a reference position, such as the surface 10 IS of the substrate 101, wherein an "upwards" direction is determined by the transistor 100 so that the buried layer 102 is formed “above” the substrate 101, while the transistor 100 is formed “above” the buried layer 102.
  • the gate insulation layer 104 is located “under” or “below” the gate electrode 105
  • the channel region 106 is located below the gate electrode 105 and the gate insulation layer 104.
  • a lateral direction is to be considered as a direction substantially parallel to the surface 101 S.
  • a horizontal direction is also to be considered as a direction substantially parallel to the surface 101 S, while a vertical direction substantially corresponds to a direction perpendicular to the surface 101S.
  • the gate electrode 105 of the transistor 100 may, in some illustrative embodiments, be encapsulated by a capping layer 107, which may be formed of silicon dioxide, silicon nitride, or any other appropriate material, and corresponding sidewall spacers 108, for instance in combination with an appropriate liner material 109, formed at sidewalls of the gate electrode 105.
  • the sidewall spacers 108 may be comprised of any appropriate dielectric material, such as silicon nitride, silicon dioxide, silicon oxynitride and the like.
  • a highly doped region located within the semiconductor layer 103 adjacent to the channel region 106, a highly doped region, also referred to as extension region 111, may be formed with a lateral offset from the gate electrode 105 that is determined by the sidewall spacers 108.
  • the extension regions 111 may be formed by any appropriate dopant material, such as a P-type dopant or an N-type dopant, depending on the conductivity type of the transistor 100.
  • a typical process flow for forming the semiconductor device 150 as shown in Figure Ia may comprise the following processes.
  • forming the semiconductor layer 103 for instance by providing an appropriate SOI-like substrate, or by epitaxial growth techniques, when the substrate 101 is a semiconductor bulk substrate without the buried layer 102, respective implantation processes may be performed in order to obtain a desired vertical dopant profile (not shown) within the semiconductor layer 103.
  • a dielectric layer may be formed, for instance by oxidation and/or deposition on the basis of well-established techniques, followed by the deposition of a gate electrode material by well-established deposition techniques, such as low pressure chemical vapor deposition (LPCVD) when, for instance, polysilicon is considered.
  • LPCVD low pressure chemical vapor deposition
  • the gate electrode material and the dielectric layer may be patterned on the basis of sophisticated photolithography and etch techniques in order to obtain the gate electrode 105 and the gate insulation layer 104. It should be appreciated that, in some illustrative embodiments, the gate electrode material may be provided with a respective capping layer, which may also be patterned in combination with the gate electrode material, thereby forming the capping layer 107.
  • the sidewall spacers 108 may be formed by depositing the liner material 109, if provided, and subsequently forming a spacer layer, such as a silicon nitride layer, a silicon dioxide layer and the like, wherein a high degree of etch selectivity may be provided between the liner 109 and the spacer layer in order to efficiently control a subsequent anisotropic etch process for removing the spacer layer material from horizontal portions of the device 150, thereby leaving the spacers 108.
  • a spacer layer such as a silicon nitride layer, a silicon dioxide layer and the like
  • a thickness of the spacer layer and thus a width of the spacers 108 is selected in accordance with device requirements so as to obtain a desired offset of the extension regions 111 from the gate electrode 105 during a subsequent ion implantation process 129 for introducing a desired dopant species with a specific concentration at a specified depth of the semiconductor layer 103.
  • an anneal process may be performed after the ion implantation 129 in order to activate the dopants in the regions 111, while, in other strategies, a corresponding anneal process may be performed at a later manufacturing stage.
  • a further spacer layer may be formed above the device 150 on the basis of well-established techniques, such as plasma enhanced chemical vapor deposition (PECVD), wherein the further spacer layer may be comprised of substantially the same material as the spacers 108 or may be comprised of a material having a high etch selectivity with respect to the spacers 108.
  • PECVD plasma enhanced chemical vapor deposition
  • silicon nitride or silicon dioxide may be deposited in a substantially conformal manner with a specified layer thickness and thereafter an anisotropic etch process may be performed to remove the further spacer material from horizontal portions of the device 150.
  • Figure Ib schematically illustrates the semiconductor device 150 after the completion of the above- described process sequence and during an etch process 128.
  • the transistor 100 of the device 150 comprises a further spacer element 110, which may be formed directly on the spacer 108, or which may comprise a further liner (not shown), depending on the process requirements.
  • the spacer 110 is comprised of an appropriate material that has a high etch selectivity with respect to the material of the semiconductor layer 103 during the etch process 128, which may, in some embodiments, be designed as a substantially anisotropic etch process, while, in other illustrative embodiments, the etch process 128 may be performed with a reduced degree of anisotropy or as a highly isotropic etch process.
  • etch recipes for etching a silicon- based material with high selectivity to, for instance, silicon dioxide, silicon nitride and the like are well established in the art.
  • a recess 112 maybe formed, wherein the lateral offset 112O of the recess 112 with respect to the gate electrode 105 is determined by the width of the spacers 108 and 110 and the specifics of the etch process 128.
  • the etch process 128 is assumed to be highly anisotropic, while in other cases a certain degree of under-etching may be achieved.
  • the recess 112 may be formed down to a depth 112D that ensures a highly efficient stress transfer into the channel region 106 after the recess 112 is filled by a highly stressed overlaying material.
  • the depth 112D may be obtained on the basis of an appropriately selected target value in combination with a corresponding control of the etch time of the process 128.
  • a gate length of the transistor 100 i.e., in Figure Ib the horizontal extension of the gate electrode 105, indicated as 105L, is approximately 100 nm and significantly less, or even 50 nm and less
  • the depth 112D may range from approximately 1-20 nm.
  • the offset 112O of the recess 112 may also range from approximately several nanometers to ten or more nanometers, depending on the specifics of the etch process 128 and the width of the spacers 110 and 108, which may range from approximately 5-20 nm for gate lengths in the above-specified range.
  • Figure Ic schematically shows the semiconductor device 150 in a further advanced manufacturing stage, in which the device 150 is subjected to a further implantation process 113 for defining drain and source regions 114 adjacent to the recess 112.
  • the gate electrode 105 may also be exposed, depending on process strategies.
  • the capping layer 107 may be removed on the basis of a selective etch process, wherein, in some illustrative embodiments, the spacers 108 and 110 may also be removed if the capping layer 107 and the spacers 108, 110 are substantially comprised of the same material, such as silicon nitride and the like.
  • corresponding new spacers 115 may be formed on the basis of well-established recipes so as to act as implantation masks during the process 113.
  • at least the spacer 110 may be comprised of a material having a high etch selectivity with respect to the capping layer 107, for instance the spacer 110 may be comprised of silicon dioxide and the capping layer 107 may be comprised of silicon nitride, or vice versa, thereby substantially maintaining the spacers 110 and 108 so that the ion implantation process 113 may be performed on the basis of the spacers 110 and 108.
  • implantation processes such as a halo implantation, an amorphization implantation and the like, may be performed prior to or after the actual implantation 113 for forming the drain and source regions 114, depending on the process strategy.
  • any of these implantation processes, including the implantation 113 may comprise a tilted implantation process in order to appropriately position the respective dopant species at a sidewall 112 A of the recess 112.
  • a desired lateral and vertical dopant profile for the drain and source regions 114 may be achieved. Thereafter, an anneal process may be performed to activate the introduced dopant species as well as to, at least partially, re-crystallize implantation-induced damage in the drain and source regions 114.
  • Figure Id schematically illustrates the semiconductor device 150 in a further advanced manufacturing stage, after the completion of the above-described process sequence and with a layer of refractory metal 116 formed above the transistor 100.
  • the layer 116 may be comprised of one or more metals, such as nickel, platinum, cobalt, combinations thereof and the like, which may be formed on the basis of well-established techniques, such as sputter deposition or any other appropriate deposition technique, with any preceding cleaning recipes including plasma-based cleaning processes and/or thermally activated cleaning processes.
  • an appropriate sequence of heat treatments may be performed to initiate a chemical reaction of the metal layer 116 with underlying semiconductor material, which may be provided in the gate electrode 105 and the drain and source regions 114, thereby converting the semiconductor material, such as silicon, silicon/germanium, silicon/carbon and the like, into a highly conductive semiconductor metal compound, such as a metal suicide.
  • a chemical reaction of the metal layer 116 with underlying semiconductor material which may be provided in the gate electrode 105 and the drain and source regions 114, thereby converting the semiconductor material, such as silicon, silicon/germanium, silicon/carbon and the like, into a highly conductive semiconductor metal compound, such as a metal suicide.
  • Figure Ie schematically illustrates the semiconductor device 150, in which the transistor element 100 comprises metal suicide regions 117 formed in the drain and source regions 114 as well as in the gate electrode 105, wherein it should be appreciated that, in other process strategies, the metal suicide regions 117 may not necessarily be formed in a common process or may not be formed at all, as will be described later on. Moreover, a stressed contact etch stop layer 118 is formed above the transistor 100 such that the stressed layer 118 is also formed within the recesses 112, that is, the stressed layer 118 extends below a bottom surface 104B of the gate insulation layer 104.
  • a plurality of dielectric materials such as silicon nitride
  • silicon nitride may be highly efficiently deposited on the basis of plasma-enhanced deposition techniques so as to exhibit a high magnitude of intrinsic stress ranging, for instance, from tensile stress of 1.5 GPa (GigaPascal) or more to compressive stress of substantially the same order of magnitude by appropriately adjusting process parameters, such as deposition temperature, deposition pressure, ratio of precursor materials, ion bombardment during the deposition and the like.
  • the layer 118 may be provided with the respective internal stress.
  • the transistor 100 is to represent a P-channel transistor, wherein a compressive strain in the channel region 106 may increase the hole mobility and thus the drive current capability of the transistor 100, the contact etch stop layer 118 may be provided with compressive stress, which creates a corresponding compressive strain in the channel region 106.
  • the stressed layer 118 may provide a certain degree of strain into the channel region 106 in a similar way as in transistor architectures having substantially flush drain and source regions, wherein, however, in this case, additionally stress is transferred highly efficiently into the channel region 106 due to the fact that the layer 118 is positioned at a height that approximately corresponds to the position of the channel region 106. Consequently, a corresponding stress indicated by the arrows 118B may highly efficiently act laterally in a "direct" manner on the channel region 106, thereby creating additional strain therein.
  • a high degree of strain in the channel region 106 may be created even without a strained semiconductor material, as is frequently used in other transistor configurations, as will be described later on, thereby reducing production costs since corresponding epitaxial growth processes may be omitted.
  • the desired type of strain may be created in the channel region 106.
  • the transistor 100 may represent an N-channel transistor requiring a tensile stress for increasing the electron mobility in the channel region 106
  • the layer 118 may be formed with high tensile stress on the basis of appropriately selected deposition parameters, as explained above.
  • different types of transistors may receive the layer 118 with a different stress, as will be described later on in more detail, thereby providing a high degree of design flexibility.
  • the contact etch stop layer 118 may be formed directly on the respective drain and source regions, i.e., in the example shown in Figure Ia directly on the respective metal suicide regions 117, while, in other approaches, an intermediate liner (not shown) may be deposited, wherein an intermediate liner, which may be used as an etch stop layer for removing unwanted portions of the layer 118 from respective device areas, as will be described later on, may not necessarily negatively impact the strain transfer mechanism since the stress 118B may nevertheless substantially directly act on the channel region 106, even if a thin intermediate layer is provided.
  • Figure 1 f schematically illustrates the semiconductor device 150 according to still further illustrative embodiments, in which the drain and source regions 114, as well as the extension regions 111, may be formed by the ion implantation 113 prior to the formation of the recesses 112.
  • the transistor 100 may have the gate electrode 105 encapsulated by the capping layer 107 and the corresponding spacers 108 and 110, wherein the spacers 108 may provide the desired offset of the extension regions 111 with respect to the gate electrode 105, while the spacers 110 may provide the desired offset of the drain and source regions 114, as is also described above.
  • the respective process parameters may be selected such that the drain and source regions 114 are designed in conformity with the recess 112 that is to be formed in a subsequent manufacturing step. That is, during the implantation 113, and also during any associated implantation processes for halo implants and amorphization, the process parameters, such as implantation dose, implantation energy and possibly tilt angle, may be selected such that the drain and source regions 114 receive a desired dopant concentration and gradient at the PN junction, as is also described with respect to Figure Ic, so that the drain and source regions 114 may be appropriately recessed while nevertheless maintaining the required functionality of the regions 114.
  • the process parameters such as implantation dose, implantation energy and possibly tilt angle
  • Figure Ig schematically illustrates the device 150 after the ion implantation 113, wherein, in some illustrative embodiments, the etch process 128, which may be an anisotropic process or an isotropic process as is previously described, may be performed prior to performing an appropriate anneal process for activating the dopants in the regions 114. Consequently, during the etch process 128, an increased etch rate may be obtained, due to the preceding implantation processes, which may substantially affect the crystalline structure and thus the etch rate during the process 128.
  • the etch process 128 which may be an anisotropic process or an isotropic process as is previously described
  • the etch selectivity with respect to the spacers 110 and the capping layer 107 may be increased, since the ion bombardment during the preceding implantation processes may modify the semiconductor layer 103 more efficiently compared to the dielectric materials of the spacers 110 and the capping layer 107.
  • the etch process 128 may be performed after any anneal cycles for activating the dopant species and for re-crystallizing implantation-induced damage.
  • the recesses 112 are formed within the drain and source regions 114, wherein, with respect to the depth of the recess 112 as well as with respect to its lateral offset with respect to the gate electrode 105, the same criteria apply as previously described. Thereafter, further processing may be continued as is also described with reference to Figures Id-Ie.
  • the capping layer 107 may not necessarily be provided prior to the etch process 128 so that, during the corresponding process, the gate electrode 105, when comprised of polysilicon, may also be recessed, wherein a corresponding material removal of the gate electrode 105 may be taken into consideration during the formation of the gate electrode 105.
  • the gate electrode material may be provided with a certain extra thickness that substantially corresponds to the depth 112D ( Figure Ib) of the recess 112, wherein, additionally, the difference in etch rate may be taken into consideration, when, for instance, the etch process 128 is performed on the basis of a substantially crystalline material in the semiconductor layer 103, while the silicon of the gate electrode 105 may be substantially a polycrystalline material.
  • a highly conductive metal suicide in the drain and source regions and/or the gate electrode for a substantially silicon-based semiconductor device 150.
  • the respective metal suicide regions such as the regions 117 ( Figure Ie)
  • a thickness of the metal suicide in the gate electrode 105 is substantially determined by the device constraints imposed by the characteristics of the respective drain and source regions 114, since, in these regions, the metal suicide may not be formed with a thickness as would be desirable for the gate electrode 105 in order to appropriately enhance the conductivity thereof. Consequently, in some illustrative embodiments, the formation of respective metal suicide regions in the drain and source regions 114 and the gate electrode 105 maybe efficiently formed independently from each other.
  • Figure Ih schematically illustrates the semiconductor device 150 in accordance with one illustrative embodiment, in which the formation of respective metal suicide regions may be accomplished in a highly independent fashion.
  • the device 150 may, in this manufacturing stage, Le., after the formation of the recessed drain and source regions 114, comprise the layer 116 of refractory metal, wherein, additionally, a silicidation mask 119 is formed so as to cover the drain and source regions 114 while exposing at least a top surface of the gate electrode 105.
  • the capping layer 107 possibly in combination with the spacers 110 and 108, may be removed and may be replaced by spacers 130. In other cases, the gate electrode 105 may have been formed without the capping layer 107, as previously described.
  • the silicidation mask 119 may be comprised of any appropriate material, such as a polymer material, that may withstand the temperatures required for depositing the layer 116 and initiating a chemical reaction with material of the gate electrode 105.
  • the silicidation mask 119 may be formed by depositing an appropriate material, such as a polymer, a photoresist or any other dielectric material, in a highly non-conformal fashion, for instance by any deposition technique providing a substantially flow-like fill behavior, such as spin-on techniques, when low viscous materials are considered and the like.
  • a subsequent removal process for instance by etching the material selectively to the gate electrode 105, may be performed in order to obtain a level for the silicidation mask 119 that at least exposes the top surface of the gate electrode 105.
  • the layer 116 may be deposited on the basis of any appropriate deposition techniques as explained above.
  • a thickness of the layer 116 and the material composition thereof may be selected with respect to requirements for the gate electrode 105 in order to obtain a required amount and type of metal suicide in the gate electrode 105.
  • the chemical reaction may be initiated on the basis of an appropriate heat treatment to obtain the desired amount of highly conductive metal suicide in the gate electrode 105.
  • other silicidation regimes may be used in which, for instance, a silicidation of the gate electrode material may be accomplished during deposition and simultaneous conversion of an appropriate metal into metal suicide.
  • the silicidation mask 119 may also be removed, for instance by any appropriate etch technique.
  • any appropriate etch technique For example, well-established etch techniques which may have a high degree of selectivity with respect to metal suicide and other materials, such as the material of the spacers 110 and the drain and source regions 114, are well-established and may be used during this process sequence.
  • an appropriate silicidation process may be performed for the drain and source regions 114, wherein the respective process parameters may be selected such that an appropriate type and thickness of metal suicide is obtained in the drain and source regions 114.
  • the further silicidation process may have only a minor effect on the previously formed metal suicide in the gate electrode 105.
  • further processing may be continued as is also described with reference to Figure Ie.
  • Figure Ii schematically illustrates the semiconductor device 150 comprising a first transistor lOOp and a second transistor 10On, which may represent transistors of different conductivity types, such as a P-channel transistor and an N-channel transistor.
  • the transistors 10Op, lOOn may have substantially the same configuration as the transistor element 100 previously described, wherein, however, the respective drain and source regions, as well as the corresponding channel regions, may have appropriate dopant species in order to provide the desired conductivity type.
  • the transistors 10Op, lOOn may be formed on the basis of the process techniques described above with reference to transistor 100, wherein, however, the various implantation processes may be performed on the basis of respective implantation masks in order to selectively introduce the required dopant species into the transistors 10Op, lOOn on the basis of well-established masking techniques.
  • the respective recesses 112 may be formed according to similar process techniques as previously described and the further processing, for instance the formation of metal suicide regions (not shown), may be accomplished as is previously described.
  • a first contact etch stop layer 118p may be formed above the first and second transistors 10Op, 100n, wherein, in some illustrative embodiments, an optional etch stop layer 120 may be provided.
  • the optional etch stop layer 120 may be comprised of silicon dioxide, when the first contact etch stop layer 118 ⁇ may be comprised of silicon nitride. In other illustrative embodiments, the etch stop layer 120 may be omitted.
  • the first contact etch stop layer 118p may be removed from the transistor 10On, for example based on the etch stop layer 120, if provided, and a second contact etch stop layer 118n, possibly in combination with a second etch stop layer 121, may be formed so as to cover the second transistor 10On.
  • the first contact etch stop layer 11 Sp may have a high intrinsic compressive stress when the transistor lOOp represents a P-channel transistor, while the second contact etch stop layer 118n may comprise a high tensile stress when the transistor lOOn represents an N-channel transistor.
  • an appropriate etch mask such as a resist mask 123, may be formed to expose the transistor lOOp in order to remove the second contact etch stop layer 118n by means of a corresponding etch process 124, which may be controlled on the basis of the etch stop layer 121, if provided.
  • both transistors have formed thereon appropriately stressed contact etch stop layers, that is, the transistor lOOp may have formed thereabove the layer 118p creating in a highly efficient manner a respective strain, wherein the transistor lOOn comprises the layer 118n having a different type of intrinsic stress so as to create in the respective channel region a different desired type of strain.
  • a strained semiconductor material is positioned in close proximity to the channel region by means of a disposable spacer, thereby enabling an efficient combination of the two strain- inducing mechanisms, i.e., providing strained semiconductor material close to the channel and using a recessed transistor configuration, similar to embodiments previously described with reference to Figures Ia-Ii.
  • a semiconductor device 250 may comprise a transistor 200, which may have a similar configuration as the transistor 100 in Figure Ia, except for the extension regions 111.
  • the transistor 200 may comprise a gate electrode 205 that is formed above a semiconductor layer 203 provided above a substrate 201, wherein the gate electrode 205 is separated from the semiconductor layer 203 by a gate insulation layer 204.
  • the gate electrode 205 may be encapsulated by a capping layer 207 and spacers 208, possibly in combination with a liner 209.
  • substantially the same processes may be involved as previously described with reference to the device 150 in Figure Ia.
  • the device 250 may be subjected to an etch process 228 for forming a recess adjacent to the gate electrode 205 with an offset therefrom corresponding to a width 208W of the spacer 208 and the characteristics of the etch process 228, as is also described above with reference to the etch process 128. That is, the process 228 may be designed as an anisotropic or isotropic etch process for recessing the semiconductor layer 203 adjacent to the gate electrode 205 with a specified depth in order to form in the respective recess a strained semiconductor material, which may then provide a desired strain in a channel region 206 of the transistor 200.
  • a corresponding strained semiconductor material may be formed on the basis of well- established selective epitaxial growth techniques, in which the remaining crystalline material of the layer 203, after being recessed by the etch process 228, is used as a growth template in order to re-grow the strained semiconductor material, which is selected to have in its natural or unstrained state a slightly different lattice spacing compared to the template material of the remaining semiconductor layer 203.
  • silicon/germanium or silicon/carbon are crystalline semiconductor compounds which when grown on a substantially undisturbed silicon lattice may form a strained semiconductor material due to a respective slight mismatch in lattice spacing.
  • a silicon/germanium material grown on a substantially undisturbed silicon lattice may form a compressively strained lattice due to a slightly greater lattice spacing of non-strained silicon/germanium with respect to silicon.
  • silicon/carbon grown on silicon may form a semiconductor material of tensile strain.
  • Figure 2b schematically illustrates the device 250 according to one illustrative embodiment in which, after the completion of the etch process 228 and any pre-epitaxial processes, such as clean processes and the like, a strained semiconductor material 230 is formed in the corresponding recess, wherein, in this embodiment, the strained semiconductor material 230 may be formed so as to substantially completely fill the corresponding recess without requiring an over growth to provide excess material for a subsequent silicidation process. In other embodiments, as will be described later on, after the selective epitaxial growth process, a certain degree of underfill may be maintained. In the illustrative example shown, a silicon/germanium semiconductor material 230 may have been formed to provide a respective compressive strain.
  • the spacer 208 having the width 208 W that, in combination with the process parameters of the etch process 228, substantially determines an offset of the strained semiconductor material 230 with respect to the gate electrode 205 may be removed on the basis of well-established selective etch recipes. Thereby, the capping layer 207 may also be removed. After the removal of the spacer 208, a corresponding spacer regime may be used in order to provide the required lateral and vertical dopant profile in the semiconductor layer 203, thereby forming respective extension regions and drain and source regions.
  • Figure 2c schematically illustrates the semiconductor device 250 during a corresponding process sequence, wherein an offset spacer 231 may be used for defining an extension region 211, while one or more final spacers 232 may be used as an implantation mask during an ion implantation process 213 for forming drain and source regions 214.
  • the spacer 232 in combination with the spacer 231 has a width 232W that is greater than the corresponding width 208W, wherein it should be appreciated that the width 232W may include the width of the offset spacer 231.
  • the increased width 232W provides a respective offset between a metal suicide region to be formed within the strained semiconductor material 230 and a portion 230A of the material 230 located next to the channel region 206.
  • Figure 2d schematically illustrates the semiconductor device 250 with correspondingly formed metal silicide regions 217, wherein the corresponding offset 217A of the metal silicide regions 217 in the strained semiconductor material 230A of the drain and source regions 214 is provided, thereby laterally positioning a strained semiconductor material between the substantially relaxed metal silicide region 217 and the channel region 206.
  • FIG. 2e schematically illustrates the semiconductor device 250 in accordance with yet other illustrative embodiments in which, after the completion of the process sequence as described with reference to Figure 2a, i.e., after a corresponding cavity etch and selective epitaxial growth process, a recess 212 is still provided adjacent to the gate electrode 2Q5. That is, the epitaxial growth process may be stopped at a height level that is below the level defined by the gate insulation layer 204.
  • the recess 212 may have a depth of approximately 1-20 nm, when the material 230 is formed down to a depth of approximately 30-40 nm.
  • the process time may be reduced, in addition to providing further enhancement of the strain-inducing mechanism.
  • the device 250 as shown in Figure 2b may be subjected to a further etch process for removing strained semiconductor material in order to provide the recess 212 when a control of the selective epitaxial growth process may not result in the desired process uniformity.
  • the spacer 208 may be removed and further processing may be performed on the basis of device spacers, such as the spacers 231 and 232, having the increased spacer width 232W in order to form the drain and source regions 214 and the extensions 211.
  • Figure 2f schematically illustrates the device 250 after completion of the above-described processes.
  • Figure 2g schematically illustrates the device 250 in a further advanced manufacturing stage.
  • the transistor 200 may comprise metal suicide regions 217 which may be formed on the basis of the spacer 232, as is also described above with reference to Figure 2d. Consequently, a certain amount of non-silicided strained semiconductor material 230A is provided between the metal suicide region 217 and the channel region 206 due to the offset provided by the increased spacer width 232W compared to the spacer width 208 W used for forming the respective strained semiconductor material 230.
  • the formation of the metal silicide regions 217 in the gate electrode 205 and the drain and source regions 214 may be performed in a common process, as shown in Figure 2g, or may be performed in a more independent manner, as is for instance described with reference to Figure Ih or in accordance with any other appropriate regime.
  • the device 250 comprises a stressed contact etch stop layer 218, which may comprise any appropriate intrinsic stress so as to further enhance the strain in the channel region 206.
  • the layer 218 may be provided with high compressive stress in order to enhance the strain created by the respective silicon/germanium material 230.
  • the strained semiconductor material 230 may be comprised of silicon and carbon, thereby inducing a tensile strain in the channel region 206.
  • the contact etch stop layer 218 may be provided with high intrinsic tensile stress, which may be accomplished on the basis of appropriately selected deposition parameters, as is previously described.
  • the recess 212 may provide further enhanced stress transfer into the channel region 206, since a significant portion of the layer 218 is formed within the recess 212, thereby providing direct "pushing" 218B or "drawing,” depending on the type of stress, with respect to the channel region 206.
  • the strain of the non-silicided portion 230A may be combined with the additional direct stress 218B, thereby resulting in a corresponding high strain in the channel region 206.
  • a depth 212D of the recess 212 of approximately 1-20 nm and a depth 230D of the strained semiconductor material 230 in the range of approximately 30-50 nm a significant increase of the strain in the channel region 206 may be observed.
  • Figure 2h schematically illustrates the semiconductor device 250 according to further illustrative embodiments in which the device 250 comprises a first transistor 20Op and a second transistor 20On of different conductivity types.
  • the transistor 20Op may represent a P-channel transistor and the transistor 20On may represent an N-channel transistor.
  • the same criteria may apply as previously explained with reference to the transistor 200, wherein, however, the corresponding profiles and concentrations in the channel regions 206 and the drain and source regions (not shown for clarity) may be selected so as to correspond to the respective conductivity type.
  • the first transistor 20Op may have formed thereabove a first contact etch stop layer 218p, which extends into the corresponding recess 212 in order to further enhance the strain created by the strained semiconductor material 23Op.
  • the second transistor 20On comprises a second contact etch stop layer 218n having a different type of internal stress so as to correspondingly increase a strain in the respective channel region provided by the strained semiconductor material 230n.
  • two strain-inducing sources i.e., a strained semiconductor material and a stressed overlaying layer
  • a strained semiconductor material may be efficiently combined for different types of transistors by at least positioning the strained semiconductor material more closely to the gate electrode, wherein, in some illustrative embodiments, additionally a recessed transistor configuration may be provided in order to even more enhance the stress transfer mechanism for the respectively stressed contact etch stop layers.
  • the present invention provides an enhanced technique for the manufacturing of transistor elements having formed therein one or more strain-inducing sources, the efficiency of which is significantly increased by positioning the respective strain-inducing source more closely to the channel region of the respective transistor element.
  • this may be accomplished by recessing the drain and source regions and forming a stressed layer in the recess, such as a stressed contact etch stop layer, which may now generate the strain in the channel region more directly.
  • strained semiconductor material may be positioned more closely to the channel region, wherein deleterious strain relaxing effects from metal suicides may be reduced or substantially avoided. Consequently, increased efficiency in providing strain in the channel region may be achieved.
  • the different techniques may be advantageously combined so as to enhance the strain-inducing mechanism provided by a strained semiconductor material in combination with an enhanced efficiency of an overlaying stressed layer by forming the same in a recessed drain and source region. Since one or more of the preceding techniques may be readily applied to different transistor types, a high degree of flexibility in individually improving the performance of these transistors may be obtained.

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Abstract

Par l'encastrement (112D, 212D) des régions de drain et de source (114, 214), une couche hautement stressée (118, 218), telle qu'une couche de contact d'arrêt de gravure, peut être formée dans l'encastrement (112, 212) afin d'améliorer la génération de contraintes dans la région canal adjacente (104, 204) d'un transistor à effet de champ (100, 200). En outre, un matériau semi-conducteur contraint (230) peut être placé tout près de la région canal (104, 204) en réduisant ou en évitant les effets de relaxation indus des siliciures métalliques (217), permettant ainsi de fournir également un rendement amélioré de la génération de contraintes. Dans certains aspects, les deux effets peuvent être combinés pour obtenir un mécanisme créateur de contraintes encore plus efficace.
PCT/US2007/004689 2006-03-31 2007-02-21 Technique permettant d'obtenir des sources de stress dans les transistors très rapprochés d'une région canal par l'encastrement des régions de drain et de source WO2007126495A1 (fr)

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CN2007800114369A CN101416287B (zh) 2006-03-31 2007-02-21 用于通过使漏极及源极区凹陷而在晶体管中紧邻沟道区提供应力源的技术
JP2009502792A JP5576655B2 (ja) 2006-03-31 2007-02-21 ドレイン及びソース領域にリセスを設けることでチャネル領域に極めて近接するトランジスタにストレスソース与える技術
KR1020087026877A KR101430703B1 (ko) 2006-03-31 2007-02-21 드레인 및 소스 영역들을 함몰시킴으로써 트랜지스터들 내에 채널 영역에 근접하는 스트레스 소스들을 제공하는 기술
GB0817592A GB2449824B (en) 2006-03-31 2007-02-21 Technique for providing stress sources in transistors in close proximity to a channel region by recessing drain and source regions

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DE102006015077A DE102006015077B4 (de) 2006-03-31 2006-03-31 Transistor mit abgesenkten Drain- und Source-Gebieten und Verfahren zur Herstellung desselben
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US11/558,006 2006-11-09
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US20050269650A1 (en) * 2004-06-08 2005-12-08 Fujitsu Limited, Semiconductor device having stress and its manufacture method
US20060065914A1 (en) * 2004-09-29 2006-03-30 International Business Machines Corporation Structure and method for making strained channel field effect transistor using sacrificial spacer

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US20050110082A1 (en) * 2003-11-25 2005-05-26 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device having high drive current and method of manufacture therefor
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US8669146B2 (en) 2011-01-13 2014-03-11 International Business Machines Corporation Semiconductor structures with thinned junctions and methods of manufacture
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