WO2007113769A1

WO2007113769A1 - Integrated circuit with a capacitor bank and method for testing a capacitor bank

Info

Publication number: WO2007113769A1
Application number: PCT/IB2007/051192
Authority: WO
Inventors: Ivano Midulla; Stefano Menichelli; Oreste Concepito
Original assignee: Dsp Group Switzerland Ag
Priority date: 2006-04-05
Filing date: 2007-04-03
Publication date: 2007-10-11

Abstract

An integrated circuit is provided which comprises a capacitor bank (CB) having a plurality of capacitors (C1-C6) and a switch (sw1-sw6) associated to each of the capacitors (C1-C6). The integrated circuit furthermore comprises a test circuit for testing the capacitor bank. The test circuit comprises a state machine unit (SM) for setting the switches (sw1-sw6) in the capacitor bank (CB). A current generator (Ic) is provided for generating a current to charge those capacitors (C1-C6) in the capacitor bank whose associated switches (sw1-sw6) have been set by the state machine unit (SMU). A comparator unit (CU) compares the voltages across the capacitors in the capacitor bank (CB) with a reference voltage (Vref). A counter (C) determines the time required by the current generator to charge the capacitors (C1-C6) to the reference voltage (Vref).

Description

DESCRIPTION

Integrated circuit with a capacitor bank and method for testing a capacitor bank

The present invention relates to an integrated circuit with a capacitor bank and a method for testing a capacitor bank.

Many integrated circuits in applications like in the communication field utilize a tunable reference oscillator or crystal oscillator based on an external quartz crystal, which need to be tuned exactly, preferably with an accuracy of a few ppms. Such a level of accuracy is typically achieved by using capacitor banks arranged on chip in order to perform the required tuning. The tuning of the oscillator frequency may be carried out once in the lifetime of the product, e.g. when the chip is arranged on a application board or circuit board during fabrication or it may be performed dynamically to align the reference frequency of e.g. a transmitter and a receiver.

An algorithm to perform the required tuning will be very simple as long as the monotonicity of the capacitor array is present. However, the tuning algorithm will become more complex if a monotonic behavior of a capacitor array cannot be provided. In particular, if the tuning is performed dynamically, this may lead to a major problem as the corresponding code for implementing the tuning algorithm has to be provided on the device in some means for storing. Accordingly, a simple and compact code for the tuning algorithm is required.

Furthermore, in order to provide for a dynamic frequency tuning, the tuning algorithm or tuning process must be as fast as possible such that the frequency of the transmitter and the receiver can be aligned very fast in order to be able to use time slots according to typical communication standards. The capacitor banks which are required to tune the oscillator frequency of an integrated circuit can be implemented as binary tree or as an additive structure. As an example, in order to realize a capacitor bank with a capacitance of 32pF, 2⁶=64 steps may be required. Fig.l shows a basic circuit diagram of a capacitor bank according to the prior art. The capacitor bank is implemented based on six capacitors C0-C5 and six switches swθ-sw5. The values of the six capacitors may be 16pF, 8pF, 4pF, 2pF, IpF and 0,5pF, respectively. Accordingly, such a capacitor bank is very compact as only six capacitors and six switches are required. As an example, if a capacitance of 16pF is to be implemented, merely the switch sw5 needs to be closed while the other switches are opened. If a capacitance of 16,5pF is to be realized, merely the switches sw5 and swO must be closed. If a capacitance of 15,5pF is required, merely the switches swO and sw4 are to be closed. However, possible process mismatches must be considered, such that a case may occur where the capacitor C5 is smaller than required, i.e. 16pF. In particular, it may be smaller than the sum of all other capacitors, namely 15,5pF. For cases where the steps are larger than 64 steps, for example at least 256 steps and the least significant bit LSB is small, i.e. in the area of tens of fF, a non-monotonic capacitance array may be the result.

In a further implementation of a known capacitor bank, all capacitors have the same value, namely the minimum step value. Accordingly, the total number of capacitors will then correspond to the number of steps which are to be implemented. Therefore, in order to implement 32pF in 64 steps, the capacitor bank will be based on capacitors having a capacitance of 0,5pF, each with a switch in series to the capacitance.

The total amount of capacitance according to such an additive structure corresponds to the implementation according to the binary tree while the actual size of the capacitance will be smaller such that an increased silicon area is required if layout rules are to be met preventing the design of the capacitors closer than a predefined limit. In case of small capacitors, the necessary space between one capacitor and any adjacent capacitor could be larger than the capacitor itself depending on the actual implemented technology. In addition to the silicon area required for the capacitance, additional silicon area is also required to implement the switches, i.e. if the number of switches increases, also the required silicon area will increase. Therefore, the total amount of area required for an additive structure capacitor bank can be three or four times larger than the area required for a binary tree capacitor bank. However, the additive capacitor bank array is monotonic due to the actual additive structure such that no verification is required.

US 2005/0099198 Al discloses a build-in self test circuit for determining the values of the capacitors in a capacitor bank in an integrated circuit. The capacitors are charged and discharged cyclically to determine the actual values of the capacitors.

It is therefore an object of the invention to provide an integrated circuit with a capacitor bank and a test circuit for determining the monotonicity of the capacitor bank and a method for determining the monotonicity of the capacitor bank.

This object is solved by an integrated circuit according to claim 1 and a method for testing a capacitor bank according to claim 6.

Therefore, an integrated circuit is provided which comprises a capacitor bank having a plurality of capacitors and a switch associated to each of the capacitors. The integrated circuit furthermore comprises a test circuit for testing the capacitor bank.

The test circuit comprises a state machine unit for setting the switches in the capacitor bank. A current generator is provided for generating a current to charge those capacitors in the capacitor bank whose associated switches have been set by the state machine unit. A comparator unit compares the voltages across the capacitors in the capacitor bank with a reference voltage. A counter determines the time required by the current generator to charge the capacitors to the reference voltage. Accordingly, a build-in self test BIST is provided to determine the monotonicity of the capacitor bank.

According to an aspect of the invention, the state machine unit is adapted to test all possible combinations of capacitors in the capacitor bank and to test the most critical transitions in the configurations of the capacitor bank by setting the associated switches accordingly.

According to a preferred aspect of the invention, a reference oscillator is provided and is set according to the results of the testing of the capacitor bank. If the monotonicity of the capacitor banks has been ascertained simple tuning algorithm may be used. Otherwise a complex tuning algorithm must be used.

According to a further aspect of the invention, a register unit is provided for storing the results of the counter. The state machine unit compares the results of the counter to determine the monotonicity of the capacitor bank . The invention also relates to a method for testing a capacitor bank having a plurality of capacitors each with an associated switch. The switches of the capacitor bank are controlled. A current is generated for charging those capacitors in the capacitor bank whose associated switches have been set. The voltages across the capacitors in the capacitor bank are compared with a reference voltage. The time which the current generator requires to charge the capacitors until the voltages thereof correspond to the reference voltage is determined.

The invention further relates to an integrated circuit. A binary tree capacitor bank comprises n capacitors and a switch associated to each of the capacitors. The value of each capacitor corresponds to 2^1"1 times the value of a step capacitor, wherein i is an integer from 1 to n. At least a first capacitor of the capacitor bank is divided into a first and second part.

The invention relates to the idea to test the monotonicity of a capacitor bank by charging the respective capacitors by a constant current, by comparing the voltage across the capacitor with a reference voltage and by determining the time required for the voltage of the capacitor to reach the reference voltage. This is performed for the capacitors as well as combinations thereof within the capacitor bank. According to these measurements, it can be determined whether the capacitor bank has a monotonic or non-monotonic behavior. Further aspects of the invention are defined in the dependent claims.

The embodiments and advantages of the invention will now be described in more detail with reference to the figures.

Fig.l shows a circuit diagram of a capacitor bank according to the prior art,

Fig.2 shows a block diagram of a test circuit for a capacitor bank according to a first embodiment,

Fig.3 shows a timing diagram of the test structure of Fig. 2, Fig.4 shows a schematic representation of a binary tree capacitor array according to a second embodiment,

Fig.5 shows a further schematic representation of the capacitor array of Fig. 4, Fig.6 shows a schematic representation of the binary tree capacitor array according to Fig. 4, Fig.7 shows a schematic representation of the binary tree capacitor array according to a third embodiment, Fig.8 shows a schematic representation of the binary tree capacitor array according to Fig. 7, and Fig.9 shows a schematic representation of the binary tree capacitor array according to Fig. 7.

Fig.2 shows a block diagram of a test circuit for a capacitor bank according to a first embodiment. The test circuit is provided in an integrated circuit (preferably on chip) and is arranged to test a capacitor bank having capacitors Cl-Cn and their associated switches swl-swn. The test circuit comprises a state machine unit SM, a first switch Iso, a second switch Sc, a constant current generator Ic, a resistor R_DIS, a comparator unit CU and a counter unit C. The state machine unit SM provides the signals for the switches swl-swn as well as the signals for the first switch Iso and the second switch Sc. A third switch S_cik is arranged for connecting the counter C to the clock signal elk. The capacitor bank may be coupled to the other circuits on chip by means of the first switch Iso. A register reg may be provided to store the counts of the counter C. The register may be provided in the counter, in the state machine unit or elsewhere in the integrated circuit.

The test structure according to Fig.2 is preferably arranged on chip as a dedicated circuit, i.e. as a build-in self test circuit. Otherwise, the testing of the monotonicity of the capacitor array may be difficult for any external circuits as the capacitance values of the capacitor array may be very small compared to parasitic capacitance for example of interconnections between the test circuit and the chip.

In particular, the capacitor array is tested automatically, i.e. an automatic build-in self test is provided. Merely a starting signal must be initiated. The test circuit will automatically be triggered when the result is available. The testing of the circuits on chip may be performed during waiting time without hindering the processing of the internal circuits.

The above-mentioned test circuit can be used to verify all possible capacitance values of the capacitor bank. However, it may be sufficient to monitor the most critical transitions, namely: (a) 011111 «^■ 100000

(b) 001111 «■ 010000

(c) 000111 «■ 001000

It should be noted that the above three most critical transitions are only depicted for a capacitor bank with six capacitors. These values are only shown as an example for illustrating the principles of the invention and should not be considered as restrictive. In particular, the capacitor bank may comprise a greater number of capacitors.

Fig.3 shows a timing diagram of a test circuit according to Fig. 2. The first signal corresponds to the state of the first switch Iso, the second waveform corresponds to the switch Dis associated to the resistor R_DIS and the third waveform corresponds to the switches Sw[O :n]. The state of the second switch Sc, the state of the comparator Comp, the waveform of the counter C, the waveform of the clock signal elk and the values in the register reg are also depicted.

As an example, a first configuration for the capacitor bank of 011111 (indicating which switch is closed "1" and which is opened "0") may be initially chosen and the capacitor bank is set accordingly. Those capacitors in the capacitor bank whose associated switches are closed are charged by a constant current generator Ic. The time which the constant current generator needs to charge all the capacitors whose associated switches are closed, to a predetermined reference voltage V_ref is determined. The counter C is used to determine the number k of cycles of the reference clock elk which elapse during that time. The register reg stores this number k. Thereafter, the counter is reset and the corresponding comparator input lines are discharged. Then, the capacitor banks and its associated switches are switched to a second configuration 100000. Those capacitors of the capacitor bank whose switches are closed are charged with the constant current generator Ic and the time required by the constant current generator to charge the capacitors to the reference voltage is determined by the counter and may optionally be stored in the register reg as mentioned above. This time can be considered as m cycles of the reference clock.

If the value of k and the value of m is compared by the state machine unit SM and if k < m, then a first condition is verified and the state machine will continue to a next check. If k > m, the test will be completed and a ready signal is output as "1" while the pass signal will be "0", i.e. the capacitor bank CB is non-monotonic

If all six measurements have been executed, a ready signal will be "1". If all three conditions have been satisfied, a pass signal will be output as "1", i.e. the capacitor bank is monotonic. This state is kept until the state machine unit SM is reset.

In other words the test can be performed for a transition from the 2ⁿ-l configuration (011111) to the 2ⁿ configuration (100000) of the capacitor bank. The time required by the capacitor banks to reach the reference voltage are compared to determine that the time required by the 2ⁿ-l configuration (011111) is less than the time required by the 2ⁿ configuration (100000). If this is true, them the capacitor bank can be considered as monotonic.

Accordingly, the above-mentioned method can be performed to verify the monotonicity of the capacitor array. According to the result of the monotonicity test, the tuning of the oscillator frequency will be performed according to the required tuning algorithm, i.e. either the tuning algorithm for a monotonic capacitor bank or a non-monotonic capacitor bank.

Fig.4 shows a schematic representation of a binary tree capacitor array according to the second embodiment. The capacitor array constitutes a six bits binary tree capacitor array. Within a binary tree capacitor array, each bit will correspond to a capacitor with the value of:

Fig.5 shows a further schematic representation of the binary tree capacitor array of Fig.4. Here, the configuration 100000 of the capacitor array will correspond to a value of the capacitor Cl.

Fig.6 shows a further schematic representation of the binary tree capacitor array of Fig.4. In Fig.6, the configuration of the capacitor array is switched from 100000 according to Fig.5 to 011111. Hence, the value of the capacitor array will correspond to the sum of the capacitors C2-C6. It should be noted that the actual value of the capacitance C1-C6 will depend on its silicon area as well as on the thickness of the oxide and that because of variations in the fabrication process, in particular on these parameters, the actual value of the respective capacitors may differ from the actual values of the capacitors as designed. Accordingly, a situation may occur where the left side of the area (Cl) may not be smaller than the right side (C2 - C6).

Fig.7 shows a schematic representation of a binary tree capacitor array according to a third embodiment. The binary tree capacitor array according to the third embodiment substantially corresponds to the binary tree capacitor array according to the second embodiment. However, the most significant and/or largest capacitor Cl (2^{n l} *C_step) is divided into two parts, CIa, CIb, i.e. each part CIa, CIb has the same size as the capacitance C2 (2("^"^¹ *C_step). Based on this structure, a configuration 100000 may be implemented by the capacitors CIa, C2 as shown in Fig.8 such that the value of the capacitor bank will correspond to CIa and C2.

Fig.9 shows a further schematic representation of the capacitor array of Fig.7. Here, a configuration of 011111 is depicted, i.e. the value of the capacitor array corresponds to the sum of C2-C6. Accordingly, in order to implement such a transition which is considered as most critical, only a quarter of the array needs to be switched.

Therefore, the required precision is merely half of that compared to a binary tree structure according to Fig.4, namely one least significant bit LSB as compared to a quarter of the array instead of one LSB compared to a half of the array.

The capacitor banks according to Figs.4 to 9 can be implemented as the capacitors banks CB according to Figs.2 and 3.

It should be noted that depending on the overall capacity of the capacitance array, the number of steps and the process variation, the above-mentioned procedure may be reiterated to achieve further steps.

Summarizing, a test method for testing the monotonicity of a capacitor array is shown. This test may be performed by a built-in on chip self test circuit. Furthermore, an implementation of the capacitor banks is shown to reduce the risk of a non- monotonicity. Here, one or more of the capacitors, preferably the largest capacitor, are split into two or more parts.

It should be noted that the implementation of the capacitor array according to the Figs.4 to 9 are merely shown to illustrate the basic principles of the invention and should not be considered as restrictive. In particular, the number of capacitors arranged in the capacitor array may vary according to the actual requirements.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. In the device claim enumerating several means, several of these means can be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Furthermore, any reference signs in the claims shall not be construed as limiting the scope of the claims.

Claims

CLAIMS:

1. Integrated circuit, comprising a capacitor bank (CB) having a plurality of capacitors (C1-C6) each with an associated switch (swl-sw6), and a test circuit for testing the capacitor bank (CB), said test circuit having a state machine unit (SM) for setting the switches

(swl-swn) in the capacitor bank (CB), a current generator (Ic) for generating a current to charge these capacitors (C1-C6) in the capacitor bank (CB) whose associated switches (swl-sw6) have been set by the state machine unit (SM), a comparator unit (CU) for comparing the voltages across the capacitors (C1-C6) in the capacitor bank (CB) with a reference voltage (V_REF), and a counter (C) for determining the time which the current generator (Ic) needs to charge the capacitors (C1-C6) until the voltage thereof corresponds to the reference voltage (VREF).

2. Integrated circuit according to claim 1, wherein the state machine unit (SM) is adapted to select a first configuration of the capacitor bank to be tested by setting the associated switches (swl-sw6).

3. Integrated circuit according to claim 2, wherein the state machine unit (SM) is adapted to select a second configuration of a capacitor bank after a first configuration of the capacitor bank has been tested in order to test critical transitions in the configuration of the capacitor bank (CB).

4. Integrated circuit according to claim 1, wherein the integrated circuit comprises a reference oscillator (Xtal) which is tuned by selecting the value of the capacitor bank (CB) by setting the respective switches (swl-sw6).

5. Integrated circuit according to claim 2 or 3, further comprising: a register unit (reg) for storing the results of the counter (C), wherein the state machine unit (SM) is adapted to compare the results of the counter (C) to determine the monotonicity of the capacitor bank (CB).

6. Method for testing a capacitor bank having a plurality of capacitors (C1-C6) each with an associated switch (swl-sw6), comprising the steps of: controlling the switches (swl-sw6) of the capacitor bank (CB), generating a current to charge those capacitors (C1-C6) in the capacitor bank (CB) whose associated switches (swl-sw6) have been set, comparing the voltages across the capacitors in the capacitor bank (CB) with a reference voltage, and determining the time which the current generator requires to charge the capacitors (C1-C6) until the voltages thereof correspond to the reference voltage

7. Integrated circuit, comprising a binary tree capacitor bank having n capacitors (C1-C6) and a switch (swl-sw6) associated to each of the capacitors (C1-C6); wherein the value of each capacitor (C1-C6) correspond to 2^1"1 times the value of a step capacitor (Cstep), wherein i is an integer from 1 to n; wherein at least a first capacitor (Cl) of the capacitor bank is divided into a first and second part (CIa, CIb).

8. Integrated circuit according to claim 7, wherein the first capacitor (Cl) corresponds to the largest capacitor (Cl) in the capacitor bank and comprises a capacitor value of 2"^"1 times the value of a step capacitor (Cstep), wherein the first capacitor (Cl) is divided in half.

9. Integrated circuit according to claim 7 or 8, wherein the most significant capacitor of the capacitor bank is formed by a first part (CIa) of the first capacitor (Cl) and by a second capacitor (C2) with a capacitor value of 2¹^^"1-*^"1 times the value of a step capacitor (Cstep).

10. Integrated circuit according to claim 7, further comprising a test circuit for testing the capacitor bank (CB), said test circuit having a state machine unit (SM) for setting the switches (swl-swn) in the capacitor bank (CB), a current generator (Ic) for generating a current to charge these capacitors (C1-C6) in the capacitor bank (CB) whose associated switches (sw- sw6) have been set by the state machine unit (SM), a comparator unit (CU) for comparing the voltages across the capacitors (C1-C6) in the capacitor bank (CB) with a reference voltage (V_REF), and a counter (C) for determining the time which the current generator (Ic) needs to charge the capacitors (C1-C6) until the voltage thereof corresponds to the reference voltage (VREF).

11. Device comprising an integrated circuit according to claim 1 or 7.