WO2007113757A3 - System and method for supporting a hot-word-first request policy for a multi-heirarchical memory system - Google Patents

System and method for supporting a hot-word-first request policy for a multi-heirarchical memory system Download PDF

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Publication number
WO2007113757A3
WO2007113757A3 PCT/IB2007/051135 IB2007051135W WO2007113757A3 WO 2007113757 A3 WO2007113757 A3 WO 2007113757A3 IB 2007051135 W IB2007051135 W IB 2007051135W WO 2007113757 A3 WO2007113757 A3 WO 2007113757A3
Authority
WO
WIPO (PCT)
Prior art keywords
data
block size
level memory
customized
cache system
Prior art date
Application number
PCT/IB2007/051135
Other languages
French (fr)
Other versions
WO2007113757A2 (en
Inventor
Miland Manohar Kulkarni
Original Assignee
Koninkl Philips Electronics Nv
Miland Manohar Kulkarni
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv, Miland Manohar Kulkarni filed Critical Koninkl Philips Electronics Nv
Publication of WO2007113757A2 publication Critical patent/WO2007113757A2/en
Publication of WO2007113757A3 publication Critical patent/WO2007113757A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0879—Burst mode

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

Fetching data from a low level memory utilizing customized data requests based on a determination of the spatial locality of a currently running task/transaction. One of two customized requests are issued from a cache system to a low level memory (20). In the case where the spatial locality information is determined to be above a predetermined threshold value, a first customized data request (type-one) is issued to the low-level memory (20) which retrieves data in a single operation with a block size equal to the block size of a higher order cache (18) in the cache system (10). Otherwise, in the case where the spatial locality information is determined to be below the predetermined threshold value, a second customized data request (type-two) is issued from the cache system (10) to the low-level memory (10). The type-two data request comprises multiple data requests where each individual data request retrieves data for a block size equal to the block size of a level one (Ll) cache (16A-16C) in the cache system (10).
PCT/IB2007/051135 2006-04-04 2007-03-29 System and method for supporting a hot-word-first request policy for a multi-heirarchical memory system WO2007113757A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US78955606P 2006-04-04 2006-04-04
US60/789,556 2006-04-04

Publications (2)

Publication Number Publication Date
WO2007113757A2 WO2007113757A2 (en) 2007-10-11
WO2007113757A3 true WO2007113757A3 (en) 2007-12-13

Family

ID=38432907

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2007/051135 WO2007113757A2 (en) 2006-04-04 2007-03-29 System and method for supporting a hot-word-first request policy for a multi-heirarchical memory system

Country Status (1)

Country Link
WO (1) WO2007113757A2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104572502A (en) * 2015-01-12 2015-04-29 浪潮电子信息产业股份有限公司 Self-adaptive method for cache strategy of storage system

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5700262B2 (en) 2010-02-24 2015-04-15 マーベル ワールド トレード リミテッド Cache based on spatial distribution of access to data storage devices
US9678868B2 (en) 2014-10-31 2017-06-13 Xiaomi Inc. Method and device for optimizing memory
US9811464B2 (en) * 2014-12-11 2017-11-07 Intel Corporation Apparatus and method for considering spatial locality in loading data elements for execution

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6345334B1 (en) * 1998-01-07 2002-02-05 Nec Corporation High speed semiconductor memory device capable of changing data sequence for burst transmission
US20040049615A1 (en) * 2002-09-11 2004-03-11 Sunplus Technology Co., Ltd. Method and architecture capable of programming and controlling access data and instructions

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6345334B1 (en) * 1998-01-07 2002-02-05 Nec Corporation High speed semiconductor memory device capable of changing data sequence for burst transmission
US20040049615A1 (en) * 2002-09-11 2004-03-11 Sunplus Technology Co., Ltd. Method and architecture capable of programming and controlling access data and instructions

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JOHNSON T L ET AL: "Run-time spatial locality detection and optimization", PROCEEDINGS OF THE 30TH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE. MICRO-30. RESEARCH TRIANGLE PARK, NC, DEC. 1 - 3, 1997, PROCEEDINGS OF THE ANNUAL INTERNATIONAL SYMPOSIUM ON MICROARCHITEC TURE, LOS ALAMITOS, CA : IEEE COMPUTER SO, vol. 30TH CONF, 1 December 1997 (1997-12-01), pages 57 - 64, XP010261283, ISBN: 0-8186-7977-8 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104572502A (en) * 2015-01-12 2015-04-29 浪潮电子信息产业股份有限公司 Self-adaptive method for cache strategy of storage system

Also Published As

Publication number Publication date
WO2007113757A2 (en) 2007-10-11

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