WO2007111518A1 - Filling of nanoscale and microscale structures - Google Patents

Abstract

A method of depositing particles into a depressed region of a substrate comprising the steps of: a) providing of a substrate having a depressed region in its surface, the depressed region having a depth greater than the width of the depressed region and thereby an aspect ratio greater than 1, and at least one of the dimensions of the depressed region being less than 100 microns, b) providing of a source of particles, and c) directing the particles towards the substrate with kinetic energy sufficient to reduce or minimise adhesion of the particles to at least the sidewalls of the depressed region such that the particles fill at least part of the depth of the depressed region with particles.

Description

"FILLING OF NANOSCALE AND MICROSCALE STRUCTURES"

FIELD OF THE INVENTION

The present invention relates to a method of filling, at least partially, high aspect ratio trenches or other nanostructures or microstructures which have been formed into a substrate surface (for example by etching). More particularly but not exclusively it relates to a method of filling trenches on semiconductor substrates (or trenches in polymeric materials coated onto a substrate) with metals for interconnect applications or for filling trenches on metallic or dielectric substrates with dielectric materials for optical applications. In all cases the applications are both on the nanoscale and optionally up to the micron-scale.

BACKGROUND TO THE INVENTION

Over the past half century the microelectronics industry has developed a wide range of techniques for fabrication of electronic devices, interconnects and other structures on semiconductor wafers. These techniques have allowed continuous reduction in the dimensions of the features on an integrated circuit (IC) which have been largely responsible for a dramatic increase in computing power, as well as enabling new technologies such as cell phones and other consumer electronic devices.

Features on ICs are now routinely fabricated at dimensions smaller than lOOnm. It is now widely believed that many of the existing techniques used by the integrated circuit industry will be inadequate to further advance the development of ICs, and, in particular, that existing techniques for fabrication of interconnects (i.e. the electrical connections between devices on an IC) will be difficult to apply to the next generation of interconnect structures.

In order to reduce the amount of surface area taken up with interconnect structures on an IC, the industry has developed techniques for fabricating deep, narrow trenches (i.e. with a high aspect ratio) and then filling them with a metal, such as copper. [1] However, because the openings of the trenches (at the substrate surface) are narrow, it is difficult to uniformly fill the trenches, and voids or other inhomogeneities in the resulting interconnects may give rise to undesirably high resistances and/or cause failure of the interconnect in operation.

In addition, the techniques currently utilised by industry to fill interconnect trenches result in a significant coverage of the surface of the substrate with metal. This metal must then be removed, usually by chemical and mechanical polishing (CMP). This is a relatively expensive ptocess and alternative processes which remove, or reduce, the need for a CMP step are highly desired.

Cluster deposition into relatively large (0.8 micron) holes with aspect ratios ~1 has been conducted using small (1000-2000 atom) Cu clusters in one previous study [2]. In that study it is reported that good hole filling was achieved "due to thermally induced mobility" when the substrate was heated during deposition to 500K but only at high cluster energies (>1 OeV/ atom).

In that work [2] the trench filling was understood within a "sticky ball" model in which clusters are assumed to adhere to the substrate on contact.

Finally, it is noted that many other industries have requirements for homogeneous filling of high aspect ratio trenches, and that the techniques described herein may find widespread application.

One such industry is the optical components industry, which fabricates, for example, wavepktes, by such methods [3]. Examples of the materials of interest include dielectrics (e.g., SiO₂), metals (e.g. aluminium), and dielectric/metal combinations trench-filled with various materials such as

TiO₂, SiO₂, HfO₂, Ta₂O₅ and Al₂O₃, and combinations thereof.

Any discussion of documents, acts, materials, devices, articles or the like which has been included in the present specification is solely for the purpose of providing a context for the present invention. It is not to be taken as an admission that any or all of these matters form part of the prior art base or were common general knowledge in the field relevant to the present invention as it existed before the priority date.

OBJECT OF THE INVENTION It is an object of the invention to provide a technique useful in fabrication of integrated circuits and/ or optical elements such as waveplates and/ or other such structures which comprise high aspect ratio nanostructures or microstructures and/or a technique which overcomes one or more of the abovementioned disadvantages and/ or a technique which at least provides the public with a useful alternative.

SUMMARY OF THE INVENTION

According to a first aspect of the invention there is provided a method of depositing particles into a depressed region of a substrate comprising the steps of: a) provision of a substrate having a depressed region in its surface, the depressed region having an aspect ratio greater than 1 and at least one of the dimensions of the depressed region being less than 100 microns, b) provision of a source of particles, c) directing the particles towards the substrate with kinetic energy sufficient to reduce or minimise adhesion of the particles to at least the sidewalls of the depressed region such that the particles fill at least patt of the depth of the depressed region with particles.

Preferably a major part of the depth of the depressed region is filled with particles and more preferably the depth of the depressed region is substantially fully filled with particles. Preferably the depression fills generally from the bottom first.

Preferably at least one of the dimensions of the depressed region is less than 1 micron, more preferably less than lOOnm.

Preferably the depressed region is a trench.

Preferably the trench has an aspect ratio greater than 3. More preferably the trench has an aspect ratio greater than 10.

^"Preferably the trench has an approximately rectangular vertical cross section.

Preferably the particles are atomic clusters.

Preferably the clusters are of two or more atoms which may or may not be of the same element.

Preferably the clusters are nanoscale of uniform or non-uniform size; and the average diameter of the clusters is between 0.5nm and l,000nm. More preferably the average diameter of the clusters is between 0.5nm and lOOnm; even more preferably the average diameter of the clusters is between 0.5nm and 40nm.

Preferably the momentum of die clusters is sufficient to cause the clusters to fill the depression or trough substantially from the bottom. More preferably the momentum is sufficient to minimise clogging of the depression or trough from the sides and/ or about the neck or the depression.

Preferably the particles have diameters in the range 1- 50nrn. More preferably the particles have diameters smaller than 25 nm. More preferably the particles have diameters smaller than 15 nm.

Preferably in step c) the velocity of the particles is greater than 10m/s. More preferably the velocity of the particles is greater than 100m/s.

Preferably the velocity of a particle of a particular size is chosen so that the kinetic energy of the particle is greater than the energy of attachment to the surface.

Preferably the velocity of the clusters is controlled by the flow rate of the inert gas that is introduced to the cluster source chamber.

Preferably the velocity of the particles is controlled by controlling an accelerating or decelerating potential.

Preferably the kinetic energy per atom of the particles is less than lOeV/atom., IeV/ atom, or

Preferably the particles impact on the sidewalls of the trenches or nanostructures or microstructures at glancing incidence.

Preferably the substrate is rotated, for example to a position or angle, so as to encourage the bouncing of particles from the surface of the substrate while encouraging the particles to accumulate in the depression (i.e. while maintaining the sidewalls of the trench parallel to the cluster beam).

Optionally there may be one or more steps during or after the method, of removal of excess cluster material from the substrate. Preferably this step is a step which may include chemical and/ or mechanical polishing. More preferably the clusters are removed from the surface by simple wiping of the surface. Optionally again the method may include overfilling the depression with particles so as to form the T-gate of a transistor.

In one embodiment of the fitst aspect of the invention, the depressed region or trench is disposed between two devices, two electrical contacts, or two regions of the substrate which may be engineered to become devices or contacts, so that, when the region or trench is filled with a plurality of conductive clusters, a current carrying pathway is formed between the devices, contacts or regions of the substrate.

Preferably the current carrying pathway is an interconnect.

In one preferred form the substrate is (fully or partially) a semiconductor. More preferably it is silicon, even more preferably doped silicon.

In another preferred form the substrate is polymeric. Preferably it is SU8, polyamide, polyimide, or PMGI

Preferably the substrate is covered with dielectric material. More preferably it is a dielectric material with dielectric constant <3.8.

Preferably the substrate further includes (or is provided with) a barrier material or seed layer which covers at least part of the surface of the depressed region or trench. Preferably the barrier layer or seed layer covers substantially all the surface of the depressed region or trench.

Preferably the barrier or seed material or material derived from the seed material is one which causes the cluster material to wet the surface of the trench. Preferably the barrier or seed material is one which causes the cluster material to wet the surface of the trench during an annealing stage subsequent to the deposition of the clusters. Preferably the barrier material is one of TiN, TiSiN, Ta, TaSiN, Hf, HfN, TaN, Ru, RuO₂ or BC_xN₇. Preferably, the seed layer is one of Cu, Ru, Pt, Al or Pd.

Preferably the material of the clusters is highly conductive in its bulk form.

More preferably the clusters are Cu or Al clusters.

Preferably following or during step d) there is a further step of annealing of the clusters. In one form of the fitst embodiment clusters ate annealed during deposition in the trench. More preferably the clusters are annealed in hydrogen or other reducing atmosphere. More preferably the hydrogen pressure is in the range O.ltorr to lOOtorr and the substrate temperature is in the range IOOC to 600C. Most preferably the hydrogen pressure is in the range 5torr to 50torr and the substrate temperature is in the range 200C to 500C.

In a second form of the first embodiment the clusters are annealed after deposition in the trench. More preferably the clusters are annealed in hydrogen or other reducing atmosphere. More preferably the hydrogen pressure is in the range O.ltorr to lOOtorr and the substrate temperature is in the range IOOC to 600C. Most preferably the hydrogen pressure is in the range 5torr to 50torr and the substrate temperature is in the range 200C to 500C.

In a second embodiment of the first aspect of the invention the substrate includes a plurality of depressed regions formed in its surface.

Preferably at least one of the depressed regions is a trench. Preferably there is a plurality of trenches ordered or arranged with respect to each other.

Preferably the plurality of trenches are so arranged so as to form the optical component of a waveplate, polarizer or retarder once filled with particles or clusters.

Preferably the trenches form nanogratings.

Preferably the nanogratings have a regular period and a regular linewidth.

Preferably the substrate is a dielectric. More preferably the substrate is SiO₂, Al₂O₃, or one of a number of other such materials. Preferably the substrate is transparent. Alternatively the substrate is metallic. More preferably the substrate is aluminium, copper or silver. Alternatively the substrate is a dielectric/metal combination. Alternatively the substrate, part of the substrate, or a substrate coating is polymeric. Preferably it is SU8, polyamide, polyimide, or PMGI.

Preferably the trenches are filled with clusters of materials such as TiO₂, SiO₂, HfO₂, Ta₂O₅ or Al₂O₃, or combinations thereof. Preferably the trenches are filled with clusters of materials such as Ti, Si, Hf, Ta or Al, or combinations thereof, which are then oxidised.

Preferably there is a step subsequent to the cluster deposition in which a polymer, glue, resist or other similar material is applied to the surface. Preferably that material adheres to the surface. Preferably that material encapsulates the cluster material in the trenches. Preferably that material is initially liquid and fills any voids between the clusters prior to becoming solid. Preferably that material can be hardened or ripened by diermal annealing or UV-exposure.

Preferably following or during step d) there is a further step of annealing of the clusters.

In one form of the first embodiment clusters are annealed during deposition in the trench. More preferably the clusters are annealed in hydrogen or other reducing atmosphere. More preferably the hydrogen pressure is in the range O.ltorr to lOOtorr and the substrate temperature is in the range IOOC to 600C. Most preferably the hydrogen pressure is in the range 5torr to 50torr and the substrate temperature is in the range 200C to 500C.

In a second form of the first embodiment the clusters are annealed after deposition in die trench. More preferably the clusters are annealed in hydrogen or other reducing atmosphere. More preferably the hydrogen pressure is in the range O.ltorr to lOOtorr and the substrate temperature is in the range IOOC to 600C. Most preferably the hydrogen pressure is in the range 5torr to 50torr and the substrate temperature is in the range 200C to 500C.

According to a further aspect of the invention there is provided a substrate including one of more depressed regions filled with particles prepared substantially as herein described with reference to any one or more of the figures and/ or examples.

According to a further aspect of the invention there is provided a substrate including one or more depressed regions filled with particles prepared substantially according to the above method.

According to a further aspect of the invention there is provided an integrated circuit including an interconnect prepared substantially according to the above method. According to a further aspect of the invention there is provided aft optical component including one or more depressed regions tilled with particles prepared substantially according to the above method.

This invention may also be said broadly to consist in the parts, elements and features referred to or indicated in the specification of the application, individually or collectively, and any or all combinations of any two or more of said parts, elements or features, and where specific integers are mentioned herein which have known equivalents in the art to which this invention relates, such known equivalents are deemed to be incorporated herein as if individually set forth.

DEFINITIONS

"Particle" as used herein has the following meaning - a particle with dimensions in the range 0.5nm to lOOmicrons, which includes atomic clusters formed by inert gas aggregation or otherwise.

"Nanoparticle" as used herein has the following meaning - a particle with dimensions in the range 0.5 to 1000 nanometres, which includes atomic clusters formed by inert gas aggregation or otherwise. "Nanoscale" as used herein has the following meaning - having one or more dimensions in the range 0.5 to 1000 nanometres.

"Micronscale" as used herein has the following meaning - having one or more dimensions in the range 1 to 1000 micrometers.

"Cluster" as used herein has the following meaning - a particle with dimensions in the range 0.5 to 1000 nanometres, which includes atomic clusters formed by inert gas aggregation or otherwise. It is typically composed of between 2 and 10⁷ atoms.

"Contact" as used herein has the following meaning — an area on a substrate, usually but not exclusively comprising an evaporated metal layer, whose purpose is to provide an electrical connection between a device or surface feature and an external circuit or another electronic device. "Substrate" as used herein has the following meaning - an insulating or semiconducting material comprising one or more layers which is used as the structural foundation for the fabrication of the device. The substrate may be modified by the deposition of electrical contacts, by doping or by lithographic processes intended to cause the formation of surface texturing. The substrate may be a polymeric material, in which case the polymer would normally be chosen to be one with favourable mechanical properties, such as strength, thermal stability and robustness against damage during subsequent chemical processing, e.g. SU8 and PMGI. "Pathway" as used herein has the following meaning — a structure made up of individual units which may or may not be wholly interconnected (i.e. while it maybe a connected network, there may also be some spaces between the units). Like a wire it is not restricted to a single linear form but may be direct, or indirect. It may also have side branches or other structures associated with it. The particles may or may not be partially or fully coalesced. The definition of pathway may even include a film of particles which is not homogeneous. The pathway may or may not conduct. "Wires" as formed according to the method of the invention is a subset of "pathway". "Interconnect" as used herein has the following meaning - an electrical conduction path between devices on a integrated circuit which includes wires, vias, studs etc. "T tench" as used herein has the following meaning - a channel or depression in the substrate, which may be regular or irregular, and which has an approximately rectangular vertical cross- section and which is typically much longer than is is wide or deep. "Aspect Ratio" as used herein has the following meaning — the relationship between the depth and the width of a trench or other depression in the surface of the substrate, i.e. for an aspect ratio of 2 the depth of the trench is twice that of the width.

"High Aspect Ratio" as used herein has the following meaning — a ratio between the trench or depression depth and width greater than 1 i.e. the depression is deeper than it is wide. "Depressed Region" as used herein has the following meaning — a region in the surface of the substrate lower than the general level of the substrate. It may be a regular or irregular region, already present in the substrate or formed there for the purposes of the method. It may be elongate or single point or any other arrangement.

"Nanograting" as used herein has the following meaning — fine grooves, trenches, wires or rulings with widths in the sub-micron regime often formed in parallel and equally spaced patterns on a substrate.

"Wave Plate" as used herein has the following meaning - an optical device that alters the polarization state of a light wave travelling through it. "Polatiser" as used herein has the following meaning - a device that converts an unpolarized or mixed-polarization beam of electromagnetic waves (e.g., light) into a beam with a single polarization state (usually, a single linear polarization) "Retarder" as used herein has the following meaning - an optical device that alters the polarization state of a light wave travelling through it. "Filled" means having accumulated material substantially from the bottom of the depression and preferentially without the formation of significant voids. "glancing incidence" means incident with a trajectory that makes an angle of no more than 20 degrees to the plane of the surface in question.

"seed layei" means a replacement for, or additional layer on top of, the barrier layer such as that indicated in figure 1 which promotes the growth or annealing of a layer of clusters or other subsequently deposited material.

"PMGI" means Polymethylglutarimide which is a positive tone resist with very unique material and performance properties. It is ideally suited for multilayer applications such as lift-off processing and T-gate and airbridge fabrication.

"SU8" means a polyepoxyfunctional resin and in particular a polyepoxyfunctional novolak resin, which may in one form have an average of about eight epoxy functional groups. Such a resin is available in various formulations e.g. SU8-2000 and SU8-3000 but these are based on the EPON SU8 epoxy from Shell Chemicals (US Patent No. 4882245 (1989)). The cross-linked film is resistant to most alkaline & acidic solutions.

As used herein the term "and/or" means "and" or "or", or both.

As used herein "(s)" following a noun means the plural and/ or singular forms of the noun. "The term "comprising" as used in this specification and claims means " consisting at least in part of"; that is to say when interpreting statements in this specification and claims which include "comprising", features, other than those prefaced by this term in each statement, can also be present. Related terms such as "comprise" and "comprised" are to be interpreted in similar manner."

Other aspects of the invention may become apparent from the following description which is given by way of example only and with reference to the accompanying drawings

BRIEF DESCRIPTION OF THE FIGURES

The invention is further described with reference to the accompanying figures: Figure 1. Schematic of a trench in a semiconductor substrate coated with a barrier material.

Figure 2. Micrographs (top view SEM) of clusters deposited on various planar surfaces. Figure 3. Micrographs (XSEM) showing near complete trench filling for 400nm dense trenches (a), 300nm dense trenches (b), 240nm iso trenches (c) and 195nm dense trenches (d). Figure 4. Micrographs (XSEM) showing cluster size for clusters generated with 800sccm

Ar, Power of 10OW, and aggregation length of 13cm. Figure 5. Micrographs (XSEM) showing near complete filling for sub-200nm trenches with source conditions which produce cluster sizes around 24nm. Figure 6. Micrographs (XSEM) showing near complete trench filling with cluster sizes around 16nm. Figure 7. Micrographs (XSEM) showing that clusters with insufficient momentum stick to trench side walls. Figure 8. Micrographs (XSEM) showing that clusters with insufficient momentum stick to ^• the top plateau and close the trench opening.

Figure 9. Micrographs showing incomplete sintering of clusters (Lagg=13cm) in various trenches under a vacuum anneal.

Figure 10. Micrographs (XSEM) showing incomplete sintering of clusters (Lagg=llcm) in various trenches under a vacuum anneal. Figure 11. Micrographs (XSEM) showing result of annealing clusters in 5Torr of H₂ at 350⁰C for lhr. Figure 12. Micrographs (top view SEM) showing excellent selectivity on trenches coated with Ru(O_x) Figure 13. Micrographs (XSEM) showing complete filling of trenches even for sub-lOOnm trenches coated, with Ru(O_x).

Figure 14. Micrographs (top view SEM) showing that with optimized deposition time, the trenches of different width can be completely filled without many clusters on the plateau.

Figure 15. Micrographs (top view SEM) showing Cluster deposition on Ru(O_x) film has been reduced by pre-annealing in H₂ at 200⁰C for 30min prior to deposition.

Figure 16. Micrographs (XSEM) showing complete trench filling of Ru(O_x) trenches with clusters of diameter around llnm.

Figure 17. Micrographs (XSEM) of clusters in Ru(O_x) trenches after exposure to the atmosphere and annealing in vacuum at 400⁰C for Ihour.

Figure 18. Micrographs (left: XSEM, right: top view SEM) showing clusters subjected to vacuum anneal at 400⁰C immediately after deposition. Figure 19. The same sample as shown in the previous figure after exposure to H₂ ambient and annealing at 400⁰C for Ihour.

Figure 20. Micrographs (XSEM) showing result of H₂ annealing immediately after deposition for a sample with no excess of copper on the sample surface.

Figure 21. Micrographs (XSEM) of trenches covered with a Cu seed layer. Figure 22. Micrographs (top view SEM) showing excellent selectivity observed on trenches with a Cu seed layer. Figure 23. Micrographs (XSEM) showing trenches as narrow as 145nm have been fully filled with clusters. Cluster size is around 20nm. Figure 24. Micrographs (top view SEM) showing excellent selectivity and trench filling with cluster size around 12 to 15nm. Figure 25. Micrographs (XSEM) showing cross-sectional SEM view of clusters on Cu seed layer annealed in vacuum at 400⁰C for lhour.

Figure 26. Micrographs (XSEM) showing cross sectional view SEM of clusters deposited at 400⁰C and annealed in vacuum at 400⁰C for lhour.

Figure 27. Micrographs (XSEM) showing cross sectional SEM view of clusters deposited on

Cu seed layer and H2 annealed at 400⁰C for lhour. Figure 28. Micrographs (top view SEM) showing top view SEM images of small clusters deposited on Cu seed layer trenches before and after annealing. Figure 29. Micrographs (XSEM) showing cross-sectional SEM image of the same sample as in. the previous figure. Figure 30. Micrographs (XSEM) showing with higher temperature annealing for a longer period clusters coalesce into the Cu seed layer and form continuous wires within the trenches.

Figure 31 Micrographs (XSEM) showing trench fining incomplete, due to inadequate bouncing of clusters on the plateau.

Figure 32 Micrographs (XSEM) showing excellent selectivity using a de Laval nozzle

Figure 33 Cluster velocities as a function of size at different gas flow conditions.

Figure 34 Schematic of a multilevel interconnect structure prepared in SU8 (or other robust polymer) trenches.

Figure 35 Schematic of a T-gate transistor prepared in a SU8 (or other robust polymer) template. Figure 36. SEM images of Bi clusters on planar (a) SiO_x, (b) Si₃N₄, (c) Au and (d) SU8 surfaces. Figure 37 The measured cluster coverage on SiO_x, Si₃N₄, Au and SU8 surfaces after three differing deposition periods. Figure 38. (a) SEM image of a 100 μm long Bi cluster-assembled interconnect with a minimum width of 600nm and (b) its post-formation in-vacuum 1(V) plot. The inset to (a) is a high resolution image of the interconnect and the relatively small number of clusters on the surrounding SU8 plateau. Figure 39. The 1(V) characteristics of a Bi cluster-assembled interconnect (length lOOμm and minimum width lμm) at 300K, 330K, 370K, 400K, 430K and 460K. (The resistance of the wire decreases with increasing temperature).

Figure 40. Bi cluster-assembled wires formed in aperture slots in an SU8 layer. The wire

(with width ~0.6μm) in (a) has been subject to a maximum temperature of 300K whilst the wire (with width ~lμm) in (b) has been subject to a maximum temperature of 460K. Figure 41. A Bi cluster-assembled wire that was annealed in high-vacuum at a temperature of 600K. A Si₃N₄ coated substrate supports the wire and SU8 template layer

Figure 42. An SEM image (a) and AFM image (b) of a contacted Bi cluster-assembled interconnect formed on SiN using a patterned SU8 layer with thickness 50nm. The minimum width of the wire is approximately 350nm and the thickness is approximately 300nm.

DETAILED DESCRIPTION OF THE INVENTION

The present invention provides a novel method of filling high aspect ratio trenches or other nano- and micro- scale structures with particles (particularly clusters, more particularly nanoclusters), particularly in order to form interconnect structures. The invention includes the steps of cluster (and herein after the term "clusters" will be often be used, for convenience) deposition but may also include annealing during cluster deposition and/ or annealing subsequent to the deposition in order to compact or sinter the clusters, for example in order to form a solid conductor. More particularly the invention may include the step of a hydrogen anneal in order to remove oxides from the surface of the clusters and/ or the barrier material coating the trench walls, thereby enhancing the coalescence or sintering of the clusters. The advantages of the technology (compared with many competing technologies) include that: the clusters bounce from the sidewalls of the typically high aspect ratio trenches or other nano- and micro- scale structures so that they are directed towards the bottom of the high aspect ratio trenches or other nano- and micro- scale structures, thereby ensuring the trench fills (at least substantially) from the bottom thereby reducing the possibility of the formation of voids or other defects in the resulting structure The clusters bounce from the surface of the substrate into which the high aspect ratio trenches or other nano- and micro- scale structures have been etched, thereby reducing the amount of unwanted material covering the surface of the substrate. This is advantageous since in many applications removal of material on the surface of the substrate is problematic and/ or expensive and/or time consuming.

The clusters which do accumulate on the surface may be easily removed since they may not adhere strongly.

A. METHOD OF THE INVENTION The invention relies upon a number of steps and/ or techniques:

1. Preparation/Provision of a substrate with typically high aspect ratio mnostructures or microstructures defined in its surface,

2. the formation of atomic clusters,

3. deposition of the clusters onto the substrate and into the high aspect ratio nanostructures or microstructures defined in its surface,

4. optionally: annealing the clusters either during or after deposition.

5. optionally: removing the clusters from the surface of the substrate one or more times during or after above process.

1. Preparation /Provision of a Substrate

The substrates used in the present work were fabricated by standard commercial microelectronics industry processes (see for example [I]).

2. Formation of atomic clusters Metal vapour is evaporated into a flowing inert gas stream which causes the condensation of the metal vapour into small particles. The particles are carried through a nozzle by the inert gas stream so that a molecular beam is formed. Particles from the beam can be deposited onto a suitable substrate. This process is known as inert gas aggregation (IGA), but clusters could equally well be formed using cluster sources of any other design (see e.g. the sources described in the review [4], but most particularly by sputtering of the cluster material from a target). Clusters could be of Si, Pd, Pt, Cu, Bi, Pb, Sb, Ag and Au or of many other materials. We prefer Cu, AJ, Si, Bi, Sb, and Pd. Sizes of cluster can range from less than 0.5nm to lOOOnm in diameter. We prefer clusters with diameters in the l-50nm range and an apparatus as described in [6].

3. Deposition of the clusters onto the substrate The basic design of a cluster deposition system is described in Refs [5] and [6], the contents of which are hereby incorporated by way of reference. In the preferred form, following the cluster source is a series of differentially pumped chambers allow ionisation, size selection, acceleration and focussing of clusters before they are finally deposited on a substrate. In fact, while such an elaborate system is desirable, it is not essential, and our devices have frequently been formed in relatively poor vacuums without ionisation, size selection, acceleration or focussing.

It is a feature of the deposition systems described in Refs. [5,6] that the flowing inert gas stream, and the clusters contained within it, is accelerated by the flow of gas through the nozzles between differential pumping stages. There may be a supersonic expansion at one or more nozzles. This results in clusters with some degree of transktional kinetic energy, which is directed towards the substrate, and which is in fact crucial to the invention.

A feature of our technique is that the clusters deposited within trenches, or other flanostructures or microstructures, form a substantially continuous layer of material within the trench, or other nanostructure or microstructure. Deposition of atomic vapour from a standard evaporator would result in metallic layers blanketing the surface of the substrate but would produce very little coverage of the sides or bottom of any trenches, or other nanostructures or microstructures.

A further feature of the invention is that the deposited clusters adhere weakly to the surface of the substrate (i.e. the planar regions between trenches, or other nanostructures or microstructures) i.e. preferentially the substrate surface material and cluster materials are such that the clusters bounce from the substrate surface material, while accumulating in the trench, or other nanostructure or microstructure. This is important because in alternate processes [1] it is common for a thick layer of deposited material to build up on the planar substrate surface, necessitating expensive and time-consuming CMP processes to remove the accumulated material.

4. Annealing of the clusters

One embodiment of the present invention includes the step of annealing during cluster deposition and also annealing subsequent to the deposition in order to compact or sinter the clusters, for example in order to form a solid conductor. More particularly the invention includes the step of a hydrogen anneal in order to remove oxides from the surface of the clusters and/or the barrier material coating the trench walls, thereby enhancing the coalescence or sintering of the clusters. 5. Successful Filling of the trenches or depressions

In the preferred embodiment, the invention, involves deposition of particles (clusters) into micro- and/or nanoscale voids or depressions formed on a substrate. The voids or depressions in the substrate are formed using the standard lithographic and/or etching techniques of the micorelectronics industry.

The invention is applicable to a variety of cluster/substrate systems and the size of the incident clusters is unimportant so long as the clusters are smaller than the openings in the substrate surface. Preferably the average cluster kinetic energy is sufficient to prevent adhesion on the surface of the substrate and to the walls of the nanoscale or microscale aperture in the substrate surface, so that clusters accumulate first at the bottom of the nanoscale or microscale aperture, and subsequently fill up the trench. The kinetic energy of the incident clusters can be adjusted via the source inlet gas flow or via applied electrostatic potentials. The bouncing of clusters from surfaces was studied extensively in [7]. The bouncing of clusters from the flat surfaces between trenches may also be improved by tilting the sample, i.e. depositing the clusters at an angle.

The apparatus and the method according to the invention make it possible to fill with clusters a range of trenches, nanostructures and microstructures with widths from ~20nm to >100μm. The technique is not limited to wire-like patterns; also possible are arbitrarily shaped trenches, nanostructures and microstructures, so long as the opening of the trenches, nanostructures and microstructures are not smaller than the dimensions of any deeper part of the trenches, nanostructures and microstructures.

6. Cleaning the surface of the substrate In the preferred embodiment, the clusters typically do not adhere strongly to the planar (top) surface of the substrate, and so they may be simply wiped away. In an alternative embodiment standard CMP processes may be used to remove excess clusters.

B. APPLICATIONS OF THE INVENTION The apparatus and the method according to the present invention allow the filling of high aspect ratio nanostructures with clusters. In general this may result in cluster-assembled wires in the trenches or the filling of any other nanostructure. There are a wide range of applications of such nanostructures in micro and nanoelectronics, photonics, and in various biological systems. Here we describe briefly three applications, chosen from the microelectronics industry and from the optics industry, but we emphasise that there are many others. 1) Interconnects

As discussed above, the microelectronics industry requires new techniques which enable filling of high aspect ratio trenches with high density and uniform metals. In current process technologies, the emphasis is on formation of copper interconnects within trenches that are formed by anisotropic etching of a semiconducting substrate (101) and subsequent coating with a thin layer of a barrier material (102), resulting in a structure similar to that shown schematically in figure 1. The semiconducting material is typically silicon and the barrier material may be any one of a number of materials including TaN, Ru(O_x) [we use this notation to indicate that after preparation of a Ru thin film and subsequent exposure to air the oxidation state of the film is unknown] or Cu. Although Cu is currently the preferred material for the interconnect structure itself, Al has been used in the industry until recently and other highly conductive materials may be preferred for future generations of interconnects.

The microelectronics industry is continuously looking for new dielectric materials and new ways of patterning those materials in order to provide trenches which may be filled with metal and thereby form interconnects. A particular aspect of the present invention which may provide significant improvements on the techniques of the prior art is the formation of trench structures in SU8 or other mechanically robust polymeric materials such as polyamide, polyimide, or PMGI. One advantage of these materials is that they are patternable in 3 dimensions, thereby allowing different sizes and levels of interconnect structures to be prepared in a small number of lithographic steps, as illustrated schematically in Figure 34.

2) Optical devices

By etching deep trenches and other subwavelength nanostructures into the surface of an optical element it has been shown (see ref [3] and refs therein) that a wide variety of high performance optical components can be manufactured. These components, which include polarisers, retarders and waveplates, may rely on artificial birefringence which is a result of breaking the in-plane symmetry of the substrate material.

3) T-gate transistors In some iαtegtated circuits it is considered advantageous to engineer the gate structure of a transistor so as to achieve a small source-drain separation "while maintaining a relatively large dimension for part of the gate structure so as to allow a large current carrying capacity. The high degree of selectivity of the filling of trenches using the metho.d of the present invention allows for the formation of such T-gate structures by over-filling a trench such that clusters spill out of the trench across the neighbouring surface of the template in which the trench resides, as illustrated schematically in Figure 35.

EXPERIMENTAL 1. Characterisation of cluster-assembly on surfaces relevant to the microelectronics industry

The bouncing of clusters on different substrates can be measured by depositing clusters at coverages below the percolation threshold and then measuring the resulting surface coverage. By placing all the samples close to one another it is possible to ensure that the deposition rate and cluster size are consistent among all samples.

Figure 2 compares top view SEM images for clusters (F=800sccm Ar, P=IOOW, Lilian) deposited for 20min on Ru(O_x), Cu, SiO₂ and TaN surfaces. It is clear that the reflectivity of Cu clusters on those substrate goes as TaN>Cu>Ru(O_J1) >SiO₂. These results demonstrate that TaN and Cu surfaces are preferable for Cu cluster deposition on trenches or other nanostructures as the surface reflectivity is high, and this ensure that there is a low surface coverage on the plateaus between the trenches or other nanostructures, reducing the need for CMP or other processes which may be otherwise required to remove the excess cluster material.

2. Fabrication of trenches The trenches used in the present work were fabricated by standard commercial microelectronics industry processes [1], although the invention is not restricted to this. We can form suitable trenches or other depressions in the substrate surface as required.

3. Cluster-deposition Our preferred apparatus is described in Ref. [6] and an overview of the experimental techniques used is broadly given in [8]. Clusters are produced in an inert-gas condensation source. The apparatus may be operated with a thermal source or a magnetron source. When operated with the thermal source, metal contained in a crucible is heated and evaporated. The sputter source produces metallic or semiconducting vapour from a magnetron sputter head and can therefore produce clusters from materials with very high-melting points. In both the thermal and magnetron source the metallic/semiconducting vapour is mixed with inert gas which causes clusters to nucleate and grow. The cluster/gas mixture passes two stages of differential pumping (from ~1 Torr in the source chamber down to ~10^~6 Torr in the main chamber) such that most of the gas is extracted. The beam enters the main chamber through a nozzle having a diameter of about 1 mm and an opening angle of about 0.5 degrees. In order to determine the intensity of the cluster beam, a quartz crystal deposition rate monitor is used. The samples are mounted on a movable rod and are positioned in front of the quartz deposition rate monitor during deposition.

Note that the specific range of source parameters appears not to be critical: clusters can be produced over a wide range of pressures (0.01 torr to 100 torr) and evaporation temperatures and deposited at almost any pressure from 1 torr to 10^"12 torr. Any inert gas, or mixture of inert gases, can be used to cause aggregation, and any material that can be evaporated may be used to form clusters. The cluster size is determined by the interplay of gas pressure, gas type, metal evaporation temperature, and nozzle sizes used to connect the different chambers constituting the deposition apparatus.

4. Filling of trenches with Cu clusters

We present results for three types of commercially produced trenches i.e. those with TaN barrier layers, Ru(O_x) barrier layers, and those with Cu seed layers. For TaN and Ru(O_x) the samples contained structures with widths down to sub-200 nm. The highest aspect ratio (depth/width) of TaN samples and Ru(O_x) samples are 5:1 and 1:1.

Clusters were deposited in two main sets of conditions, namely pure Argon aggregation, and mixture of Argon and Helium aggregation. The pure Ar aggregation process produces clusters with 20-40nm in diameter; the mixture of Argon and Helium aggregation process produces clusters with 10-25nm in diameter. For most of the depositions, the magnetron power is 10OW.

The aggregation length of the clusters from the sputtering head to the nozzle is either 11cm or

13cm. All of the results discussed herein were obtained using the de Laval nozzle described below.

The cross sectional scanning electron microscope (XSEM) images of the deposition have been obtained by cleaving the sample after deposition, and viewed under microscope normal to the edge. 4.1 Depoήtion Results on TaN coated samples.

For cluster source conditions P=IOOW, 800sccm and L_agg=13cm, clusters fill lμrn deep trenches with various width, as shown in Figure 3. The correspondence cluster size is around 17nm as shown in Figure 4.

For cluster source conditions P=IOOW, 800sccm Ar and L =11 cm, the sub 200nm trenches have been near completely filled, as shown in Figure 5. The cluster size is around 24nm. This is larger than the clusters deposited with L_agg=13cm shown in Figure 4.

With additional Helium gas added as a cooling gas into the source (F=800sccm Ar, F=100sccm He, power=100W, L = 13cm), the clusters become smaller. Figure 6 shows the near complete trench filling and the clusters size around 16nm. In order to obtain still smaller clusters, we can use lower Ar flow and additional Helium. Figures 7 and Figure 8 show the trench filling and cluster size for Ar flows of 600sccm and He flow of lOOsccm and aggregation lengths of 13cm and 11cm respectively. In Figure 7 the Cluster size is around 12nm and clusters stick to the side- wall of the trenches and form "trees" growing out from the sidewalls since the clusters have insufficient momentum to overcome their attraction to the sidewalls of the trench. Similarly in Figure 8 the clusters also have insufficient momentum, and so they stick to the surface near the entrance of the trench and grow outwards, slowly covering the trench opening. This results in triangular cross-section "Christmas trees" which grow from the base of the trench. Clearly higher velocities would have been needed in these examples in order to obtain good trench filling.

4.2 Annealing Results on TaN coated samples.

Firstly, samples with trench filled clusters have been subjected to vacuum anneal at 400⁰C for lhour. The annealing result for clusters produced with F=800sccm Ar, P=IOOW, Lagg=13cm and Lagg=llcm are reported in Figure 9 and Figure 10 respectively. We observe that the clusters anneal into irregular shapes and the sintering of the clusters is incomplete. The agglomeration of the clusters has left holes in the trenches while the clusters filled the trenches during deposition.

Lastly, hydrogen annealing experiments have been conducted to understand the condensation of Cu clusters in the presence of hydrogen environment. As shown in Figure 11, Cu clusters (F=800sccm Ar, P=IOOW, Lagg=llcm) subjected to a hydrogen (~5 Torr pressure) anneal are sintered strongly. This is promising for application of the clusters in low resistivity Cu interconnects but clearly the tendency for the clusters to pull away from the trench walls and to leave voids around the compacted structures is undesirable. 4.3 Deposition Results on HfJf(O_x) coated samples.

Ru has been proposed by some manufacturers of Cu interconnects as a new barrier material and adhesion promoter. We have obtained commercially fabricated trenches coated with Ru with trench depths around 200-300nm. However we note that due to exposure to the atmosphere between production and experimentation, the surface layer of the Ru is likely to be at least partially oxidized, and so we refer to these samples as having Ru(O_x) barrier layers.

Figures 12 (source conditions: F=800sccm Ar, P=IOOW, Lagg=llcm), Figure 13 (F=800sccm Ar, P=IOOW₃ Lagg=llcm) and Figure 14 (F=800sccm Ar, P=IOOW, Lagg=llcm.), demonstrate that we have excellent selectivity on Ru(O_x) (i.e. minimal amounts of clusters are observed on the top of plateau while the trenches are filled), and excellent trench filling. Note that in the cross- sectional images the trenches have bowed outwards due to the effect of heating by the electron beam in the SEM.

Figure 12 shows that clusters can be almost entirely reflected from smooth areas of the wafer. Figure 14 shows that the deposition time can be optimized so that the trenches of different width can be completely filled with minimal clusters on the plateaus between trenches. With additional Helium gas, llnm clusters can be produced and these smaller clusters also fill the Ru(O_x) trenches, as indicated in figure 16 (source conditions: F=600sccm Ar=50sccm He, P=IOOW, Lagg=llcm).

It is believed that after fabrication the Ru coating on the trenches is oxidized to Ru(O_x). Figure 15 (source conditions: F=800sccm Ar, P=IOOW, Lagg=llcm) shows that there is indifference in selectivity when we reduce the Ru(O_x) prior to deposition. Compared to figure 14, the selectivity is about the same, except that the reduced sample was deposited on for slighdy longer.

4.4 Annealing Results on Ru(OJ coated samples.

Annealing experiments on the Ru(O_x) coated samples were conducted in vacuum, during deposition at different substrate temperatures, and in a hydrogen atmosphere.

Firstly, clusters (F=800sccm Ar₅ P=IOOW, Lagg=llcm) have been annealed in vacuum at 400⁰C after exposure to the atmosphere, as shown in Figure 17. Due to the exposure to the atmosphere, it is expected mat an oxide shell around the clusters may prevent aggregation of the clusters. However, since the cluster size has increased to around 35nm, it can be deduced that the clusters have been partially annealed. The increase in cluster size is probably due to agglomeration of smaller clusters into bigger clusters. However, the agglomeration of bigger clusters probably needs higher temperature to occur.

Secondly, clusters (F=800sccm Ar, P=IOOW, Lagg=llcm,) have been deposited at 400⁰C substrate temperature, and annealed in vacuum at the same temperature for lhour, as shown in Figure 18. The cluster size is again around 35nm. Note that in contrast to the TaN trenches, no degradation in the trench-fining is observed for deposition of clusters at elevated temperatures.

After exposure to the atmosphere, the same sample has been subjected to hydrogen (~5 Torr) annealing at 400⁰C for lhour. The clusters then agglomerate to enormously large (>400nm) particles, as shown in Figure 19. Extensive coalescence has occurred. In this case the coalescing surface particles appears to have pulled the Cu from the trenches towards the surface, possibly due to poor wetting of the trench surface and the effects of surface tension. It is expected that if the excess cluster material was removed from the surface before hydrogen annealing this would not occur.

In an additional experiment the excessive Cu clusters (F=800sccm Ar, P=IOOW, Lagg=llcm) on top of the plateau have been controlled by ensuring that the deposition stops when trenches are just filled and the clusters are not exposed to the atmosphere before annealing (~5Torr, 350⁰C for lhour), as in Figure 20. In this case large particles are formed and the copper is not pulled out of the trench because there is no excess Cu on the sample surface. We expect that a more favourable barrier material (e.g. Cu or unoxidised Ru) coating the trench walls would cause the annealed clusters to wet the trench walls.

4.5 Deposition Results on Cu-seed coated samples.

A further set of experiments have been conducted on commercial trenches covered with a Cu- seed layer. Figure 21 shows the Cu seed layer covering the trenches. The depth of the trenches is around 160nm, but the actual gap for Cu clusters to fill depends on the trench width and the Cu seed uniformity.

With similar deposition conditions as for the previous samples (F=800sccm Ar, P=IOOW,

Lagg=13cm), excellent selectivity was obtained (i.e. minimal amounts of clusters are observed on the top of plateau while the trenches are filled), as shown in Figure 22. Increasing the deposition time resulted in fully filled trenches (Figure 23). The cluster size is around 20nm. Changing the gas flow to a mixture of Ar and He, while keeping other parameters constants, reduces die cluster size to 12-15 run (F=600sccm Ar+50sccm He, P=IOOW, Lagg=13cm.). Similar selectivity can be observed with these smaller clusters, as shown in figure 24.

4.6 Annealing Jkesults on Cu-seed coated samples.

The effects of a range of annealing conditions on clusters deposited on a Cu seed layer are examined in this section. Firstly, the effect of vacuum annealing of the clusters is discussed. Then, the effect of elevated substrate temperature on the selectivity is studied. Finally, the impacts of hydrogen annealing with different clusters size are evaluated in greater detail.

A Cu-seed coated sample was deposited at room temperature with source conditions F=800sccm Ar, P=IOOW, L_agg=llcm. The sample was then annealed in vacuum at 400⁰C for lhour. The cross-sectional SEM images in figure 25 show that while the coalescence is incomplete the clusters have clearly begun to merge with each other and into the Cu seed layer, demonstrating that sintering is at least partially successful.

Cluster deposition (F=800sccm Ar, P=IOOW, L_agg=llcm) has been conducted while keeping the substrate at an elevated temperature of 400⁰C. The samples were then annealed at 400⁰C in vacuum for lhour. In this case clusters agglomerate but do not merge significantly into the Cu seed layer (Figure 26).

It is interesting to observe that the clusters deposited at room temperature merge into the Cu seed layer more readily than the clusters deposited at 400⁰C after annealing under the same conditions This could simply be an effect of the annealing time since the former sample was annealed during the 30-60 minutes it took to reach a stable temperature of 400⁰C.

Hydrogen annealing experiments were carried out with clusters created at F=800sccm Ar, P=IOOW and L₃^=HcIn. After exposure to the atmosphere, the sample was annealed in H₂ (~5 Tort) at 400⁰C for lhour. Figure 27 shows that the clusters fill the trenches completely (left) and cluster size is around 20nm (right). In contrast with the Ru(O_x) samples, clusters do not agglomerate to 35nm i.e. the majority of the clusters still remain as 20nm, and the seed layer seems to be rougher than original cross-section (figure 21). We believe that the small clusters coalesce into the Cu seed layer faster than they coalesce together. To test this hypothesis, we deposited smaller Cu clusters (F=600sccm Ar, P=IOOW, Lagg— 11cm) in room temperature and annealed in H₂ at 400⁰C for lhour. Figure 28 shows that top view SEM before and after annealing. Before annealing the trenches were completely filled, and size of clusters around 18nm. After annealing the trenches were not completely filled, and the size of clusters ranges from 13 to 44nm.

With smaller clusters, it appears that the rate of agglomeration increases while the rate of merging with the Cu seed layer only increases slightly, thus, both the agglomeration and merging are observed with this setting. It is clearly shown that clusters agglomerate as well as merge into the Cu seed layer in the cross-sectional SEM in figure 29.

We then made even smaller clusters (using He flow: F = όOOsccm Ar + lOOsccm He, P=IOOW, L_agg=llcm), and annealed in H₂ at higher temperatures and for a longer time (H₂ anneal at 450°C anneal for 2hour witiiout exposure to the atmosphere). Figure 30 shows that we can make densely packed Cu wires within the trenches. Note that the copper material within the trenches is quite homogeneous, indicating that cluster deposition and subsequent annealing has achieved the original goal of this development project, and that commercialisation of this process may be possible. Note that although the copper layer above the surface of the wafer is not homogeneous in Figure 30, this is unimportant as this layer would be removed (e.g. by CMP) in a commercial production environment.

To further demonstrate the effectiveness of the annealing procedures used here, Cu clusters of different sizes (15, 30nm) were generated in an IGA source and deposited on unpatterned samples with a barrier and copper seed. After annealing in H₂ at 450⁰C for 2 hours, the conductance and the thickness of the film were measured. From cross-sectional SEM images, a transition of smooth surfaces to rough surfaces and eventually a 3D porous network was observed for samples with increasing film thickness. Using a parallel resistor model, the resistivity of the cluster films was found to be 2.3 x 10^"8 Ω.m (for films < 120nm thick) in 30nm cluster film and 1.8 x 10^"8 Ω.m (for films < 50nm thick) in 15nm cluster film. These values are in fact close to the bulk resistivity (1.6 x 10^"8 Ωm) and the value required by industry (2.2 x 10^"8 Ωm). As the film thickness increases, the resistivity is observed to increase due to the increased porosity of the films — this effect will most likely be eliminated by improved annealing procedures, but large thicknesses are in any case not required for the small trenches / interconnects.

5. Selection of nozzles Various types of source nozzles have been tested. An 11mm long, 4mm diameter barrel nozzle resulted in cluster sizes around 7-1 Onm. A longer nozzle (17mm long and 4mm diameter) did not change the cluster size. This is understandable because the long barrel of the nozzle merely helps the collimation of the cluster beam, and not the formation of the clusters. Figure 31 shows the incomplete trench filling and the cluster size achieved using the 4mm diameter nozzle and source conditions F=400sccm Ar, P=IOOW, L_agg=15cm.

In subsequent experiments a convergent-divergent ("de Laval") nozzle with a narrow waist with a diameter around 3mm has been made to improve the velocity of the carrier gas exiting the nozzle, and hence the velocity of the clusters. The advantage of using a smaller diameter nozzle is that the pressure difference between source chamber and skimmer chamber is higher, and therefore increase the velocity of the clusters in order to obtain bouncing clusters. The de Laval nozzle is also expected to accelerate the exiting gas more than a simple barrel nozzle thus further increasing the velocity of the clusters. Note that the precise relative contributions of the reduction in nozzle diameter and shape of the nozzle to the increase in velocity are not clear at this stage. Figure 32 shows the excellent selectivity with a de Laval nozzle [9] with source conditions 700sccm Ar, P=IOOW, L_agg=13cm.

In order to characterize the velocity of the clusters, we have developed an ion deflector to mass select or measure the velocity of the clusters. The velocity measured with the de Laval nozzle is around 200 to 280m/s at 600 seem Ar, see figure 33. The cluster velocity depends to larger extent on the gas mixture than on the flow rate. This can be seen in figure 33 where the velocity is nearly identical for 600sccm and 750sccm argon, but increases significantly if a mixture of argon and helium is used. Helium has a higher thermal velocity exiting the source and may accelerate the cluster more than argon does.

We note that the kinetic energies of the clusters can be calculated from the data show in Figure 33 and illustrate this with the example of the data provided for 750sccm flow rate. In this case the 5nm and 25nm clusters have total kinetic energies ~160eV and ~10.1keV respectively, corresponding to kinetic energies per atom of ~0.03eV / atom and 0.015 eV / atom respectively. Values of <0.1eV/atom are traditionally considered to be in the "soft landing" regime, and in the case of the work of Ref [2] efficient filling of trenches was not possible at energies in this regime.

6. Deposition of Bi clusters on SU8 coated substrates and fabrication of structures using SUR SU8 is a negative resist which was originally developed for use in mictoelectromechanical systems as an optical resist [10] but patterning of this material can also be performed using electron-beam exposure [H]. Amongst many other attractive material properties, SU8 boasts a high degradation temperature [12] and a high sensitivity to optical and electron-beam exposure [13]. The patternability and long-term stability of SU8 make it an excellent choice as a permanent template layer for assembly of nanoscale particles. Its high temperature stability also enabled a preliminary study of annealing effects in Bi cluster-assembled wires to be incorporated into our experiments.

6.1. Preparation of SU8/ 'AM/ Si₃N₄/ SiO_x test substrates

Si substrates with planar layers of LPCVD-grown Si₃N₄, thermally-grown SiO_x, thermally evaporated Au and SU8 (2000-0.5 formulation) were prepared and clusters were deposited onto these substrates in order to determine the adhesion/reflection properties of the Bi-clusters on the respective layers. These were mounted on carriers and positioned on the sample arm of the deposition system so that the normally incident cluster-beam was centered on the intersection between the four samples. Only areas in the neighboring corners of the substrates (within a 200μm diameter area) were imaged in order to minimize differences in the deposition rate across the cluster beam spot. The effective cluster layer thickness required to produce a percolating cluster network on a contacted SiO_x passivated Si substrate was found and used as a calibration of the layer-thickness (the percolation threshold in the continuum model [14] occurs at a coverage of ~68%). Depositions onto the Si₃N₄/SiO_x/Au/SU8 samples were then performed with fixed deposition rates and periods which were varied to produce cluster-layer thicknesses of 0.22, 0.45, and 0.68 times the calibration layer-thickness. Once the depositions were complete, the cluster-coverage was measured from FE-SEM images using image processing software.

6.2. Preparation of SO 8 templated substrates

Si wafers with lOOnm thick Si₃N₄ or SiO_x layers were used as the substrate material for the contacted samples. Using optical lithography, planar Ti/ Au electrical contacts were formed on the surface of the wafer before it was diced into 10x1 Omm² substrates. SU8 was spun onto each substrate at 4000rpm for 45s to produce a layer of thickness 500nm, or the SU8 was diluted with GBL solvent and spun at 6000rpm for 45s to produce a layer of thickness 50nm. (The layer thicknesses were measured using AFM). The substrates were then baked for 2-mins on a hotplate at a temperature of 95⁰C and placed in a Raith 150 electron-beam writing system. The optimum electron-beam dose required for faithful reproduction of the desired patterns in the 500nm thick SU8 layers was found to be 0.9 x 10^'6 μC/cm² (using an accelerating voltage of 1OkV and an aperture of 10μm). When exposing the thinner SU8 layers, these operating parameters were maintained and consequently, over-exposure of the negative resist layer occurred. The lateral dimensions of the developed apertures were therefore smaller (by approximately 50nm) than intended. After removal from the electron-beam system, a 2-min 95°C post-exposure bake was performed on all samples. The samples were then developed for 40s in SU8 developer, rinsed with IPA and finally dried using N₂ gas.

Two SiO_x coated Si test samples (ie. without clusters) featuring patterned SU8 layers were subjected to a 1-hour 350°C oven bake in order to assess any degradation effects which might occur at elevated temperature during annealing. The samples were imaged in an SEM after the bake process and the aperture-slots remained intact with no measurable change in the average width or line edge roughness.

6.3. Bi Cluster production In this example the filling of trenches was illustrated using Bi clusters. Bi pellets (>99.999% purity) were evaporated from a filament-heated crucible in the source chamber of a UHV- compatible cluster deposition system [6] and the temperature of the crucible was monitored and controlled via a thermocouple. Once the temperature of the crucible is raised sufficiendy to achieve a vapor pressure of 0.1-1.0 mbar, clusters are grown from the supersaturated metallic vapour "within the source chamber. The growth process relies on the presence of an inert gas; for the Bi clusters produced here this is argon (>99.999% purity). The argon is fed through a flow controller and then directly into the source chamber. In addition to assisting with the cluster growth process, the Ar gas provides a means to control the average kinetic energy of the clusters [15]. A source exit nozzle generates an argon/cluster output beam which is directed through nozzles in two differential pumping stages and finally into a high vacuum chamber (base pressure ~10^"s mbar). The high vacuum chamber houses a sample arm/ shutter mechanism and a deposition rate monitor. The sample arm is designed to carry up to three contacted substrates. Three 10-pin electrical feedthroughs allow the conductivity between sample contacts to be monitored throughout the deposition experiment and 1(V) measurements to be performed on cluster-assembled films /wires. The deposition rate for a given Ar gas flow rate is adjusted via the temperature of the source and is monitored via a quartz crystal film thickness monitor (FTM) mounted behind the sample and inline with the cluster beam. A stable deposition rate is established using the FTM prior to deposition and die substrate holder is then moved in front of the FTM. An electronic shutter attached to the sample arm is opened in order to begin deposition onto the sample. For the work presented here, the samples were at room temperature during the deposition process.

6.4.. Bi clusters on SU 8, A.u, Si₃N₄ and SiO_x surfaces Figure 36 shows SiO_x, Si₃N₄, Au and SU8 surfaces (the SU8 layer was exposed and a postexposure bake was performed) after a cluster deposition process with a source-inlet Ar flow-rate of lOOsccm (corresponding to a calculated velocity of 50ms^"1, ignoring velocity slip [15]), a deposition rate of 0.34A/s and a deposition period of 100s. Clearly far fewer clusters have adhered to the SU8 layer than have adhered to the SiO_x, Si₃N₄ or Au layers. This experiment was performed using identical source conditions and three different deposition periods, which produced cluster-coverages on the SiO_x substrates ranging from ~0.2 to ~0.5 monolayers. The cluster-coverages were measured from FE-SEM images using image processing software and are shown in Figure 37. From the FTM layer thicknesses and the cluster-coverages measured on the samples, we estimate that at least 99% of the Bi clusters which were incident on the SU8 were reflected away from it. Similarly, we estimate that approximately 75% of the clusters which were incident upon the Si₃N₄ were reflected away. Hence, the number of Bi clusters found on the Si₃N₄, SiO_x and Au surfaces after each of these depositions was at least 25-times greater than the number found on the SU8 surfaces. Indeed, the coverage on the SU8 is so low that it suggests that clusters may only adhere when they are incident upon defects in the SU8 layer.

The mean and standard deviation of the diameter of the Bi clusters were measured from FE- SEM images of depositions on SiO_x and Si₃N₄ layers and found to be 25nm and lOnm respectively. This relatively large variation in the size and mass of the clusters produces a correspondingly large variation in the kinetic energy of the clusters. (The estimated kinetic energies for 15nm-diameter and 35nm-diameter Bi clusters produced with lOOsccm source-inlet Ar flow and with a velocity of 50ms^"1 are approximately 2 x 10⁴⁷ Joules and 3 x 10^"16 Joules respectively). Despite the clusters having a wide range of kinetic energies, the assembly method provides highly selective deposition characteristics. Reflection of the majority of the clusters from the SU8 occurred even for the smallest clusters with the lowest kinetic energy. (Preliminary deposition experiments using Sb clusters (average diameter 25nm and average K.E. 1 x 10^"16 Joules) and Cu clusters (average diameter lOnm and average K.E. 2 x 10^"lδ Joules) have produced cluster-assembled structures with equally selective adhesion to Si₃N₄ and reflection from SU8).

6.5. Contacted 'Bi cluster-assembled wires Figure 38 (a) shows a Bi cluster-assembled interconnect in an SU8 template formed using electron-beam lithography and having a minimum width of όOOnm. and an estimated thickness ranging from 20-60nm. This interconnect extends between two planar Au contacts separated by lOOμm. A linear 1(V) characteristic was recorded for this single cluster-assembled interconnect over the range -6V to +6V (shown in Figure 38(b)). The resistance for the single cluster- assembled wire was 71kΩ, which corresponds to a resistivity approximately 50-times that of the bulk. The main cause for this high resistance is thought to be the granular nature of the wire and to some degree, oxidation of the clusters. Scattering of carriers at grain boundaries increases the resistance of the wire, but we expect these effects to be less significant in shorter wires with few grains and in wires in which an electrical current causes coalescence of neighbouring particles [16]. At V = 7V and I = 105μA this wire irreversibly ceased to conduct. The maximum current density in the wire was estimated to be approximately 10^δ A/cm². FE-SEM inspection of the interconnect after the experiment revealed no obvious breaks.

The 1(V) characteristics of a single Bi cluster-assembled wire (with a minimum width of lμm, length lOOμm and estimated thickness of 50nm) are shown at various temperatures in Figure 39. Upon completion of the deposition process a linear 1(V) characteristic was obtained and the resistance was lOkΩ. A heater and temperature controller were then used to raise the temperature of the sample to 300K, 330K, 370K, 400K, 430K and finally 460K. As shown in Figure 39, the resistance of the interconnect decreased as the temperature of the sample was increased and the resistance at 460K was 5.8kΩ. The wire was then cooled to room temperature, and a final resistance of 6.5KΩ was measured (corresponding to a resistivity approximately 5- times that of the bulk).

The increase in conductance of the wire after annealing is due to increased coalescence of the Bi clusters at elevated temperatures and a permanent change in the morphology and grain size of the wire. This change is clearly seen in Figure 40, where a cluster-assembled wire (deposited under identical conditions) which remained at temperatures below 300K (Figure 40 (a)) is shown next to the cluster-assembled wire which was heated to 460K (Figure 40 (b)). The width of the SU8 template apertures used to produce these wires were 600nm (Figure 40 (a)) and lμm (Figure 40 (b)). The average grain size is clearly larger in Figure 40 (b) than in Figure 40 (a).

Figure 41 shows a Bi cluster-assembled wire that was heated to 620K (approximately 75K above the melting point of bulk Bi) in high-vacuum. The morphology of this wire is clearly different to that of the cluster-assembled wires shown in Figure 38 and Figure 40. The average grain size is much larger than the average diameter of the deposited clusters (25ntn) and facets are clearly visible. The SU8 template layer did not appear to have suffered any degradation after this experiment. At present we cannot measure the electrical properties of cluster-assembled -wires at temperatures above 450K but a sample arm which will enable 1(V) characterization at temperatures up to 700K is currently being constructed. It is anticipated that annealing at temperatures close to, but below, the melting point may produce wires which are less distorted than the wire shown in Figure 41. Further experiments are planned to investigate diis.

Figure 42(a) and Figure 42(b) show respectively an SEM image and an AFM image of a Bi cluster-assembled wire which was produced using an SU8 template layer with a thickness of

50nm. The wire has a minimum width of 300nm (the width of the aperture in the SU8 layer).

This sample was 'over-deposited' ie. the cluster deposition was continued for a much longer period than required to produce a percolating film. AFM inspection of this wire revealed that the average thickness was approximately 300nm (250nm thicker than the SU8 template layer). Bi clusters which are incident upon already-attached Bi clusters have a high probability of adhesion and a cluster film is therefore expected to grow outwards and adopt a 'mushroom' cross-section as it becomes thicker than the template layer. Cluster out-growths which result from this process are seen extending from the wire in Figure 42 (a). This sample does however demonstrate that the SU8 template method can be used to produce high aspect ratio nanostructures.

6.6. Summary of filling ofSU8 trenches with Bi clusters

The method described uses SU8 templated Si substrates and selective adhesion of Bi clusters to form interconnects with minimum widths of 350nm. (Smaller SU8 template-apertures could have been formed with a lower E-beam exposure dose. Our EBL system was operated using an accelerating voltage of 1OkV and the minimum dose achievable at that voltage). The cluster assembly process integrated readily with the optical and electron-beam lithography stages necessary to accurately position electrical contacts on or near the wires. The high-selectivity of the cluster deposition method ensures that conducting wires can be formed while at the same time maintaining electrical isolation from neighbouring wires and devices. Similar results have been achieved using thermally grown Sb clusters and sputtered Cu clusters deposited from IGA sources onto SU8 templated Si₃N₄ substrates. A thermal annealing process has been used to increase the effective grain size and reduce the resistance of a Bi cluster-assembled interconnect.

6.7. Application to interconnect structures in polymeric trenches The formation of trench structures in SU8 or other mechanically robust polymeric materials such as polyamide, polyimide, or PMGI may be useful in the preparation of interconnect structures. One advantage of these materials is that they are patternable in 3 dimensions, thereby allowing different sizes and levels of interconnect structures to be prepared in a small number of lithographic steps, as illustrated schematically in Figure 34. There the polymeric material (3402) is supported on a substrate (3401), patterned and coated with a barrier or seed layer (3404) before being filled with cluster material (3403). In a preferred embodiment the clusters are annealed after deposition into the trenches.

6.8. Application to T-gate transistor structures

The spill-over of clusters from a trench which has been filled with clusters could be used to fabricated a variety of structures, such as the T-gate transistor structures shown schematically in Figure 35 (noting that these diagrams do not show the high aspect ratio of the structures). Here source and drain contacts (3502) and a template for gate (in SU8, but more probably in a material of the appropriate dielectric constant) are fabricated lithographically on substrates (3501) covered in an oxide or insulating barrier layer (3505), and then filled with cluster material (3504) to the desired level. Because the clusters do not adhere to the surface of the template, there are no clusters on the surface until the trench is overfilled. As shown in the lower part of Figure 35, the trench may be a narrower part of a larger trench. In a preferred embodiment the clusters are annealed after deposition into the trenches.

1 S. P. Murarka, Mat. Sci Eng. R19, 87 (1997).

2 H. Haberland et al, J. Vac. Sci Technol. A 12, 2925 (1994)

3 J. J. Wang et al, J. Vac. Sci. Technol. B 23, 3209, (2005).

4 W. A. de Heer, Rev. Mod. Phys. 65, 611 (1993).

5 I. M. Goldby et al, Rev. Sci. Inst. 68, 3327 (1997).

6 R. Reichel, Journal of Nanoparticle Research 8, 405 (2006)..

7 S. A. Brown and J. G. Partridge, 'Templated cluster assembled wires'. New Zealand Patent Application No. 524059. International Patent Application number PCT/NZ2004/00012.

8 S. A. Brown and J. Schmelzer, jr, International Patent Application number PCT/NZ02/00160; NZ Patent Application number 513637, "Nanoscale Electronic Devices and Fabrication Methods".

9 http://en.wikipedia.org/wiki/De_Laval_nozzle Lee K Y, LaBianca N, Rishton S A, Zolghamain S, Gelome J D₅ Shaw J and Chang T H -P

1995/. Vac. Sd <& Tech. B 13 3012 ] Wong W H and Pun E Y B 2001 J Vac. Sd & Tech B 19 732 Feng R and Fams R J 2002 /. Mat. Sd. 37 4793 Shields E A, Williamson F and Leger J R 2003 /. Vac. Set <& Tech. B 21 1453 Quintanilla J, Torquato S, Ziff R M 2000 J. Phys. A 33 L399 Partridge J G, Brown S A, Dunbar A D F₅ Reichel R, Kaufinann M, Siegert C₅ Scott S and Blaikie R J 2004 Nanotechnology 15 1382 Black M R, Padi M, Cronin S B, Lin Y -M, Rabin O, McClure T, Dresselhaus G, Hagelstein P L and Dresselhaus M S 2000 Appl Phys. Lett. 11 4142

Claims

1. A method of depositing particles into a depressed region of a substrate comprising the steps of: a) providing of a substrate having a depressed region in its surface, the depressed region having a depth greater than the width of the depressed region and thereby an aspect ratio greater than 1, and at least one of the dimensions of the depressed region being less than 100 microns, b) providing of a source of particles, and c) directing the particles towards the substrate with kinetic energy sufficient to reduce or minimise adhesion of the particles to at least the sidewalls of the depressed region such that the particles fill at least part of the depth of the depressed region with particles.

2. A method according to claim 1 including directing the particles with velocity greater than 10m/s.

3. A method according to claim 1 including directing the particles with velocity greater than 100m/s.

4. A method according to any one of claims 1 to 3 where the kinetic energy per atom of the particles is less than lOeV/atom.

5. A method according to any one of claims 1 to 3 where the kinetic energy per atom of the particles is less than leV/atom.

6. A method according to any one of claims 1 to 3 where the kinetic energy per atom of the particles is less than O.leV/atom.

7. A method according to any one of claims 1 to 6 including filling a major part of the depth of the depressed region with particles.

8. A method according to any one of claims 1 to 6 including substantially fully filling the depth of the depressed region with particles.

9. A method according to any one of claims 1 to 8 including filling the depressed region generally from the bottom thereof.

10. A method according to any one of claims 1 to 9 wherein at least one of the dimensions of the depressed region is less than 1 micron

11. A method according to any one of claims 1 to 9 wherein at least one of the dimensions of the depressed region is less than lOOnm.

12. A method according to any one of claims 1 to 11 including directing the particles towards the substrate with kinetic energy sufficient to reduce or rninimise adhesion of the particles to the substrate around the depressed region.

13. A method according to any one of claims 1 to 12 wherein the depressed region is a trench.

14. A method according to claim 13 wherein the trench has an aspect ratio greater than 3.

15. A method according to claim 13 wherein the trench has an aspect ratio greater than 10.

16. A method according to any one of claims 13 to 15 wherein the trench has an approximately rectangular vertical cross-section.

17. A mediod according to any one of claims 1 to 16 wherein the particles are atomic clusters.

18. A method according to claim 17 wherein the average diameter of the clusters is between 0.5nm and l,000nm.

19. A method according to claim 17 wherein the average diameter of the clusters is between 0.5nm and lOOnm.

20. A method according to claim 17 wherein the average diameter of the clusters is between 0.5nm and 40nm.

21. A method according to any one of claims 1 to 17 wherein the particles have diameters in the range 1- 50nm.

22. A method according to any one of claims 1 to 17 wherein the particles have diameters smaller than 25 ntn.

23. A method according to any one of claims 1 to 17 wherein the particles have diameters smaller than 15 am.

24. A method according to any one of claims 1 to 23 wherein the particles are atomic clusters and including controlling the velocity of the clusters by the flow rate of an inert gas that is introduced to a cluster source chamber.

25. A method according to claim 24 wherein the velocity of the clusters is controlled by choice of nozzle parameters.

26. A method according to claim 24 wherein the velocity of the clusters is controlled by selection of a de Laval nozzle.

27. A method according to any one of claims 1 to 26 including controlling the velocity of the particles by controlling an accelerating or decelerating potential.

28. A method according to any one of claims 1 to 27 including directing the particles to impact on the sidewalls of the trenches or nanostructures or microstructures at glancing incidence.

29. A method according to any one of claims 1 to 28 including rotating the substrate to a position or angle so as to encourage the bouncing of particles from the surface of the substrate while encouraging the particles to accumulate in the depressed region.

30. A method according to any one of claims 1 to 29 including subsequently removing excess particle material from the substrate.

31. A method according to claim 30 including subsequently removing excess particle material from the substrate by chemical and/or mechanical polishing.

32. A method according to claim 30 including subsequently removing excess particle material from the substrate by wiping.

33. A method according to any one of claims 1 to 32 including overfilling the depressed region with particles so as to form the T-gate of a transistor.

34. A method according to claim 33 wherein the depressed region is disposed between two devices, two electrical contacts, or two regions of the substrate which may be engineered to become devices or contacts, and filling the depressed region with conductive particles to form a current carrying pathway between the devices, contacts or regions of the substrate.

35. A method according to claim 34 wherein the current carrying pathway is an interconnect.

36. A method according to any one of claims 1 to 35 wherein the substrate is a semiconductor.

37. A method according to claim 36 wherein the substrate is silicon.

38. A method according to any one of claims 1 to 37 wherein the substrate, or part of the substrate, is polymeric, or wherein the substrate is coated with a polymeric material.

39. A method according to claim 38 wherein the substrate, part of the substrate, or a substrate coating is SU8, polyamide, polyimide, or PMGI.

40. A method according to any one of claims 33 to 39 wherein the substrate, part of the substrate, or a substrate coating is a dielectric material.

41. A method according to claims 33 to 39 wherein the substrate, part of the substrate, or a substrate coating is a dielectric material with dielectric constant <3.8.

42. A method according to any one of claims 33 to 39 wherein the substrate includes a barrier material or seed layer which covers at least part of the surface of the depressed region.

43. A method according to claim 42 wherein the barrier layer or seed layer covers substantially all the surface of the depressed region.

44. A method according to claim 42 or claim 43 wherein the barrier material or seed layer or a material derived from the seed material causes the particles to wet the surface of the depressed region.

45. A method according to claim 44 wherein the barrier material or seed layer or other material is one which causes the particles to wet the surface of the trench during an annealing stage subsequent to deposition of the particles.

46. A method according to any one of claims 42 to 45 wherein the barrier material is any of TiN, TiSiN, Ta, TaSiN, Hf, HfN, TaN, Ru, RuO₂ and BC_xN_y or the seed layer is any one of Ru,

Cu, or Al.

47. A method according to any one of claims 33 to 46 wherein particles are particles of a material which is highly conductive in bulk form.

48. A method according to claim 47 wherein the particles are Cu or Al clusters.

49. A method according to any one of claims 1 to 48 including annealing the clusters after filling the depressed region.

50. A method according to any one of claims 1 to 48 including annealing the clusters during deposition in the depressed region.

51. A method according to any one of claims 1 to 48 including annealing the clusters after deposition in the depressed region.

52. A method according to any one of claims 49 to 51 including annealing the clusters in hydrogen or other reducing atmosphere.

53. A method according to claim 52 wherein the hydrogen or reducing atmosphere pressure is in the range O.ltorr to 100 torr and the substrate temperature is in the range IOOC to 600C.

54. A method according to claim 52 wherein the hydrogen or reducing atmosphere pressure is in the range 5torr to 50 torr and the substrate temperature is in the range 200C to 500C.

55. A method according to any one of claims 33 to 54 wherein the substrate includes a plurality of depressed regions in its surface.

56. A method according to claim 55 wherein said depressed regions comprise a plurality of trenches in a predetermined order or arrangement.

57. A method according to claim 56 wherein the plurality of trenches form the optical component of a waveplate, polarizer or retarder once filled with particles.

58. A method according to claim 55 wherein the trenches form nanogratings.

59. A method according to claim 58 wherein the nanogratings have a regular period and linewidth.

60. A method according to any one of claims 55 to 59 wherein the substrate is a dielectric.

61. A method according to claim 60 wherein the substrate is SiO₂, or Al₂O₃.

62. A method according to claim 60 "wherein the substrate is transparent.

63. A method according to any one of claims 55 to 59 wherein the substrate is metallic.

64. A method according to claim 63 wherein the substrate is aluminium, copper or silver.

65. A method according to any one of claims 55 to 59 wherein the substrate is a dielectric/metal combination.

66. A method according to any one of claims 55 to 59 wherein the substrate is polymeric.

67. A method according to claim 66 wherein the substrate, part of the substrate, or a substrate coating is SU8, polyamide, polyimide, or PMGI.

68. A method according to any one of claims 55 to 67 wherein the depressed regions are filled with clusters of TiO₂, SiO₂, HfO₂, Ta₂O₅ or Al₂O₃,.

69. A method according to any one of claims 55 to 67 wherein the depressed regions are filled with clusters of Ti, Si, Hf, Ta or Al, or combinations thereof, which are then oxidised.

70. A method according to any one of claims 55 to 69 including subsequent to the particle deposition applying a polymer, glue, or resist to the surface of the substrate.

71. A method according to claim 70 wherein that material encapsulates the particle material in the trenches.

72. A method according to claim 70 or 71 wherein that material is initially liquid and fills any voids between the particles prior to becoming solid.

73. A method according to any one of claims 70 to 72 wherein that material is hardened or ripened by thermal annealing or UV-exposure.

74. A method according to any one of claims 1 to 73 wherein the substrate is at a temperature less than about 230 C.

75. A method according to any one of claims 1 to 73 wherein the substrate is at a temperature less than about 100 C.

76. A method according to any one of claims 1 to 73 including carrying out the method substantially without heating the substrate.

77. A substrate including one or more depressed regions filled with particles prepared according to a method of any one of claims 1 to 76.

78. An integrated circuit including an interconnect prepared according to a method of any one of claims 1 to 76.

79. An optical component including one or more depressed regions filled with particles prepared according to any one of claims 1 to 76.

80. A method of depositing particles into a depressed region of a substrate comprising the steps of: a) providing of a substrate having a depressed region in its surface, the depressed region having a depth greater than the width of the depressed region and thereby an aspect ratio greater than 1, and at least one of die dimensions of the depressed region being less than

100 microns, b) providing of a source of particles, and c) directing the particles towards the substrate with kinetic energy of the particles sufficient to rninimise clogging of the depression or trough from the sides and/ or about the neck or the depression and thereby fill at least a major part of the depth of the depression with particles, from the bottom first.

81. A method according to claim 80 including directing the particles with velocity greater than 10m/s.

82 . A method according to claim 80 including directing the particles with velocity greater than 100m/s.

83 . A method according to any one of claims 80 to 82 including substantially fully filling the depressed region with particles.

84. A method according to any one of claims 80 to 83 wherein at least one of the dimensions of the depressed region is less than lOOnm.

85. A method according to any one of claims 80 to 84 wherein the depressed region is a trench.

86. A method according to claim 85 wherein the trench has an aspect ratio greater than 3.

87. A method according to claim 85 wherein the trench has an aspect ratio greater than 10.

88. A method according to any one of clams 85 to 87 wherein the trench has an approximately rectangular vertical cross-section.

89. A method according to any one of claims 80 to 88 wherein the particles are atomic clusters.