WO2007110839A2

WO2007110839A2 - Method, system, and apparatus for sample rate conversion

Info

Publication number: WO2007110839A2
Application number: PCT/IB2007/051064
Authority: WO
Inventors: Gunnar Wetzker
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2006-03-27
Filing date: 2007-03-27
Publication date: 2007-10-04
Also published as: WO2007110839A3

Abstract

The present invention comprises a method and system of sample rate conversion in an efficient way in case that out-of-band noise is present. The presented method and system can be used for reducing (decimating) as well as increasing (interpolating) the sample rate of a time discrete signal. There, the sample rate conversion is achieved by an appropriate combination of decimation and/of interpolation steps with appropriate decimation and/ or interpolation factors for each of the decimation and/of interpolation step. Further, in the present invention, a signal selective filter is incorporated in a flexible way such that the system can be matched to the properties of the incoming signal. Furthermore, sample rate conversion can be split into a coarse and a fine tuning step.

Description

Method, system, and apparatus for sample rate conversion

The present invention relates to the field of sample rate conversion, especially the fractional sample rate conversion. More particularly, the present invention relates to a method, a system, a computer program product, and a device enabling the sample rate conversion of a signal. Sample rate conversion is the process of converting a signal from one sampling rate to another, while changing the information carried by the signal as little as possible. The conversion of sample rate is required when processing signals of a system using a first sampling rate in a system, which uses a second sampling rate. For example a compact disc uses 44.1 kHz, digital audiotape uses 48 kHz and satellite broadcasting uses 32 kHz.

Generally, the principles of sample rate conversion are well known and studied. With the broadness of the possibilities of the use of the sample rate conversion flexible methods and systems of converting a signal from one sampling rate to another are required. Today, an important field of application of the sample rate conversion is represented by wireless transceivers. Combining multi-mode operation e.g. of GSM (Global System for Mobile Communications), UMTS (Universal Mobile Telecommunications System), Bluetooth, FM (Frequency Modulation) radio, or WLAN (Wireless Local Area Network) signals in one device requires flexibility with regard to the sample rate conversion as well as the channel filtering or signal selective filtering respectively.

However, the flexibility of a sample rate conversion method or system increases the complexity and costs of the corresponding method or system. Further, complexity and costs increase also if out-of-band noise is present and in the case that the processed signal is dependent on the mode of operation of a system. Availability of solutions on area and power efficient methods and systems being able to accommodate high bandwidth as well as low bandwidth signals is limited. The straightforward approach to achieve a flexible sample rate conversion is the implementation e.g. in a decimation filter, of a fully flexible signal selective filter. In the transceiver design the signal selective filter is also called channel selective filter or impulse shaping filter. This filter is typically the last and largest filter in the rate conversion processing chain. However, although sample rate conversion after the signal selective (channel) filter is simple, there is still an important disadvantage - the flexibility at this point in the chain is area and power expensive.

It is an object of the present invention to provide a method and a system, which allow flexible and efficient good quality sample rate conversion. Further, an object of the present invention is to provide an efficient good quality sample rate conversion with a presence of out-of-band noise.

The above objects are achieved by a method as claimed in claim 1 and by a system as claimed in claim 21. The above characterized objects of the present invention are further achieved by a computer program product comprising code means for performing the steps of any one of method claims 1 to 19 when run on computer controlled device and by a device for sample rate conversion in a system according to claim 21.

According to the present invention, a fractional sample rate conversion is achieved in an efficient way in case that out-of-band noise is present. The method and system according to the presented invention can be used for reducing (decimating) as well as increasing (interpolating) the sample rate of a time discrete signal. There, the sample rate conversion is achieved by an appropriate combination of decimation and/of interpolation steps with appropriate decimation and/ or interpolation factors for each of the decimation and/of interpolation steps. Further, a signal selective filter is incorporated in a flexible way such that the system providing the methodology of the present invention can be matched to the properties of the incoming signal. Further, sample rate conversion is split into a coarse and a fine-tuning step.

The above-mentioned method and system provide a decimation and/or interpolation step allowing a rate conversion with a first factor is combined with a changeable number of steps, which allow rate changes with a further factor. According to the present invention the steps of decimation and/or interpolation may comprise sub steps of decimation and/or interpolation. Thus, a cascade like implementation of the corresponding decimation and/or interpolation steps may be enabled by the present invention. For the reasons of clarity, the decimation and/or interpolation steps comprising sub steps of decimation and/or interpolation will also be referred to as stages. Further, the implementation of the decimation and/or interpolation factors can be handled very flexible. Thus, according to one preferred embodiment of the present invention, the first factor may be a factor between one or two and the further factor used by the further stages could be a factor of two. Further, corresponding to the possible values of the decimation and/or interpolation factors, also the opposite case is possible: first a couple of decimate and/or interpolate by two stages, followed by a between 1 and 2 decimation and/or interpolation stage, which can be again followed by further decimate and/or interpolate by two stages. Each of these examples allows to implement any wanted decimation and/or interpolation factor. If the decimate/interpolate between 1 and 2 is implemented in a flexible way and the decimate/interpolate by two stages can be bypassed (switched on or off), the maximum decimation and/or interpolation factor can be given by 2^β+1 , where Q denotes the number of decimate/interpolate by two stages (or steps comprising sub steps). The lowest decimation and/or interpolation factor can be given by 1. This feature provides the advantage, that any conversion factor can be realized during the sample rate conversion. A further important property of this rate change stage is that it can operate in the presence of out-of-band noise. However, according to the present invention the possible values of the decimation and/or interpolation factors are not restricted to the above- mentioned possible upper and lower bounds ( 2^β+1 and 1 respectively).

The flexibility required in the signal selective filter can be reduced as much as possible without adding too much additional area to this filter. Further, the present invention emphasizes a large degree of flexibility with regard to matching of common transceiver signals and permission of any sample rate conversion. A multi-mode operation requires a decimation process or filter, which preferably enables (fractional) decimation as well as flexible channel filtering or signal selective filtering due to differences in bandwidth and shape of the different signaling modes. Experience in signal processing shows that a root-raised cosine filter is one of the best candidates fitting the requirements of the step of channel filtering for signals modulated by Quadrature Amplitude Modulation (QAM), Gaussian Frequency Shift Keying (GFSK), and/or Orthogonal Frequency Division Multiplex (OFDM). In the present invention, flexibility in the channel filtering or signal selective filtering step can be reduced to adaptability of the roll-off factor relating to attenuation of frequencies, above or below a given point, at a specific rate if decimation step is performed before the channel filtering or signal selective filtering step.

The performance of the step of fractional decimation before the step of channel filtering or signal selective filtering allows adjusting the over-sample factor at the input of the channel filter to a fixed value independent of the ratio between signal bandwidth and clocking frequency. The clocking frequency could for example denote the clock frequency at the input of the system. Further, the fractional decimation can be enabled before the channel filtering (signal selective filtering) at reasonable additional overhead. Thus, it becomes possible to cope with out-of-band noise and sample-rate adaptation at the same instant.

In the present invention, the channel filtering / signal selective filtering, which can be tuned to the shape of the signal processed, operating at a fixed over-sampling factor (for example sample-rate/signal-bandwidth) enables flexibility by adding minimum hardware. Further, sample rate adaptation at the output of the step of channel filtering / signal selective filtering is much simpler since the channel filter removes out-of-band noise. The drawback of such an approach is that the channel filter has to be flexible in all respects. As mentioned above, the channel filter is the largest filter in the filtering chain making it the least attractive one to be made flexible. In the present invention, the flexibility of this filter is reduced to the adaptability of the roll- off factor.

The method and/or the system proposed here adapt the sample rate before channel filtering / signal selective filtering in such a way that the match between sampling rate and filter bandwidth leads to tolerable losses. An accurate sample rate adaptation with accuracy in the order of the reference clock is proposed after channel filtering. Therewith, the sample rate adaptation is split into a coarse and a fine-tuning before and after the channel filtering / signal selective filtering respectively. Thus, the fractional decimation complexity can be reduced before channel filtering / signal selective filtering and providing a clear reduction of the power consumption required for the sample rate conversion.

There, also the accuracy of the sample rate conversion can be split in two stages. In the first stage, conversion takes place in a coarse way in the presence of out-of- band noise such that the signal can be processed without major performance drawbacks by the channel filter / signal selective filter. In the second stage, fine sample rate conversion takes place after removal of out-of-band noise by the channel filter / signal selective filter. Further developments of the invention are defined in the dependent claims.

The present invention will now be described in more detail based on preferred embodiments with reference to the attached drawings, in which:

Fig. 1 shows a concept of sample rate conversion in accordance with an embodiment of the present invention;

Fig. 2 shows a block diagram of fractional decimation stage in accordance with an embodiment of the present invention; Fig. 3 shows an example for the output signal calculation of the first decimation stage in accordance with an embodiment of the present invention;

Fig. 4 shows an example of working of a modulo accumulator in accordance with an embodiment of the present invention;

Fig. 5 shows a further example of working of a modulo accumulator in accordance with an embodiment of the present invention;

Fig. 6 shows a block diagram of a modulo accumulator in accordance with an embodiment of the present invention;

Fig. 7 shows an example of working of a modulo accumulator where the triangular impulse response of the first decimation filter of the fractional decimation stage is included in accordance with an embodiment of the present invention;

Fig. 8 shows a block diagram of arithmetic operations in accordance with an embodiment of the present invention;

Fig. 9 shows a block diagram of a possible output buffering added to arithmetic calculations in accordance with an embodiment of the present invention; Fig. 10 shows a block diagram of a second accumulator for a control signal generation in accordance with an embodiment of the present invention;

Fig. 11 shows a table with values required to feed the second decimation stage in accordance with an embodiment of the present invention;

Fig. 12 shows a block diagram of simulink model implementing logic functions required to feed the second decimation stage in accordance with an embodiment of the present invention; Fig. 13 shows a block diagram of a simulink model of the complete fractional decimation stage including the second decimation stage in accordance with an embodiment of the present invention;

Fig. 14 shows an example of a possible worst case in accordance with an embodiment of the present invention, when the decimation factor of the fractional decimation stage is close to 2;

Fig. 15 shows the worst-case suppression on linear and logarithmic scale in accordance with an embodiment of the present invention;

Fig. 16 shows the distortion at the edge of the passband of a desired signal in dependence of the over sampling factor at the output of the triangular filter in accordance with an embodiment of the present invention;

Fig. 17 shows a block diagram of a fractional decimation stage with enhanced image suppression in accordance with an embodiment of the present invention;

Fig. 18 shows the impulse responses of root raised cosine filters for different roll off factors designed for an over sampling of eight in accordance with an embodiment of the present invention;

Fig. 19 shows an estimated impulse response and transfer function for a roll- off factor of 0.75 in accordance with an embodiment of the present invention;

Fig. 20 shows an estimated impulse response and transfer function for a roll- off factor of 0.25 in accordance with an embodiment of the present invention;

Fig. 21 shows a block diagram of a structure of a transposed filter;

Fig. 22 shows a block diagram of a tunable root-raised cosine filter in accordance with an embodiment of the present invention;

Fig. 23 shows a block diagram of signal generation for re-clocking in accordance with an embodiment of the present invention; and

Fig. 24 shows a block diagram of re-clocking in accordance with an embodiment of the present invention.

The embodiment of the present invention demonstrated in Fig. 1 shows a concept of sample rate conversion, a step of combination of two stages of decimation or a cascade of decimation respectively. The corresponding decimation stages consist of several steps or filters; there are half-band filters (HBF) and decimation filters (DF) used. The first stage consists of half-band filters (HBF) and allows rate changes of a power of two. According to the present invention, this first stage can be combined with a changeable number of stages. The cascade of the half-band filters (HBF) is followed by a stage allowing to decimate between a factor of 1 and 2 such that the full chain can achieve any conversion factor between one and 2^β+1 , where Q is the number of decimate by two stages realized by the half-band filters (HBF). Thus, sample rate conversion can be realized in the presence of the out-of-band noise. In the present embodiment, every decimation stage allowing rate change by two can be bypassed. Recapitulating, if Q is the number of stages allowing rate change by two, any decimation factor with value between 1 and 2^β+1 can be realized in the present embodiment. However, according to the present invention the possible values of the decimation and/or interpolation factors are not restricted to the above-mentioned possible upper and lower bounds ( 2^β+1 and 1 respectively).

Multi-mode operation of sample rate conversion requires a decimation filter, which preferably enables fractional decimation as well as flexible signal selecting filtering or channel filtering due to differences in bandwidth and shape of the different signaling modes. Experience shows that a root-raised cosine filter fits the channel filter requirements for QAM, GFSK, and OFDM modulated signals. Flexibility in the signal selecting filtering or channel filtering can be reduced to adaptability of the roll-off factor if fractional decimation is possible before the signal selecting filter or channel filter. A fractional decimation step before signal selecting filtering or channel filtering allows adjusting the over-sample factor at the input of the signal selecting filter or channel filter to a fixed value independent of the ratio between signal bandwidth and clocking frequency. In the present embodiment, the decimation cascade includes a stage of fractional decimation (FDS) before the channel filter (TCF or tunable channel filter) at reasonable additional overhead. The challenge of such a solution is to cope with out-of-band noise and sample-rate adaptation at the same instant.

The second or the flexible decimation stage is located in the present embodiment at the lowest possible sampling frequency before the step performing the tunable channel filter (TCF). There, we would like to point out that the placement of the flexible stage is not restricted to the location directly before the channel filter solely. According to the present invention, the flexible stage can also be located earlier in the chain and be followed by a number of further decimate by two stages. The over sampling factor determines the performance of the fractional decimation step with the consequence that the fractional decimation step preferably can be operated at higher sampling frequencies than the channel filter.

In the present embodiment, the signal selecting filtering or channel filter respectively can be tuned to the shape of the signal processed and is flexible with regard to the roll-off factor. There, the fractional decimation stage can be configured in a way that the over sampling factor (e.g. over sampling factor = sample rate / symbol rate) is constant for any processed mode. Thus, the present invention enables flexibility also by adding minimum hardware.

The present invention provides a great flexibility regarding the implementation of the method of sample rate conversion. The present embodiment shows just one way of realization. Thus, it is possible to implement the combination of the initial decimation by two stages in to one filter. Furthermore, because of the fact that the first decimation filtering steps are the smallest ones, a reduction of costs can be achieved by carrying out at least some of them in a parallel way, additionally said first parallel performed decimation filtering steps could also run with different decimation factors.

Fig. 2 shows a block diagram of the fractional decimation stage and explains the underlying principle of this stage. In the present embodiment, an up sampling stage and two down sampling stages are provided. The decimation stages are fixed. The first decimation stage is implemented by use of a triangular filter (TF) and is decimated by a factor of K₀ , the second decimation stage is implemented by use of a half-band filter (HBF) and is decimated by a factor of 2 . The interpolation stage which is interpolated by a factor of L is flexible. In the present embodiment, the value of L varies from K₀ + 1 to 2,ST₀ - 1 . The overall decimation factor in the present embodiment is given by 2,ST₀ / L . Thus, decimation factors from 2,ST₀ /(2,ST₀ - 1) « 1 to 2,ST₀ /(K₀ + 1) « 2 can be covered during the sample rate conversion. The amount of possible decimation factors equals K₀ - I . The worst-case difference between a given decimation factor and what can be accomplished by a corresponding sub system is given by 1/2,ST₀ .

Further, the first decimation filter (TF) of the fractional decimation stage of the present embodiment is fixed to a triangular impulse response. By choosing a triangular impulse response of length 2,ST₀ - 1 with the impulse response

{l 2 3 ... K₀ ... 3 2 l} for the first decimation filter (TF) in combination with the second decimation stage (HBF) decimated by the factor of two it is possible to provide an area and power efficient implementation. Further, in the present embodiment the second decimation stage uses polyphases, where the number of the polyphases is given by the corresponding decimation factor of the second stage.

For a better understanding of a possible implementation of the fractional decimation stage, examples detailing the operation to be carried out will be given in the following.

First, the case L = 5 and K₀ = 4 is considered. The input signal to be treated is denoted by x_k .

Fig. 3 shows an example for the calculation of the output signal x_k of the first decimation stage in accordance with an embodiment of the present invention. The input signal x_k is sampled up by factor L . Fig. 3 shows also the instants (the arrow labeled with t refers to the time) during the calculation of output samples. Per incoming sample one or two output samples are calculated. E.g. on the clock of the input sample X₁ , an output sample OUt₁ is generated. At the arrival of the input sample x₃ , output samples out ₃ and out₄ have to be calculated. Consequently, per incoming input sample at maximum one output sample of the second decimation stage with factor of two is produced and the whole fractional decimation stage can work on the clock of the incoming signal with one input and one output signal. Additionally, an enable or clock signal is required at the output of the fractional decimation stage since not every incoming sample has to lead to an output sample. To track the amount of signals to be generated, a modulo K₀ accumulator can be used. Fig. 4 shows an example of working of a modulo accumulator in accordance with above example. With every incoming sample, the accumulator value accu_k is incremented by L . The value of output samples to be generated within a period of the incoming samples results from the operation floor((accu_k__l + L)I K₀ ). Afterwards the operation accu_k = mod(accu_k__l + L, K₀ ) is carried out.

When the accumulator content equals K₀ or 2,ST₀ as marked by the rectangles in the Fig. 4, output sample instants coincide with the virtual instants. Due to the fact that the value range of L is limited, at maximum two output samples can be generated per input sample. Fig. 5 shows a further example of working of a modulo accumulator. There the following values of parameters are regarded: L = I and K₀ = 4. Further, Fig. 6 shows a block diagram of the modulo accumulator according to the present invention and according to the examples described in detail above.

Fig. 7 shows an example of working of a modulo accumulator where the triangular impulse response of the first decimation filter of the fractional decimation stage (presented in Fig. 2) is included. There, Fig. 7 redraws Fig. 6 and additionally takes in the triangular impulse response of the first decimation filter of the fractional decimation stage described above. Black dots in the impulse response indicate filter coefficients, where a multiplication of a filter coefficient with an incoming sample is required. Further, Fig. 7 points out that the required coefficients of the filter impulse response seem to have a relation with the content of the modulo accumulator. This fact can be concluded also from the inspection that in the case that only one output sample has to be generated two multiplications are required and in the case that two output samples are required only one multiplication per output sample is necessary.

There, the case concerning out₃ of Fig. 5 gave the first conclusion that one output signal could require two multiplications. Considering the example given by Fig. 7, one multiplication ( X₃ • 1 ) seems to be required. To find a general rule the following can be rewritten x₂ ■ 0 + X₁ • 1. In summary, three different computations can be distinguished according to the present invention: x_k ^■ accu_k x_k ^■ (K₀ - accu_k ) x_k ^■ accu_k + x_k ^■ [K₀ - accu_k )

Further, according to the present invention it is also possible to carry out the above-described operations with one multiplication per incoming signal. The corresponding example is provided by the block diagram represented in Fig. 8. The number of output samples at the output of the first decimation filter, which has to be generated per input sample, varies between one and two. As a consequence, per input sample one or none output sample has to be generated at the output of the second stage decimated by factor of two. Accordingly, at the output of the second decimation stage an enable signal is produced, which can be used as a clock signal for the following stages. Further, the probability is given that an output sample has to be stored at the output of the first decimation stage before a further output signal of the second decimation stage can be calculated when the next input sample arrives. The decision, which intermediate value has to be stored depends on the parameter settings and the value of the accumulator.

A straightforward approach for decision which samples could feed to the second decimation stage could be the storage of all relevant signals and an appropriate selection based on few control signals. Further, regarding the Fig. 7 the assumption can be met, that it is not necessary to store the signal s_{2 1} . Summarizing the idea, Fig. 9 shows a block diagram of a possible output buffering added to arithmetic calculations in accordance with the above regarded examples.

Regarding the generation of an enable signal, a control signal indicating whether a sample is buffered or not is required. For this reason, a number of samples n_{s k} generated at the output of the first decimation filter and coming from the system depicted for example in Fig. 6 can be aggregated in a second modulo accumulator. Fig. 10 shows a block diagram of a second accumulator for the control signal generation.

Further, if two samples are generated in a cycle, the enable signal has been high. If one sample is generated it depends whether another sample is buffered or not. Thus, the signal a_k can have the values 1, 2, or 3. In the case, if a_k have the value 2 or 3, the LUT has to provide a 1 at the output. Otherwise, in the case if a_k equals 1, the LUT has to provide a 0 at the output. The signal n_{b k} indicates whether a sample is stored at the end of a cycle of one incoming sample x_k or not. Altogether, according to the present invention, five cases regarding the selection of samples which are fed to the second decimation stage in case that the enable signal is high can be distinguished: ⁿs,k = !' ⁿb,k-i = !' ⁿs,k-i = 1 => enable^ = 0, n_{b k} = 0 ⁿ.a = 1» ⁿb,k-i = ^!' ^w _*,*-i = ² => enable^ = 1, n_{b k} = 0 n_sJc = 2, /Z₆^₁ = 0, n_sJc_, = X => enable_k__x = 1, n_hχ = 0 ⁿ.a = ²> ⁿb,k-i = ^!' ^w _*,*-i = ^l => enable^, = 0, n_{b k} = 1 ⁿs,k = ²' ⁿb,k-i = !' ⁿs,k-i = ² => enable^ = 1, n_{b k} = 1 The information coming from the cycle k - 1 is required to determine, which buffered value has to be read. As discussed above, the calculations required to derive the output samples of the first decimation stage depend on the number of samples (one or two) to be generated in a cycle. Instead of use of n_{s k}__x also the use of enable_k4 is possible.

Further, for the differentiation of the above-characterized five cases regarding the selection of samples at least three signals are required. Buffering can be avoided when the actual samples are preferred to the above previous samples. The Fig. 11 shows a table including the resulting logic for the case if the signals n_{s k} , n_{b k} , and enable_{k l} are used and required to feed the second decimation stage according to the present embodiment. In Fig. 11 the reference C denotes the number of the corresponding case. There, also other selections are possible. In the table represented in the Fig. 11, the signal n_{s k} is converted from the value set { 1,2} to {0,1 }. For the third case, the enable signal can be set equal to "don't care" since this case can be distinguished from the other cases by the first two signals. Further, P_{0 k} and

P_{1 k} denote the input signals for the polyphase components of the second decimation stage. The samples s_x refer to Fig. 9.

Furthermore, by inspecting the table represented in the Fig. 11, it is possible to derive the conditions under which a signal has to be directed to one of the polyphase components:

S_{1 e} : IF enable_k4 = 0 AND n_{s k} = n_{b k}

' 2 1 IF « s„,k ,, ≠ n ^ub k

b k

S₁ : IF n s,k — ⁿb k = 0

S_{1 1} : IF n s,k ≠ ⁿb k

IF n s,k ⁿb k = 1 Fig. 12 shows a block diagram of simulink model implementing above logic functions required to feed the second decimation stage and the multiplexing of the calculated and buffered samples to the polyphase components.

A simulink model of the complete fractional decimation stage including the second decimation stage is shown in Fig. 13. The filter impulse response implemented for the second decimation stage has a three taps impulse response with a triangular impulse shape. Further, the model can be extended with a longer impulse response and another shape.

Further, the performance of the fractional decimator is dependent on the first decimation stage. The second decimation stage is fixed in the present embodiment and therefore allows design and implementation of an impulse response fitting the requirements set out. According to the present embodiment, a triangular impulse response is used in order to keep the first decimation stage simple. Further, this triangular impulse response determines how much energy of the image bands folds back into the desired band if the signal is decimated by K₀ . According to the present embodiment, the bandwidth of images can be determined by the over sampling factor ov at the output of the triangular filter. The over sampling factor in turn can be calculated by the division of the sampling rate by the signal bandwidth. When regarding some assumed worst-case conditions, when the decimation factor of the fractional decimation stage is close to 2, this factor is almost equal to the over- sampling factor at the input. In this case, the first image undergoes the least suppression due to the shape of the transfer function of the triangular filter impulse response. Fig. 14 shows an example of a possible worst case according to the present embodiment, when the decimation factor of the fractional decimation stage is close to 2. There, the over sampling factor ov = 4 and K₀ = 16 . Further, according to the present embodiment, the normalized bandwidth of an image equals to 1 /{ov K₀ ). The location of the first image can be given by I/ K₀ . Consequently, the worst-case frequency in the first image band with the lowest attenuation can be given by 1/ K₀ — \l(pv ■ K₀ ) . At the attenuation the following can be derived by:

Fig. 15 shows the minimum attenuation in dependence of the over sampling factor at the output of the triangular filter according to the present embodiment. There the worst-case suppression on linear and logarithmic scale is provided, wherein K₀ = 128

Further, according to the present embodiment, the distorting of the base band of the desired signal is maximal at 1 /(2 • ov ^■ K₀ ) and can be given by:

Fig. 16 provides the distortion at the edge of the passband of the desired signal in dependence of the over sampling factor at the output of the triangular filter according to the present embodiment, wherein K₀ = 128 . Summarizing the present embodiment regarding the fractional decimation stage, it can be stated that the distorting of the passband will be negligible for most systems of interest. For the attenuation of the image it follows that relatively high over sampling factors at the output of the triangular filter are required to guarantee sufficient image suppression. A few remarks on this shall be made. The studied worst case only holds for two frequencies. A bit of distortion from these frequencies will be tolerable in most cases. Closer to the image center, the suppression for the worst-case images is much higher.

Preceding decimation stages already remove part of the noise of an over- sampled ADC over the whole band even if comb filters are applied. This relieves the specification for the fractional decimation stage.

The alias suppression can be increased by about 12 dB by doubling the over- sampling factor at the output of the triangular filter. This has several consequences: L varies from 2K₀ to AK₀

A decimate by four in place of a decimate by two second stage is required, which causes significantly more overhead.

The control logic changes. In place of generating one or two samples per input sample at the output of the triangular filter, two to four output samples per input sample have to be generated. The complexity of the arithmetic operations is slightly reduced (one of the three operations is no longer required). The complexity of buffering the signals and controlling the decimation increases.

The resulting fractional decimation stage with enhanced image suppression, where a triangular filter (TF) and a comb filter (CF) are employed, is shown in Figure 17.

Considering a multi-mode system, which makes use of a sigma delta modulator for analogue to digital conversion running at a fixed frequency of about 430 MHz: For a wireless LAN system with 16 MHz bandwidth, this equals an over-sampling factor of about 27. A wireless LAN system typically requires 9 to 10 bit resolution at the receiver, thus about 60 dB dynamic range. The worst-case image suppression should therefore be 60 dB.

Typically, the quantisation noise of a sigma-delta modulator only amounts up to 0 dB at specific locations, which are at half or a quarter of the sampling frequencies. It has to be noted that such effects depend on the input signals e.g. with or without direct current and the design itself. If these frequencies are suppressed by a first comb filter eventually combined with a decimation stage decimated by a factor of 2 or 4, the specification of the required suppression might be reduced to 50 dB. A decimation stage decimated by a factor of two in combination with a comb filter suppressing also frequencies at /_s /4 (!) would lead to a worst case over- sampling factor at the triangular filter output of 27/2, which still guarantees more than 55 dB image attenuation.

On the other extreme are GSM signals with about 200 kHz of bandwidth.

Decimating before the fractional decimation stage by at least a factor of 8 still leaves more than 100 dB worst-case image suppression. Fortunately, the system is that simple that it can also operate at high clock speeds. In case that the fractional decimation factor is set to a value close to 2, the overhead of the whole system is given by the first decimation stage in the fractional decimation part. In case the decimation factor approaches one, the whole fractional decimation stage is overhead.

Decimation factors close to two are therewith preferred. It has to be noted that the performance of the system in terms of image suppression depends on the decimation factor. For low fractional factors, the worst case can be improved by at maximum 12 dB, because the over- sample ratio at the output of the triangular filter gets at maximum a factor 2 higher.

The fractional decimation stage as presented here runs completely on the incoming clock. Since not every input sample leads to the production of an output sample, a different clock signal is needed at the output of the system. Two possibilities exist:

1. Use the clock signal of the incoming signal together with the enable signal. This leads to the usage of flip-flops having an enable port. These flip-flops are in general significantly larger than flip-flops having no enable port. The advantage is that the processing of such a system with standard tools is straightforward.

2. Use the enable signal as a clock signal for all further flip-flops. The enable signal has a non-constant duty cycle. Furthermore, it is generated inside the system and typically synthesis tools have problems with this situation. The enable signal has to be assigned to an output port and an additional input port has to be included for the new clock signal. In the end, this input port has to be connected to the output port of the enable.

Given a fractional decimator, it is possible to change the sample rate of an incoming such that the ratio between sample rate and the symbol rate equals a given value, e.g. eight. The accuracy of this processing step depends on how large K₀ is.

For ^T₀ = 128 , the match is within a percent and for ^T₀ = 1024 within a pro mille. This is accurate enough to reduce performance loss of the filter to tolerable limits. Further increase of K₀ is possible but increases namely the bit width of the multiplier required for the arithmetic computations. Fig. 18 shows the impulse responses of root raised cosine filters for different roll off factors designed for an over sampling of eight ( ov = 8 ). Each impulse response is cut after the first sidelobe. In the extreme case for the lowest possible roll-off, the response spans

4 symbol periods (or 31 taps/coefficients).

It follows that the different impulse responses look very different. Given today's systems, the root-raised cosine filter has been demonstrated to be a reasonable channel filter for systems such as Bluetooth, DVB-S and WLAN. It should also be possible to cover GSM, DECT and FM radio as well as CDMA signals.

For multi-carrier systems using OFDM, a root-raised cosine filter can be used to filter the whole band and to suppress adjacent channel signals. The filtering per sub-carrier happens within the FFT operation, which is required to demodulate the signal.

Using the impulse responses given in Figure 18, it is possible to construct by simple means of interpolation other impulse responses with different roll off factors. E.g. by adding up the impulse response for a roll off of 0.5 hrrc, 0.5(k) to the one of a roll off of 1.0 hrrc,1.0(k) and dividing through 2. The result is an estimate of the response with a roll off of 0.75:

Krcfi 75 = -(Krcfi 5 W + Kc,l 0 (*θ)

2

Since the two impulse responses, which are used to calculate the estimate, have different lengths, the result has to be truncated differently. Fig. 19 shows the result in time and frequency plots demonstrating that the main lobes are well approximated and the out-of-band suppression of the approximation is even stronger. Fig. 20 shows the result for a similar operation but now for a roll off of 0.25 leading to similar results. Which impulse responses to use to obtain later the interpolated ones depends on the range of roll off factors to be covered. The most flexible solution is achieved in case that the full range from 0 to 1 is covered and the results above suggest that this is possible with at least three stored impulse responses. Given the considerations above, an efficient implementation is required to keep the overhead of a tunable filter low. According to the present invention, the following implementation can be given. As a starting point, a transposed filter structure as depicted in Fig. 21 is used. To simplify the explanation, it is assumed that only two impulse responses are used for interpolation. Extrapolation to three or even more ones is straightforward. The two impulse responses are denoted by Zz₁(^) and h₂(k) and they are e.g. impulse responses of root raised cosine filters with roll offs 0.25 and 0.75 respectively. The interpolation operation is given by: h_mt {k) = a - h_l{k)+ (l - a) - h₂ (k) , where a denotes the interpolation factor. In this example, a = 0.5 leads to the estimate of the impulse response with a roll off of 0.5.

Defining the difference impulse response: h_A{k) = h_l{k)- h₂{k) it is possible to write:

. This last equation provides two advantages:

1. Only one multiplication by a has to be implemented; and

2. Difference impulse responses like h_A (k) typically have small coefficients requiring fewer adders for implementation.

Fig. 22 shows a block diagram of the resulting tunable root-raised cosine filter according to the above described and developed embodiment. There, a group of the first and the last coefficients has to be switch able and some additional logic having as an input the interpolation factor is required to steer these switches.

The proposed tunable root-raised cosine filter according to the present embodiment allows fitting the roll-off factor to the properties of the received signal without the necessity to implement a fully flexible filter including a memory of all the required impulse responses. Compared to a flexible filter, dedicated coefficient multiplications can be implemented allowing to optimize the computations and to reuse sub-expressions. Compared to a fixed root-raised cosine filter, additional difference filters have to be implemented. Difference filters typically have small coefficients reducing the required amount of adders. The provided embodiment allows implementing a filter, which can be tuned to any roll-off factor by making use of two difference filters. The given transfer functions suggest that the achieved accuracy is good enough for current systems of interest. Adding more difference functions or reducing the span of the roll-off factor can improve the accuracy of the interpolation. Adding the second side lobe of the root-raised cosine filter is also possible.

Typically, this causes overhead, which is not in relation with the performance improvements. For lower order modulation schemes in single carrier systems, sticking to one side lobe is enough especially in the context of non-perfect synchronization schemes.

In Fig. 1 a fine-tuning step is drawn after the fractional decimation stage (FDS) and the tunable channel-filtering step (TCF). The fine-tuning step allows getting the sample rate accuracy in the order of magnitude of the clock reference. In principle, this is also possible in the fractional decimation stage. The advantage of doing it at a later stage is to lower the complexity of the fractional decimation stage such that the sample rate adaptation is just sufficient to avoid significant performance distortion in the channel filter. The proposed fine-tuning of the present invention is based on the concept of skipping a sample once in a while. This requires that the incoming sample rate is always higher than the outgoing. This can be achieved by setting the decimation factor in the fractional decimation stage accordingly. After the signal selecting filtering or channel filtering respectively such an operation is possible, because all out-of-band noise has been removed and can no longer fold back.

To decide when to pass and when to skip a sample, it is required to accumulate the incoming samples. If f_m is the sample frequency of the incoming signals, the phase advance in one clock interval is given by 1 / f_m . If f_out is the outgoing sampling frequency, which is always lower compared to the incoming one, a sample has to be passed if the content of the accumulator exceeds 1 / f_out . After exceeding 1 / f_out , the accumulator content has to be reduced by 1/ f_out , which can be achieved by a module 1/ f_out operation. Next to the decision, whether a sample has to be passed or not, it can be decided if it is more accurate to skip the current or the coming sample. This decision can be taken on the outcome of the modulo operation. An early signal can be generated indicating if the early or the late signal has to be taken.

Typically, the phase values above are fractional numbers. In a digital system they have to be converted into integer values. If phase bits equals the number of bits to represent the phase information the integer phases follows from:

phase_mt = and

phase_ref = round 9 phase_tlB

The multiplication by f_norm is used to get the phase values dimension free. It also can be used to get the product of the frequencies close to one, such that phase_blts represents the resulting number of bits of the integer phase values.

Fig. 23 shows a block diagram of signal generation for re-clocking according to the present invention and depicts, how phase_mt and p_ref are used to generate the early signal and an enable signal indicating if a valid signal is produced by the system or not. This enable is very similar to the enable signal, which is produced by the fractional stage and can be used as the clock signal for the following stages.

To explain the functioning in a bit more details, an example is considered. It is e.g. assumed that the value 2003250 equals phase_mt . This value corresponds to the time duration (phase shift) of one clock cycle of the incoming samples. The value p_ref for the outgoing samples is given by 2796203.

After the first clock cycle, the modulo operation has no effect since the accumulated value is smaller than phase _ref . Therefore, the enable signal is low. In the second cycle, the accumulator equals 4006500. Now the enable signal is high and 4006500-2796203 = 1210297 is calculated by the modulo operation. Since 1210297 is smaller than 2003250/2, the early signal is low. This signal indicates if the latest (early = 0) or the previous input sample (early = 1) should be taken.

The early signal is required to ensure that the sample closest to the clock tick of the outgoing clock is taken.

Fig. 24 illustrates a similar re-clocking example drawing the various signals. The arrows under the incoming samples indicate the accumulator operation. Arrows pointing from the left two the right represent the phase advance of the incoming clock. Arrows pointing from the right to the left indicate the phase value of the outgoing clock. The thick arrows are the residual values of the accumulator after the modulo operation.

The performance of the proposed method depends on two error mechanisms. The first one follows from the fact that f_m and f_out rising edges almost never occur at the same instance. Thus the sample taken as a f_out sample occurs in time a bit earlier or later.

This error is indicated in Figure 24.

This error can be treated as jitter and causes a signal-to-noise degradation. The maximum distance in time, a f_out clock tick can have with regard to the fin clock tick, is given by half of the period of the fin clock period, thus 1/(2 • f_m ) . As a consequence, the amount of distortion caused depends on the over sampling factor of the incoming signal.

A second type of error that occurs is frequency deviation. It results from the fact that the phase of f_m has to be tracked. Since the precision of the phase reference value phase _ref is finite, accumulating the phase shifts causes an error, which can be translated into a frequency error. The resulting frequency error in ppm should be smaller than what can be expected from the reference in a system. A typical value is 20 ppm.

The resulting frequency error can be calculated. The frequency error f _erτor in ppm follows from:

J error

[ppm] . f_m The reviewed re-clocking system allows to fine tune the sample rate after the signal selecting filtering or channel filtering respectively. The method and the system according to the present invention cause very little overhead. The simplicity of the method / system is caused by the circumstance that out-of-band noise is removed after the signal selecting filtering or channel filtering operation. On the other hand it has to be noted that too low over sampling factors can lead to significant signal distortion. An over sampling factor of four at the input of the system can be regarded as a minimum value. For every conversion mode, two phase values have to be stored. Since the word lengths of these values determine the re-timing accuracy of the system, word lengths in the order of 20 are to be expected. It is noted that the present invention is not restricted to any specific embodiment, any specific calculation example, or a restrictive performance of presented methodology. As adumbrated by the above described alternative solutions there are many ways of combinations and alternative executions corresponding to the presented invention. Although the embodiments and examples given above correspond more to the decimation stages and filtering steps, a corresponding implementation regarding interpolation stages and filtering steps is similar and obvious for the skilled person. The present invention can be used for reducing (decimating) as well as increasing (interpolating) the sample rate of a time discrete signal. Further, in general, several decimation and/or interpolation filters can be involved in the corresponding stages of the sample rate conversion. Thus, the present invention is not limited to the filters given in the above presented embodiments and examples. Furthermore, the preferred embodiments may vary within the scope of the attached claims.

Claims

CLAIMS:

1. A method for sample rate conversion, comprising a step of combining steps of decimation and/or interpolation, wherein the step of combining steps of decimation and/or interpolation (HBF, DF, FDS, TF, CF) comprises: a first step of decimation and/or interpolation, where the sample rate conversion is performed with a first factor; and at least one further step of decimation and/or interpolation, where the sample rate conversion is performed with at least one corresponding further factor.

2. A method according to any of preceding claims, where at least one step of decimation and/or interpolation comprises at least one sub step of decimation and/or interpolation.

3. A method according to claim 2, where at least one sub step of decimation and/or interpolation comprises at least one further sub step of decimation and/or interpolation.

4. A method according to any of claims 2 - 3, where a step or sub step of decimation and/or interpolation (FDS) comprises: a first sub step of decimation and/or interpolation (TF), where the sample rate conversion is performed with a first factor; and at least one further sub step of decimation and/or interpolation (HBF), where the sample rate conversion is performed with at least one corresponding further factor.

5. A method according to any one of preceding claims, where said first factor is a factor between one and two and/or where said at least one further factor is a factor of two.

6. A method according to any one of claims 1 - 4, where said first factor is a factor of two and/or where said at least one further factor is a factor two between one and two.

7. A method according to any one of claims 2 - 6, where a lowest decimation and/or interpolation factor used in the method has a value of one and/or where a highest decimation and/or interpolation factor used in the method is given by 2^β+1 whereas Q denotes the number of decimation and/or interpolation steps comprising sub steps performed with a factor of two.

8. A method according to any one of preceding claims, where the step of combining steps of decimation and/or interpolation comprises a step of fractional decimation and/or interpolation (FDS).

9. A method according to any one of preceding claims, where the method comprises a step of signal selecting filtering (TCF).

10. A method according to claim 8 and 9, where the step of fractional decimation and/or interpolation (FDS) is performed before signal selecting filtering (TCF).

11. A method according to any one of claims 9 - 10, where the step of signal selecting filtering (TCF) is a step of channel filtering.

12. A method according to any one of claims 9 - 10, where the step of signal selecting filtering (TCF) is a step of impulse shaping filtering.

13. A method according to any one of claims 9 - 12, where the root-raised cosine filter is used in the step of signal selecting filtering (TCF).

14. A method according to any one of claims 9 - 13, where the step of signal selecting filtering (TCF) operates at an over- sampling factor.

15. A method according to claim 14, where the over- sampling factor is adjusted to a fixed value before the step of signal selecting filtering (TCF).

16. A method according to claim 15, where the fixed value of the over- sampling factor is independent of the ratio between signal bandwidth and clocking frequency.

17. A method according to any of claims 14 - 16, where the over-sampling factor has a value obtained by division of the sample rate by signal bandwidth.

18. A method according to any one of preceding claims 9 - 17, where the sample rate conversion is performed before the step of signal selecting filtering (TCF).

19. A method according to any one of preceding claims 9 - 18, where the sample rate conversion is performed after the step of signal selecting filtering (TCF).

20. A computer program product comprising code means for performing the steps of any one of method claims 1 to 19 when run on a computer controlled device.

21. A system for sample rate conversion, comprising means for combining means for decimation and/or interpolation, the means for combining means for decimation and/or interpolation comprising: a first means for decimation and/or interpolation, where the sample rate conversion is performed with a first factor; and at least one further means for decimation and/or interpolation, where the sample rate conversion is performed with at least one corresponding further factor.