WO2007109265A2 - Iii-nitrite power semiconductor device - Google Patents

Iii-nitrite power semiconductor device Download PDF

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Publication number
WO2007109265A2
WO2007109265A2 PCT/US2007/006903 US2007006903W WO2007109265A2 WO 2007109265 A2 WO2007109265 A2 WO 2007109265A2 US 2007006903 W US2007006903 W US 2007006903W WO 2007109265 A2 WO2007109265 A2 WO 2007109265A2
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WO
WIPO (PCT)
Prior art keywords
semiconductor device
nitride
power
comprised
gate arrangement
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Ceased
Application number
PCT/US2007/006903
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French (fr)
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WO2007109265A3 (en
WO2007109265B1 (en
Inventor
Thomas Herman
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Infineon Technologies Americas Corp
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International Rectifier Corp USA
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Publication date
Application filed by International Rectifier Corp USA filed Critical International Rectifier Corp USA
Priority to US12/162,749 priority Critical patent/US9391185B2/en
Priority to DE112007000668T priority patent/DE112007000668B4/en
Priority to JP2009501508A priority patent/JP5298006B2/en
Priority to CN2007800115658A priority patent/CN101410975B/en
Publication of WO2007109265A2 publication Critical patent/WO2007109265A2/en
Publication of WO2007109265A3 publication Critical patent/WO2007109265A3/en
Publication of WO2007109265B1 publication Critical patent/WO2007109265B1/en
Anticipated expiration legal-status Critical
Priority to US15/191,222 priority patent/US9923052B2/en
Priority to US15/191,863 priority patent/US10340333B2/en
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H10D30/4755—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6738—Schottky barrier electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/675—Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/824—Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/64—Electrodes comprising a Schottky barrier to a semiconductor

Definitions

  • Hi-nitride refers to a semiconductor alloy from the InAlGaN system that includes at least nitrogen and another alloying element from group IE.
  • AIN, GaN, AlGaN, InGaN, InAlGaN, or any combination that includes nitrogen and at least one element from group IH are examples of HL-nitride alloys.
  • a conventional IH-nitride power semiconductor device includes a Hi-nitride heterojunction body 10.
  • Dl-nitride heteroj unction body 10 includes first HI- nitride semiconductor body 12 formed with one HQ-iiitride semiconductor alloy (e.g. GaN) and second HH-nitride semiconductor body 14 on body 12 formed with another Hi-nitride semiconductor alloy having a band gap different from that of first Dl-nitride semiconductor body 12 (e.g. AlGaN).
  • 2-DEG 16 so generated is rich in carriers and serves as a conductive channel between a first power electrode 18 (e.g. source electrode) which is ohmically coupled to second IH-nitride body 14 and second power electrode 20 (e.g. drain electrode) which is also ohmically coupled to second Hi-nitride body 14.
  • first power electrode 18 e.g. source electrode
  • second power electrode 20 e.g. drain electrode
  • a gate arrangement 22 is disposed between first 18 and second 20 power electrodes, which may reside on second IH-nitride body
  • Gate arrangement 22 may include a schottky body in schottky contact with second Hi-nitride body 14, or alternatively may include a gate insulation body and a gate electrode capacitively coupled to 2-DEG 16 through the gate insulation.
  • Hi-nitride heterojunction 10 in a conventional design, is disposed over a substrate
  • a transition body 30 is disposed between substrate 28 and heterojunction 10.
  • a passivation body 32 through which electrodes 18, 20 are in contact with body 14 may be also provided to protect the active portion of heterojunction 10.
  • Fig. 3 illustrates schematically electric field lines 24 near the edges of gate arrangement 22 of a device according to Fig. 1.
  • a field plate 26 is provided that extends laterally from, for example, the gate electrode of the device over passivation body 32 toward a power electrode
  • field plate 26 reduces the strength of the electric field at the edge of gate arrangement 22 by spreading the field lines 27 as illustrated schematically in Fig. 4.
  • field plate 26 can reduce the intensity of the electric field and improve the breakdown voltage of the device it is disadvantageous because:
  • the peak electric field at the edges and corners of the gate are reduced by selectively reducing the mobile charge concentration in the conducting 2-DEG.
  • the mobile charge concentration is reduced in a region that is disposed under the gate and extends laterally equal to or greater than the width of the gate, but the mobile charge concentration is otherwise held very high to keep the parasitic source-drain series resistance to a low value.
  • a power semiconductor device includes a first
  • Hi-nitride body and disposed on the first Hi-nitride body to form a Ul-nitride heteroj unction, a first power electrode coupled to the second IE-nitride body, a second power electrode coupled to the second IE-nitride body, a gate arrangement disposed between the first and the second power electrodes, and a conductive channel that includes a two-dimensional electron gas that in a conductive state includes a reduced charge region under the gate arrangement that is less conductive than its adjacent regions.
  • an implanted region in the second lH-nitride body under the gate arrangement is configured to cause the reduced charge region.
  • the gate arrangement is received in a recess over the reduced charge region, which causes the reduced charge region.
  • Fig. 1 illustrates a cross-sectional portion of the active region of a m-nitride device according to the prior art.
  • Fig. 2 illustrates a cross-sectional portion of the active region of another Hi-nitride device according to the prior art.
  • Fig. 3 illustrates schematically the electric field lines near the gate of a device according to Fig. 1.
  • Fig. 4 illustrates schematically the electric field lines near the gate of the device according to Fig. 2.
  • Fig. 5 illustrates a cross-sectional portion of the active region of a Hi-nitride device according to the first embodiment of the present invention.
  • Fig. 6 illustrates a cross-sectional portion of the active region of a Hi-nitride device according to the second embodiment of the present invention.
  • Fig. 7 illustrates a cross-sectional portion of the active region of a El-nitride device according to the third embodiment of the present invention.
  • Fig. 8 illustrates a cross-sectional portion of the active region of a Hi-nitride device according to the fourth embodiment of the present invention.
  • Figs. 9A-9C illustrates various embodiments of the present invention.
  • 2-DEG 16 includes a reduced charge region 34 which resides under gate arrangement 22.
  • Reduced charge region 34 is preferably twice as wide as gate arrangement 22, may extend beyond at least one edge of gate arrangement 22, and is less conductive than adjacent regions of 2-DEG 16 when the 2-DEG is in the conductive state. That is, in the on state (when there is conduction between the power electrodes 18, 29), region 34 include fewer carriers than regions of 2-DEG 16 adjacent each side thereof. As a result, the electric fields near the edges of gate arrangement 22 during the off state of the device are weaker compared to the prior art, which may allow for the omission of the field plate.
  • reduced charge region 34 does not need to be positioned symmetrically relative to first (source) and second (drain) power electrodes 18, 20 or with respect to gate arrangement 22.
  • reduced charge region 34 may be discontinuous and arranged in two portions 34' 34" each at one side of gate arrangement 22 (Fig. 9A), may extend farther in the direction of the drain electrode (Fig. 9B), or may only extend in direction of the drain electrode (Fig. 9C) and include no portion extending beyond gate arrangement 22 toward the source electrode.
  • the width of region 34 can be optimized and is expected to be between few tens to a few thousands of nanometers.
  • gate arrangement 22 includes a schottky body 36, which is schottky coupled to second Ul-nitride body 14.
  • Schottky body 36 may be any suitable schottky metal, for example, a nickel/gold stack, wherein the gold is atop the nickel.
  • gate arrangement 22 includes gate insulation body 38 on second IH-nitride body 14, and gate electrode 40, which is capacitively coupled to 2-DEG 16 (and particularly to reduced charge region 34) through insulation 38.
  • Gate insulation body 38 may be composed of silicon nitride, silicon dioxide, or any suitable gate insulation, while gate electrode 40 may be composed of any metallic or non-metallic conductive material. Examples of suitable materials for gate electrode 40 are nickel, titanium tungsten, titanium nitride, and polysilicon.
  • negative charge may be introduced into second Dl-nitride body 14 to repel negative carriers (electrons) in the region 34 below gate arrangement 22.
  • the negative charge may be introduced by implantation of negatively charged ions or by plasma surface treatment.
  • recess 42 may be formed in second IH-nitride body 14 in which gate arrangement 22 is received.
  • the depth and the width of recess 42 can be configured to partially relieve the stress in second Ul-nitride body 14 so that a reduced charge region 34 according to the present invention can be obtained.
  • recess 42 can be as wide as gate arrangement 22, but may be wider (as schematically illustrated) without deviating from the scope and the spirit of the present invention.
  • a field plate may be added to further enhance the breakdown capability of a device according to the present invention without deviating from the scope and spirit of the invention.
  • first and second power electrodes 18, 20 may be composed of Ti, Al, Ni, Au, or any other suitable metallic or non- metallic conductive material
  • first HH-nitride body 12 may be composed of GaN
  • second IE- nitride body 14 may be composed of AlN
  • transition layer 30 may be composed of a HI- nitride material such as AlGaN
  • substrate 28 may be composed of silicon.
  • suitable substrate materials are silicon carbide, or sapphire, or a material native to the IH-nitride system, such as a GaN substrate.

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  • Junction Field-Effect Transistors (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

A III-nitride power semiconductor device that includes a two dimensional electron gas having a reduced charge region under the gate thereof.

Description

m-NTTRIDE POWER SEMICONDUCTOR DEVICE
RELATED APPLICATION
[0001] This application is based on and claims priority to the of United States Provisional Application Serial No. 60/784,054, filed on 20 March 2006 and U.S. Patent Application Serial No. (to be assigned), filed 19 March 2007, the entire disclosures of which are incorporated herein by reference.
DEFINITION
[0002] Hi-nitride (or IH-N) as used herein refers to a semiconductor alloy from the InAlGaN system that includes at least nitrogen and another alloying element from group IE. AIN, GaN, AlGaN, InGaN, InAlGaN, or any combination that includes nitrogen and at least one element from group IH are examples of HL-nitride alloys.
BACKGROUND OF THE INVENTION
[0003] Referring to Fig. 1, a conventional IH-nitride power semiconductor device includes a Hi-nitride heterojunction body 10. Dl-nitride heteroj unction body 10 includes first HI- nitride semiconductor body 12 formed with one HQ-iiitride semiconductor alloy (e.g. GaN) and second HH-nitride semiconductor body 14 on body 12 formed with another Hi-nitride semiconductor alloy having a band gap different from that of first Dl-nitride semiconductor body 12 (e.g. AlGaN).
[0004] As is known, the composition and thickness of each El-nitride semiconductor body
12, 14 is selected to generate a two-dimensional electron gas 16 (2-DEG) at the heterojunction of the two bodies 12, 14.
[0005] 2-DEG 16 so generated is rich in carriers and serves as a conductive channel between a first power electrode 18 (e.g. source electrode) which is ohmically coupled to second IH-nitride body 14 and second power electrode 20 (e.g. drain electrode) which is also ohmically coupled to second Hi-nitride body 14. To control the state of conductivity between first power electrode 18 and second power electrode 20, a gate arrangement 22 is disposed between first 18 and second 20 power electrodes, which may reside on second IH-nitride body
14. Gate arrangement 22, for example, may include a schottky body in schottky contact with second Hi-nitride body 14, or alternatively may include a gate insulation body and a gate electrode capacitively coupled to 2-DEG 16 through the gate insulation.
[0006] Hi-nitride heterojunction 10, in a conventional design, is disposed over a substrate
28. Typically, a transition body 30 is disposed between substrate 28 and heterojunction 10.
A passivation body 32 through which electrodes 18, 20 are in contact with body 14 may be also provided to protect the active portion of heterojunction 10.
[0007] It has been observed that high electric field build-up near the gate arrangement results in gate breakdown (particularly at the edge closest to the drain electrode of the device).
Other disadvantages include low drain-source breakdown voltage, and time dependent degradation of device parameters due to hot carriers and charge trapping. Fig. 3 illustrates schematically electric field lines 24 near the edges of gate arrangement 22 of a device according to Fig. 1.
[0008] Referring to Fig. 2, to improve the capability of a IE-nitride device to withstand breakdown at the edges of its gate, a field plate 26 is provided that extends laterally from, for example, the gate electrode of the device over passivation body 32 toward a power electrode
(e.g. drain electrode) of the device. The provision of field plate 26 reduces the strength of the electric field at the edge of gate arrangement 22 by spreading the field lines 27 as illustrated schematically in Fig. 4.
[0009] While field plate 26 can reduce the intensity of the electric field and improve the breakdown voltage of the device it is disadvantageous because:
[0010] 1. it increases the active area of the device;
[0011] 2. while it causes the movement of the point of high electric field to the edge of field plate 25, it may still allow changes to occur;
[0012] 3. the increase gate-drain overlap capacitance degrades high frequency switching and increases switching losses, which is worsened by the Miller Effect. SUMMARY OF THE INVENTION
[0013] In a device according to the present invention the peak electric field at the edges and corners of the gate are reduced by selectively reducing the mobile charge concentration in the conducting 2-DEG.
[0014] According to one aspect of the present invention the mobile charge concentration is reduced in a region that is disposed under the gate and extends laterally equal to or greater than the width of the gate, but the mobile charge concentration is otherwise held very high to keep the parasitic source-drain series resistance to a low value.
[0015] A power semiconductor device according to the present invention includes a first
Hi-nitride body and a second IH-nitride body having a different band gap than that of the first
Hi-nitride body and disposed on the first Hi-nitride body to form a Ul-nitride heteroj unction, a first power electrode coupled to the second IE-nitride body, a second power electrode coupled to the second IE-nitride body, a gate arrangement disposed between the first and the second power electrodes, and a conductive channel that includes a two-dimensional electron gas that in a conductive state includes a reduced charge region under the gate arrangement that is less conductive than its adjacent regions.
[0016] In one embodiment, an implanted region in the second lH-nitride body under the gate arrangement is configured to cause the reduced charge region.
[0017] In another embodiment, the gate arrangement is received in a recess over the reduced charge region, which causes the reduced charge region.
[0018] Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Fig. 1 illustrates a cross-sectional portion of the active region of a m-nitride device according to the prior art. [0020] Fig. 2 illustrates a cross-sectional portion of the active region of another Hi-nitride device according to the prior art.
[0021] Fig. 3 illustrates schematically the electric field lines near the gate of a device according to Fig. 1.
[0022] Fig. 4 illustrates schematically the electric field lines near the gate of the device according to Fig. 2.
[0023] Fig. 5 illustrates a cross-sectional portion of the active region of a Hi-nitride device according to the first embodiment of the present invention.
[0024] Fig. 6 illustrates a cross-sectional portion of the active region of a Hi-nitride device according to the second embodiment of the present invention.
[0025] Fig. 7 illustrates a cross-sectional portion of the active region of a El-nitride device according to the third embodiment of the present invention.
[0026] Fig. 8 illustrates a cross-sectional portion of the active region of a Hi-nitride device according to the fourth embodiment of the present invention.
[0027] Figs. 9A-9C illustrates various embodiments of the present invention.
DETAILED DESCRIPTION OF THE EMBODIMENTS
[0028] Referring to Fig. 5 in which like numerals identify like features, in a device according to the present invention 2-DEG 16 includes a reduced charge region 34 which resides under gate arrangement 22. Reduced charge region 34 is preferably twice as wide as gate arrangement 22, may extend beyond at least one edge of gate arrangement 22, and is less conductive than adjacent regions of 2-DEG 16 when the 2-DEG is in the conductive state. That is, in the on state (when there is conduction between the power electrodes 18, 29), region 34 include fewer carriers than regions of 2-DEG 16 adjacent each side thereof. As a result, the electric fields near the edges of gate arrangement 22 during the off state of the device are weaker compared to the prior art, which may allow for the omission of the field plate. Note that reduced charge region 34 does not need to be positioned symmetrically relative to first (source) and second (drain) power electrodes 18, 20 or with respect to gate arrangement 22. Thus, reduced charge region 34may be discontinuous and arranged in two portions 34' 34" each at one side of gate arrangement 22 (Fig. 9A), may extend farther in the direction of the drain electrode (Fig. 9B), or may only extend in direction of the drain electrode (Fig. 9C) and include no portion extending beyond gate arrangement 22 toward the source electrode. The width of region 34 can be optimized and is expected to be between few tens to a few thousands of nanometers.
[0029] In a device, according to the embodiment shown by Fig. 5, gate arrangement 22 includes a schottky body 36, which is schottky coupled to second Ul-nitride body 14. Schottky body 36 may be any suitable schottky metal, for example, a nickel/gold stack, wherein the gold is atop the nickel.
[0030] Referring to Fig. 6, in which like numerals identify like features, in an alternative embodiment, gate arrangement 22 includes gate insulation body 38 on second IH-nitride body 14, and gate electrode 40, which is capacitively coupled to 2-DEG 16 (and particularly to reduced charge region 34) through insulation 38. Gate insulation body 38 may be composed of silicon nitride, silicon dioxide, or any suitable gate insulation, while gate electrode 40 may be composed of any metallic or non-metallic conductive material. Examples of suitable materials for gate electrode 40 are nickel, titanium tungsten, titanium nitride, and polysilicon. [0031] To obtain reduced charge region 34 in the embodiments according to Figs. 5 and 6, negative charge may be introduced into second Dl-nitride body 14 to repel negative carriers (electrons) in the region 34 below gate arrangement 22. The negative charge may be introduced by implantation of negatively charged ions or by plasma surface treatment. [0032] Referring now to Figs. 7 and 8, in which like numerals identify like features, to form reduced charge region 34 according to an alternative embodiment, recess 42 may be formed in second IH-nitride body 14 in which gate arrangement 22 is received. [0033] The depth and the width of recess 42 can be configured to partially relieve the stress in second Ul-nitride body 14 so that a reduced charge region 34 according to the present invention can be obtained. Note that recess 42 can be as wide as gate arrangement 22, but may be wider (as schematically illustrated) without deviating from the scope and the spirit of the present invention.
[0034] Note that although the provision of a reduced charge region 34 according to the present invention may allow for the omission of a field plate, a field plate may be added to further enhance the breakdown capability of a device according to the present invention without deviating from the scope and spirit of the invention.
[0035] Other methods for obtaining a reduced charge region 34 are surface plasma treatment, surface chemical treatment, and deposition of a suitable thin film. [0036] In a device according to the preferred embodiment, first and second power electrodes 18, 20 may be composed of Ti, Al, Ni, Au, or any other suitable metallic or non- metallic conductive material, first HH-nitride body 12 may be composed of GaN, second IE- nitride body 14, may be composed of AlN, transition layer 30 may be composed of a HI- nitride material such as AlGaN, and substrate 28 may be composed of silicon. Other suitable substrate materials are silicon carbide, or sapphire, or a material native to the IH-nitride system, such as a GaN substrate.
[0037] Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein, but only by the appended claims.

Claims

WHAT IS CLAIMED IS:
1. A power semiconductor device, comprising: a Hi-nitride heteroj unction body that includes a first Hi-nitride body and a second ID-nitride body having a different band gap than that of said first IQ-nitride body; a first power electrode coupled to said second IH-nitride body; a second power electrode coupled to said second IH-nitride body; a gate arrangement disposed between said first and said second power electrodes; and a conductive channel that includes a two-dimensional electron gas that in a conductive state includes a reduced charge region under said gate arrangement that is less conductive than its adjacent regions.
2. The power semiconductor device of claim 1, wherein said gate arrangement includes a gate insulation body.
3. The power semiconductor device of claim 1, wherein said gate arrangement includes a schottky body.
4. The power semiconductor device of claim 1, wherein said gate arrangement is received in a recess over said reduced charge region.
5. The power semiconductor device of claim 4, wherein said recess is configured to cause said reduced charge region.
6. The power semiconductor device of claim 4, wherein said recess is wider than said gate arrangement.
7. The power semiconductor device of claim 1, further comprising at least one implanted region in said second Hi-nitride body under said gate arrangement configured to cause said reduced charge region.
8. The power semiconductor device of claim 1, wherein said gate arrangement does not include a field plate.
9. The power semiconductor device of claim 1, further comprising a passivation body disposed over said m-nitride heterojunction body.
10. The power semiconductor device of claim 1, wherein said first Hi-nitride body is comprised of a semiconductor alloy from the InAlGaN system, and said second Hi-nitride body is comprised of another alloy from the InAlGaN system.
11. The semiconductor device of claim 1, wherein said first IQ-nitride body is comprised of GaN and said second Hi-nitride body is comprised of AlGaN.
12. The semiconductor device of claim 1, wherein said heterojunction body is disposed over a substrate.
13. The semiconductor device of claim 12, wherein said substrate is comprised of silicon.
14. The semiconductor device of claim 12, wherein said substrate is comprised of silicon carbide.
15. The semiconductor device of claim 12, wherein said substrate is comprised of sapphire.
16. The semiconductor device of claim 12, wherein said substrate is comprised of a El-nitride material.
17. The semiconductor device of claim 16, wherein said IE-nitride material is GaN.
18. The semiconductor device of claim 12, further comprising a transition body disposed between said substrate and said IH-nitride heteroj unction body.
19. The semiconductor device of claim 18, wherein said transition body is comprised of a IH-nitride material.
20. The semiconductor device of claim 19, wherein said transition body is comprised of AlN.
21. The semiconductor device of claim 1, wherein said reduced charge region extends beyond an edge of said gate arrangement toward one of said power electrodes only.
22. The semiconductor device of claim 1, wherein said reduced charge region extends farther toward one power electrode than the other power electrode.
23. The semiconductor device of claim 1, wherein said reduced charge region is discontinuous.
PCT/US2007/006903 2006-03-20 2007-03-20 Iii-nitrite power semiconductor device Ceased WO2007109265A2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
US12/162,749 US9391185B2 (en) 2006-03-20 2007-03-20 III-nitride power semiconductor device
DE112007000668T DE112007000668B4 (en) 2006-03-20 2007-03-20 Group III-nitride power semiconductor component
JP2009501508A JP5298006B2 (en) 2006-03-20 2007-03-20 III-nitride power semiconductor devices
CN2007800115658A CN101410975B (en) 2006-03-20 2007-03-20 Group III-Nitride Power Semiconductor Devices
US15/191,222 US9923052B2 (en) 2006-03-20 2016-06-23 III-nitride power semiconductor device
US15/191,863 US10340333B2 (en) 2006-03-20 2016-06-24 III-nitride power semiconductor device

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US78405406P 2006-03-20 2006-03-20
US60/784,054 2006-03-20
US11/725,430 2007-03-19
US11/725,430 US7408208B2 (en) 2006-03-20 2007-03-19 III-nitride power semiconductor device

Related Parent Applications (2)

Application Number Title Priority Date Filing Date
US11/725,430 Continuation-In-Part US7408208B2 (en) 2006-03-20 2007-03-19 III-nitride power semiconductor device
US11/725,430 Continuation US7408208B2 (en) 2006-03-20 2007-03-19 III-nitride power semiconductor device

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US7408208B2 (en) 2008-08-05
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DE112007000668T5 (en) 2009-01-29
CN101410975A (en) 2009-04-15

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