WO2007102781A1 - Method for metal-free synthesis of epitaxial semiconductor nanowires on si - Google Patents
Method for metal-free synthesis of epitaxial semiconductor nanowires on si Download PDFInfo
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- WO2007102781A1 WO2007102781A1 PCT/SE2007/050131 SE2007050131W WO2007102781A1 WO 2007102781 A1 WO2007102781 A1 WO 2007102781A1 SE 2007050131 W SE2007050131 W SE 2007050131W WO 2007102781 A1 WO2007102781 A1 WO 2007102781A1
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- Prior art keywords
- substrate
- nanowires
- growth
- oxide template
- residues
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Classifications
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
Definitions
- the present invention relates to a method of growing III-V semiconductor nanowires on a silicon substrate.
- the invention relates to a method of growing nanowires without using Au, or any other metal, as a catalyst.
- Nanowires are also referred to as nanowhiskers, nanorods and nanocolumns etc.
- nanowire is used for a nanostructure that include one-dimensional nanoelements, essentially in one-dimensional form, that are of nanometer dimensions in their width or diameter. Controlling the one-dimensional growth on the nanometer scale offers unique opportunities for combining materials, manipulating properties, both mechanical and electromagnetical, and to design novel devices.
- III-V semiconductors on Si presents several difficulties such as lattice mismatch, differences in crystal structure (III-Vs have a polar zincblende or wurtzite structure whereas Si has a covalent diamond structure), a large difference in thermal expansion coefficient and the formation of so called anti-pahse domains.
- the object of the present invention is to provide a method that overcomes the drawbacks of the prior art methods. This is achieved by the method as defined in claim 1.
- the method according to the invention provides a nanostructured devices which comprises a nanowire epitaxially grown from a surface of a substrate.
- the method comprises the steps of:
- the oxide template defines a plurality of nucleation onset positions for the subsequent nanowire growth
- the oxide template is according to one embodiment self-assembled or produced in a process wherein a self-assembled thin layer of another material is utilized in the formation of the oxide template.
- the step of providing an oxide template comprises:
- Au or other materials recognized as hazardous by the silicon industry can be avoided as catalyst materials in the growth of nanowires or nanostructures.
- Si surfaces can be treated to produce epitaxially oriented compound nanowires using epitaxy growth systems.
- Such epitaxial NW can e.g. be used for high speed electronics and photonics.
- One advantage of the invention is that the steps of the method can be easily adapted to industrial batch processing.
- a further advantage is that the method of growing nanowires according to the invention can be combined with modern nanolithography techniques.
- Figure 1 is a schematic illustration of the steps according to the method of the invention
- Figure 2 illustrates the resulting nanowires grown on a Si(IOO) substrate using the method according to the invention
- Figure 3 illustrates the resulting nanowires grown using one embodiment of the method according to the invention
- Figure 4 is a flowchart over one embodiment of the method of the invention using a thin organic film in forming an oxide template
- Figure 5 is a schematic illustration of the steps according to the method of the invention using a thin organic film in forming an oxide template ;
- Figure 6a-c Illustrates the effect of the nucleation onset period
- Figure 7a-d illustrates InAs nanowires grown according to the method of the invention using the organic compounds: a) allyl alcohol, b) n-decane, c) acetone, d) ethanol;
- Figure 8a-b illustrates the effect of the pre-heating according to one embodiment of the invention, (a) without pre-heating and (b) with preheating.
- a general method is provided to produce epitaxial nanowires of III-V materials, without using Au-particles as catalyst.
- the method is described with InAs as the primary material in the Nanowires.
- InAs has one of the highest electron mobility within the family of III-V compounds and is therefore very interesting for electronic applications of nanowires. It has been shown that InAs nanowires can easily be contacted and gated. With inbuilt barriers (e.g. InP), the functionality of such structures in single electron transistors as described by C. Thelander et al., Appl Phys. Lett.
- Si is for most applications the preferred choice of substrate material, due to the electronic properties and not at least, to the well established methods of using Si in large scale production.
- the nanowires grow in the ⁇ 111 > direction with an epitaxial relation to the substrate.
- the nanowires are directed normal to the surface, for a Si(OOl) surface the nanowires form an angle of approximately 35 degrees with the surface etc.
- the method according to the invention is optimized, but not limited, for the use of a Si(l l l)-substrate.
- the method according to the invention is applicable also to other substrates, for example substrates of III-V compounds could be of interest for some applications. Modifications of the method to accommodate for various substrates materials are obvious for the skilled in the art.
- nanowire growth on the Si substrate is guided by an oxide template provided on the Si surface in a pre- treatment, prior to the growth process.
- the oxide template guides the nanowire nucleation by increasing the probability of nucleation in certain areas of the substrate. These areas of increased probability of nucleation will be referred to as nucleation onset positions.
- the method according to the invention is schematically illustrated in FIG.1 and comprises the basic steps of:
- the HF etching removes native oxides 105 from the surface of the Si(I I l) substrate 100 and provides a substrate with a temporarily passivated surface 110.
- the oxide template defining a plurality of nucleation onset positions for subsequent nanowire growth.
- the oxide template can be provided in different ways which will be described below.
- the oxide template can provide nucleation onset positions by the oxide forming localised patches of silicon oxide which subsequently acts as catalyst particles for the onset of nanowire growth.
- the composition in the localised patches is preferably and typically SiO x , x ⁇ l.
- the oxide template forms a growth inhibiting mask, the mask typically being fully oxidised, Si ⁇ 2. Nucleation onset positions are provided as less oxidised, or non-oxidised, patches in the growth inhibiting mask. In this case the subsequent growth of nanowires would occur in the patches wherein the surface of the substrate is less oxidised.
- the oxide template is self-assembled, i.e. the structure of the oxide template is primarily formed spontaneously.
- self-assembled oxide template should also be understood to include an oxide template wherein the self- assembled characteristics are provided in a process including that another substance, for example an organic compound, has a self-assembled structured that is at least partly transferred to the oxide template.
- the self- assembling process may be influenced by the environment, the temperature, the material in the substrate and the substrate surface etc. This embodiment will promote a subsequent growth of nanowires at random positions on the substrate surface.
- the oxide template may be given a structure by patterning, for example using lithographic methods. According to this embodiment the growth of nanowires will be at pre-determined positions.
- the oxide template 115 is directly provided on the passivated substrate surface.
- the embodiment comprises a pre-treatment of applying a thin layer of a volatile species, for example and preferable SiO x (x ⁇ l), on the substrate prior to the growth procedure.
- the thin layer of a volatile species forms the oxide template 115 either as a catalyst layer or as a growth inhibiting mask.
- the structure of the oxide template may be formed directly at the application of the thin layer, or alternatively, through a subsequent treatment of the thin layer, for example by highering the temperature.
- the basic steps of the method according to the invention is modified according to:
- c 5 during the growth phase provide conditions as regard to time, pressure and temperature, ensuring that the nucleation of nanowires is guided by the oxide template 115.
- the oxide template may undergo changes during the growth phase, for example evaporate partly, or restructure due to the increased temperature.
- the method of the embodiment may be further refined by ensuring that the nucleation of nanowires take place prior to any significant re-structuring of the oxide template 115.
- Step c 7 then comprises:
- c': l providing a first condition wherein the source for the nanowire growth is turned on at a substrate temperature lower than a pre-determined temperature associated to the oxide template.
- the pre-determined temperature is chosen so that no significant re-structuring of the oxide template occurs in the time-frame of the step.
- the pre-determined temperature is typically lower than an optimized nanowire growth temperature, but high enough to facilitate an onset of the nucleation of nanowires.
- c':2 providing a second condition wherein the temperature of the substrate is optimised for promoting the growth of the nanowires.
- the second temperature is typically higher than the first temperature. Due to that the nucleation have started in the previous step, changes to the oxide template will have low impact on the growth of the nanowires.
- An implementation example according to the embodiments utilizing a direct deposition of the oxide template may comprise the following process: For wire-growth a low pressure metal organic vapor phase epitaxy (LP- MOVPE) was used at a pressure of 10 kPa, with trimethylindium (TMI), arsine (AsH ⁇ ), and phosphine (PH3) as precursor materials, transported in a flow of 6000 ml/min of H2 as carrier gas. For the precursors typical molar fractions of 2*10- 6 for TMI and 2* 10- 4 for AsH 3 were used. For TMI, also higher molar fractions were tested, but had no significant effect on the growth rate.
- LP- MOVPE low pressure metal organic vapor phase epitaxy
- TMI trimethylindium
- AsH ⁇ arsine
- PH3 phosphine
- the molar fraction for PH3 was varied in the range (3.5 -15) XlO 3 .
- substrates epitaxy-ready III/V wafers and Si wafers were used.
- the native oxide was removed by an HF dip, corresponding to step a).
- a thin SiO x layer was sublimated onto the surface, corresponding to step b 5 ).
- the substrates were then heated to the growth temperature between 520 0 C and 680 0 C in a H2 atmosphere. As soon as the growth temperature was reached, the precursors were switched on simultaneously. The growth was stopped by switching off the TMI source, and the samples were cooled under ASH3 flow, or for InAsP deposition, under additional PH3 flow. Resulting nanowires grown on Si(IOO) are shown in FIG. 2.
- the use of an oxide template is combined with a patterning method, for example a lithographic method, to produce a defined pattern, for example an array or matrix of nanowires.
- the pattern can be prepared by conventional lithographic methods, for example electron beam lithography.
- the pattern was prepared by spinning PMMA onto the InP(I I l)B substrates, and writing a regular array of dots using electron beam lithography. Si substrates are treated the same way. After developing the positive resist to open up apertures down to the substrate, the SiO x layer was deposited, and the remaining resist was removed in a lift-off process.
- the sources had to be activated already during the heating-up period at 510 - 520 0 C. Activating the sources later, i.e., at higher growth temperatures, leads to a loss of the pattern. This has most probably to do with the thermal stability of SiO x , which evaporates markedly at temperatures above 500 0 C. Scanning tunneling microscopy investigations at temperatures of around 500 0 C have shown that a 1.3 nm thick SiO x layer evaporates in time scales comparable to our growth times of several minutes.
- the oxide template 115 is provided by a controlled oxidation process.
- a thin organic film is applied to the passivated surface, for example allyl alcohol (2-propen-l-ol).
- organic materials such as acetone and n-decane can be used.
- the thin organic film should, at least at some part of the pre-treatment, be semi-permeable to substances that could affect the surface of the Si substrate. Suitable thin film thickness will be dependent on the organic compound used, on the time scale of the pre-treatment and the conditions wherein the pre-treatment is performed, as regards to for example humidity. Typical thin film thicknesses is in the range 10-200 A.
- a subsequent part of the pre-treatment according to the embodiment of invention allows for forming of nucleation onset positions by localised alterations in the substrate surface or localised formations, or residues, on the substrate surface.
- the method of producing epitaxial nanowires on a Si substrate comprises the following main steps:
- a Hydrogen termination of the substrate surface, for example by etching in hydrofluoric acid, HF.
- the HF etching removes oxides 505 from the surface of the Si(I I l) substrate 500 and provides a substrate with a temporarily passivated surface 510.
- a HF etching procedure is utilised that produces a Si surface exhibiting at least some roughness.
- Procedures for controlling the roughness of the passivated surface of an Si(I I l) substrate depend on the pH of the HF-solution, and are well known in the art, see for example "Ideal Hydrogen Termination of the Si-(IIl) Surface" by Higashi, G. S. et al, Applied Physics Letters 56, 656-658 (1990).
- roughness in this context is on an atomic scale, the roughness achieved with the referred process is in the order of 0.3 nm. It should also be noted that the term roughness also refers to a less stable, less ideal, hydrogen termination of the substrate surface, which makes it more prone to oxidation.
- the thin film may be applied by, for example, spin coating, vaporisation, and dipping.
- the thin film typically leaves a plurality of residues 514 on the substrate surface, either by a self- assembling process or by a patterning process.
- b":2) Providing a nucleation onset period. During this period a plurality of separated nucleation onset positions 516 are formed on the surface of the substrate. The density of the nucleation onset positions as well as the size of the individual nucleation onset positions are dependent on a combination of the thin organic film characteristics and the conditions during the nucleation onset period. An oxidation of the substrate surface 510 occurs during the nucleation onset period. The oxidation is guided by the thin organic film, or residues thereof. The procedure results in an oxide template 515 defining a plurality of nucleation onset positions 516, there the structure of the oxide template has a correlation to the structure of the thin organic film, or the organic residues of the film.
- the organic thin film, applied in step b": l forms localised residues 514 on the substrate surface 510.
- the residues may form directly after the application of the thin organic film, or during the nucleation onset period due to changes of the film such as cracking or uneven evaporation.
- steps b":2 substances present in the environment may penetrate weakenings in the film, or has direct access to the surface in areas not covered by the localised residues.
- an oxidising environment for example humid air
- localised oxidation will occur in areas wherein the thin film is thin enough, or absent.
- the substrate and the thin organic film is exposed to an oxidising environment.
- An oxidising environment can be provided in many ways - a simple approach is to use the humidity in air, whereby the expected reactions would be:
- SiO 2 will cover the substrate surface, except in areas covered by organic residues 514, and forms the oxide template 515.
- the areas covered with organic residue 514 is either un-oxidised or has a lower oxidation state, for example SiO, and will form the nucleation onset positions.
- the density of nanowires grown in subsequent steps has been found to be strongly dependent on the exposure time to ambient air between applying the organic thin film onto the substrate, and loading it into the reactor cell, wherein the growth step c" is performed. According to one embodiment of the invention this effect is used to control the nanowire density by performing controlled oxidations.
- step a) providing a relatively rough Si(I I l) surface may be advantageous.
- a further optional substep, to be taken before the nanowire growth, according to the embodiment comprises:
- the thin film is arranged to leave residues during the pre-heating.
- the residues can be of various constitutions, depending on the organic thin film.
- the thin organic film can initiate the formation of carbides, SiC, on the substrate surface. Alternatively the residues alter the surface, which gives a localized increased probability of nucleation.
- the forming of areas of increased permeability, for example due to an uneven evaporation, or cracking, of the thin organic film is utilised to form essentially randomly distributed residues, which in turn provides the nucleation onset positions.
- the process is preferably performed in the same chamber as growth phase take place.
- the thin organic film is used to passivate parts of the Si surface and nucleation onset positions will be provided in the openings of the film.
- the process could be compared to providing a mask of an organic compound and lithographically, for example, form holes in the mask.
- the properties of the thin organic film in combination with providing a suitable environment "holes" are formed spontaneously as a result of the cracking or uneven evaporation of the organic thin film.
- the process of lithographically providing holes could be avoided.
- a thin organic film comprising oxidation substance or oxidation substance present on the surface is utilised in the forming of nucleation onset positions.
- growth step c,c', and c methods are known in the art.
- LP-MOVPE metal organic vapor phase epitaxy
- Other possible techniques include, but is not limited to MOVPE, Molecular Beam Epitaxy (MBE) and Chemical Beam Epitaxy (CBE). Details in a form of a non-limiting example will be given below.
- the nanowiskers have been exemplified with InAs.
- other semiconductors in particular III-V semiconductors such as InP and GaP could advantageously be grown with the method according to the invention.
- Required modifications, for examples in the LP-MOVPE process, are obvious to the skilled persons.
- suitable for use for the thin organic film 515 a large plurality of other organic compounds can be used. The selection dependent on the method of applying the film available, for example by spin coating, and preferred timescales and conditions of the nucleation onset period. Suitable organic compounds include, but is not limited to, allyl alcohol, n-decane, and acetone.
- Si(I I l) substrates were used. The wafer was diced and the samples cleaned in an ultrasonic bath. To remove organic residues the samples were subjected to an UV+ozone clean. The samples were then etched for 30s in 4% aqueous hydrofluoric acid and removed without rinsing.
- n-decane was used as the organic substance in the same manner. However, after spinning the sample was kept in a humid atmosphere for approx. 10 min period before transfer to an inert atmosphere.
- a low-pressure, 100 mbar, MOVPE system was used with TMI and arsine as precursor gases.
- a constant hydrogen carrier gas flow of 6 1/min was used.
- a 10 min anneal at 625 0 C was performed to improve the quality of the growth.
- the temperature was then ramped down to a typical growth temperature of 550 0 C. Growth was initiated when the two precursors were simultaneously introduced in the growth cell.
- typical molar fractions of 2x10 6 for TMI and 2* 10- 4 for AsHe were used. After a growth time of typically a few minutes the growth was halted by switching the TMI off. Cooling to room temperature was done under a protecting arsine flow.
- FIG 6a-b Illustrates the effect of the nucleation onset period.
- n-decane was spun and the sample directly transported to the growth apparatus.
- the sample was spun with n-decane and stored in humid air for approx. 10 min.
- the viewing angle is 45 degrees with respect to the substrate normal.
- the time of exposure of the coated substrate to an oxidising environment can be used to control the nanowire density, this is further illustrated in FIG 6c, wherein the nanowire density is a function of exposure time.
- the conditions were stable around 22-24 0 C and 85-90 % relative humidity. Whereas the 6 h sample still shows nearly ideal NW growth, the 1O h sample exhibits an increased amount of non-epitaxial wires and competing island growth. Further oxidation (>14 h under the above conditions) results in zero density, i.e. no growth.
- FIG 7a-d illustrates InAs nanowires grown according to the method of the invention using the organic compounds: a) allyl alcohol, b) n-decane, c) acetone, d) ethanol.
- the viewing angle is 45 degrees with respect to the substrate normal. It should be noted that in the figures the nanowires appearing to having an angle to the substrate is an effect of the imaging process. In reality the nanowires are epitaxial and vertically standing on the surface of the substrate.
- FIG 8a-b the effect of the optional pre-heating or annealing is illustrated.
- no pre-heating was performed prior to the growth phase.
- the substrate illustrated in (b) were annealed at 625 0 C for 10 minutes.
- the annealed substrate shows an increased growth quality.
- allyl-alcohol compared to n- decane is consistent with the fact that allyl-alcohol is hygroscopic, attracting moisture which should increase the oxidation rate, whereas n-decane is hydrophobic.
- the above procedure including a thin organic layer in the formation of the oxide template can be combined with modern nanolithography techniques such as micro-contact printing wherein a mask of organic material is transferred from a stamp to the substrate. Also techniques using scanning tunnelling microscopy such as dip-pen lithography can be used to give the organic thin film a pre-determined pattern, and hence the oxide template a corresponding pre-determined pattern.
- the basic steps of the method according to the invention can readily be implemented in an industrial production system.
- One approach is to perform all the steps of the method in the same chamber, or at least in the same system, in order to avoid uncontrolled exposure to air, humidity etc..
- the steps of the method could in this case be modified according to:
- i Introducing one or a plurality of substrate in a vacuum chamber.
- ii Hydrogen termination by the use of atomic hydrogen, for example heating the substrate(s) and exposure to hydrogen plasma.
- the voltage and the plasma composition can be used to determine surface roughness.
- v Growth of nanowires, utilizing the same vacuum chamber, or after transfer to a growth chamber in the same system.
- This modified process is well suited to combined with various patterning techniques.
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CN200780016774.1A CN101443265B (en) | 2006-03-08 | 2007-03-07 | Method for metal-free synthesis of epitaxial semiconductor nanowires on Si |
EP07716104.0A EP1991499A4 (en) | 2006-03-08 | 2007-03-07 | Method for metal-free synthesis of epitaxial semiconductor nanowires on si |
JP2008558235A JP5483887B2 (en) | 2006-03-08 | 2007-03-07 | Method for synthesis of epitaxial semiconductor nanowires on Si without metal |
KR1020087024591A KR101375435B1 (en) | 2006-03-08 | 2007-03-07 | Method for metal-free synthesis of epitaxial semiconductor nanowires on si |
US12/224,822 US8691011B2 (en) | 2006-03-08 | 2007-03-07 | Method for metal-free synthesis of epitaxial semiconductor nanowires on si |
AU2007222162A AU2007222162B2 (en) | 2006-03-08 | 2007-03-07 | Method for metal-free synthesis of epitaxial semiconductor nanowires on Si |
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US11295983B2 (en) | 2020-05-27 | 2022-04-05 | International Business Machines Corporation | Transistor having source or drain formation assistance regions with improved bottom isolation |
CN112736173B (en) * | 2021-04-06 | 2021-06-29 | 至芯半导体(杭州)有限公司 | Composite substrate, preparation method thereof and semiconductor device |
CN112802930B (en) * | 2021-04-15 | 2021-07-06 | 至芯半导体(杭州)有限公司 | Method for manufacturing group III nitride substrate and semiconductor device |
Family Cites Families (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4341605A (en) * | 1981-01-16 | 1982-07-27 | E. I. Du Pont De Nemours And Company | Process for cation permeable membrane with reinforcement fabric embedded therein and product thereof |
GB2210728B (en) * | 1987-10-07 | 1991-11-13 | Stc Plc | Isolation trenches for semiconductors |
US5976957A (en) | 1996-10-28 | 1999-11-02 | Sony Corporation | Method of making silicon quantum wires on a substrate |
CN100344004C (en) | 1997-10-30 | 2007-10-17 | 住友电气工业株式会社 | GaN single crystal substrate and method of making the same |
US6596377B1 (en) | 2000-03-27 | 2003-07-22 | Science & Technology Corporation @ Unm | Thin film product and method of forming |
WO2002080280A1 (en) | 2001-03-30 | 2002-10-10 | The Regents Of The University Of California | Methods of fabricating nanostructures and nanowires and devices fabricated therefrom |
US6709929B2 (en) | 2001-06-25 | 2004-03-23 | North Carolina State University | Methods of forming nano-scale electronic and optoelectronic devices using non-photolithographically defined nano-channel templates |
US7335908B2 (en) | 2002-07-08 | 2008-02-26 | Qunano Ab | Nanostructures and methods for manufacturing the same |
US7355216B2 (en) | 2002-12-09 | 2008-04-08 | The Regents Of The University Of California | Fluidic nanotubes and devices |
JP4428921B2 (en) | 2002-12-13 | 2010-03-10 | キヤノン株式会社 | Nanostructure, electronic device, and manufacturing method thereof |
CN1187153C (en) * | 2002-12-16 | 2005-02-02 | 同济大学 | Method for making silver nano wire using aerogel as template |
US7608147B2 (en) | 2003-04-04 | 2009-10-27 | Qunano Ab | Precisely positioned nanowhiskers and nanowhisker arrays and method for preparing them |
US7445742B2 (en) | 2003-08-15 | 2008-11-04 | Hewlett-Packard Development Company, L.P. | Imprinting nanoscale patterns for catalysis and fuel cells |
US7354850B2 (en) | 2004-02-06 | 2008-04-08 | Qunano Ab | Directionally controlled growth of nanowhiskers |
EP1766108A1 (en) | 2004-06-25 | 2007-03-28 | Btg International Limited | Formation of nanowhiskers on a substrate of dissimilar material |
US7407872B2 (en) | 2004-08-20 | 2008-08-05 | Yale University | Epitaxial growth of aligned AlGalnN nanowires by metal-organic chemical vapor deposition |
CN101065831B (en) * | 2004-08-31 | 2011-05-04 | 新加坡科技研究局 | Nanostructure and method of manufacture |
US7345296B2 (en) | 2004-09-16 | 2008-03-18 | Atomate Corporation | Nanotube transistor and rectifying devices |
US7303631B2 (en) | 2004-10-29 | 2007-12-04 | Sharp Laboratories Of America, Inc. | Selective growth of ZnO nanostructure using a patterned ALD ZnO seed layer |
US20060223211A1 (en) | 2004-12-02 | 2006-10-05 | The Regents Of The University Of California | Semiconductor devices based on coalesced nano-rod arrays |
US7309621B2 (en) | 2005-04-26 | 2007-12-18 | Sharp Laboratories Of America, Inc. | Method to fabricate a nanowire CHEMFET sensor device using selective nanowire deposition |
KR100623271B1 (en) | 2005-06-24 | 2006-09-12 | 한국과학기술연구원 | Fabrication of controlling mn doping concentration in gan single crystal nanowire |
KR101264673B1 (en) * | 2005-06-24 | 2013-05-20 | 엘지디스플레이 주식회사 | method for fabricating detail pattern by using soft mold |
US20070257264A1 (en) | 2005-11-10 | 2007-11-08 | Hersee Stephen D | CATALYST-FREE GROWTH OF GaN NANOSCALE NEEDLES AND APPLICATION IN InGaN/GaN VISIBLE LEDS |
US7349613B2 (en) | 2006-01-24 | 2008-03-25 | Hewlett-Packard Development Company, L.P. | Photonic crystal devices including gain material and methods for using the same |
JP5137095B2 (en) * | 2006-02-20 | 2013-02-06 | 国立大学法人 筑波大学 | Method for producing silicon nanocrystal material and silicon nanocrystal material produced by the production method |
WO2008048704A2 (en) | 2006-03-10 | 2008-04-24 | Stc.Unm | Pulsed growth of gan nanowires and applications in group iii nitride semiconductor substrate materials and devices |
DE102006013245A1 (en) | 2006-03-22 | 2007-10-04 | Infineon Technologies Ag | Mold layer forming method, involves forming mold layer on one of surface sections of substrate after forming template, and removing template after applying mold layer, where opening is formed in mold layer via another surface section |
US20080149946A1 (en) | 2006-12-22 | 2008-06-26 | Philips Lumileds Lighting Company, Llc | Semiconductor Light Emitting Device Configured To Emit Multiple Wavelengths Of Light |
-
2007
- 2007-03-07 US US12/224,822 patent/US8691011B2/en not_active Expired - Fee Related
- 2007-03-07 EP EP07716104.0A patent/EP1991499A4/en not_active Withdrawn
- 2007-03-07 AU AU2007222162A patent/AU2007222162B2/en not_active Ceased
- 2007-03-07 KR KR1020087024591A patent/KR101375435B1/en not_active IP Right Cessation
- 2007-03-07 JP JP2008558235A patent/JP5483887B2/en not_active Expired - Fee Related
- 2007-03-07 CN CN200780016774.1A patent/CN101443265B/en not_active Expired - Fee Related
- 2007-03-07 WO PCT/SE2007/050131 patent/WO2007102781A1/en active Application Filing
Non-Patent Citations (3)
Title |
---|
DAILY J.W. ET AL.: "Vapor-liquid-solid growth of germanium nanostructures on silicon", JOURNAL OF APPLIED PHYSICS, vol. 96, no. 12, pages 7556 - 7558, XP003013018 * |
HUI PAN ET AL.: "Single-crystal growth of metallic nanowires with preferred orientation", NANOTECHNOLOGY, vol. 16, pages 1559 - 1564, XP003013020 * |
MA D.D.D. ET AL.: "Small-Diameter Silicon Nanowire Surfaces", SCIENCE, vol. 299, pages 1874 - 1877, XP003013019 * |
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Also Published As
Publication number | Publication date |
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EP1991499A4 (en) | 2013-06-26 |
KR20080112277A (en) | 2008-12-24 |
CN101443265A (en) | 2009-05-27 |
KR101375435B1 (en) | 2014-03-17 |
JP2009532309A (en) | 2009-09-10 |
AU2007222162B2 (en) | 2013-03-07 |
US20090301389A1 (en) | 2009-12-10 |
US8691011B2 (en) | 2014-04-08 |
EP1991499A1 (en) | 2008-11-19 |
AU2007222162A1 (en) | 2007-09-13 |
JP5483887B2 (en) | 2014-05-07 |
AU2007222162A2 (en) | 2009-02-19 |
CN101443265B (en) | 2014-03-26 |
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